Mips16InstrFormats.td revision 38f85c5b9f2e2a7e1364ce44b6b8cd1ec0ffb0b3 
1//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  funct or f      Function field
16//
17//  immediate       4-,5-,8- or 11-bit immediate, branch displacement, or
18//  or imm          address displacement
19//
20//  op              5-bit major operation code
21//
22//  rx              3-bit source or destination register
23//
24//  ry              3-bit source or destination register
25//
26//  rz              3-bit source or destination register
27//
28//  sa              3- or 5-bit shift amount
29//
30//===----------------------------------------------------------------------===//
31
32
33// Base class for Mips 16 Format
34// This class does not depend on the instruction size
35//
36class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
37                      InstrItinClass itin>: Instruction
38{
39
40  let Namespace = "Mips";
41
42  let OutOperandList = outs;
43  let InOperandList  = ins;
44
45  let AsmString   = asmstr;
46  let Pattern     = pattern;
47  let Itinerary   = itin;
48
49  let Predicates = [InMips16Mode];
50}
51
52//
53// Generic Mips 16 Format
54//
55class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
56                 InstrItinClass itin>:
57  MipsInst16_Base<outs, ins, asmstr, pattern, itin>
58{
59  field bits<16> Inst;
60  bits<5> Opcode = 0;
61
62  // Top 5 bits are the 'opcode' field
63  let Inst{15-11} = Opcode;
64  
65  let Size=2;
66  field bits<16> SoftFail = 0;
67}
68
69//
70// For 32 bit extended instruction forms.
71//
72class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
73                    InstrItinClass itin>:
74  MipsInst16_Base<outs, ins, asmstr, pattern, itin>
75{
76  field bits<32> Inst;
77  
78  let Size=4;
79  field bits<32> SoftFail = 0;
80}
81
82class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
83                        InstrItinClass itin>:
84  MipsInst16_32<outs, ins, asmstr, pattern, itin>
85{
86  let Inst{31-27} = 0b11110;
87}
88
89
90
91// Mips Pseudo Instructions Format
92class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93  MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
94  let isCodeGenOnly = 1;
95  let isPseudo = 1;
96}
97
98
99//===----------------------------------------------------------------------===//
100// Format I instruction class in Mips : <|opcode|imm11|>
101//===----------------------------------------------------------------------===//
102
103class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
104           InstrItinClass itin>:
105  MipsInst16<outs, ins, asmstr, pattern, itin>
106{
107  bits<11> imm11;
108
109  let Opcode = op;
110
111  let Inst{10-0}  = imm11;
112}
113
114//===----------------------------------------------------------------------===//
115// Format RI instruction class in Mips : <|opcode|rx|imm8|>
116//===----------------------------------------------------------------------===//
117
118class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
119            list<dag> pattern, InstrItinClass itin>:
120  MipsInst16<outs, ins, asmstr, pattern, itin>
121{
122  bits<3>  rx;
123  bits<8>   imm8;
124
125  let Opcode = op;
126
127  let Inst{10-8} = rx;
128  let Inst{7-0} = imm8;
129}
130
131//===----------------------------------------------------------------------===//
132// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
133//===----------------------------------------------------------------------===//
134
135class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
136            list<dag> pattern, InstrItinClass itin>:
137  MipsInst16<outs, ins, asmstr, pattern, itin>
138{
139  bits<3>  rx;
140  bits<3>  ry;
141  bits<5>  funct;
142
143  let Opcode = 0b11101;
144  let funct  = _funct;
145
146  let Inst{10-8} = rx;
147  let Inst{7-5} = ry;
148  let Inst{4-0}   = funct;
149}
150
151//
152// For conversion functions.
153//
154class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
155               string asmstr, list<dag> pattern, InstrItinClass itin>:
156  MipsInst16<outs, ins, asmstr, pattern, itin>
157{
158  bits<3>  rx;
159  bits<3>  subfunct;
160  bits<5>  funct;
161
162  let Opcode = 0b11101; // RR
163  let funct  = _funct;
164  let subfunct = _subfunct;
165
166  let Inst{10-8} = rx;
167  let Inst{7-5} = subfunct;
168  let Inst{4-0}   = funct;
169}
170
171//
172// just used for breakpoint (hardware and software) instructions.
173//
174class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
175           list<dag> pattern, InstrItinClass itin>:
176  MipsInst16<outs, ins, asmstr, pattern, itin>
177{
178  bits<6>  _code;  // code is a keyword in tablegen
179  bits<5>  funct;
180
181  let Opcode = 0b11101; // RR
182  let funct  = _funct;
183
184  let Inst{10-5} = _code;
185  let Inst{4-0}   = funct;
186}
187
188//
189// J(AL)R(C) subformat
190//
191class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
192                  dag outs, dag ins, string asmstr,
193                  list<dag> pattern, InstrItinClass itin>:
194  MipsInst16<outs, ins, asmstr, pattern, itin>
195{
196  bits<3>  rx;
197  bits<1>  nd;
198  bits<1>  l;
199  bits<1>  ra;
200
201  let nd = _nd;
202  let l = _l;
203  let ra = r_a;
204
205  let Opcode = 0b11101;
206
207  let Inst{10-8} = rx;
208  let Inst{7} = nd;
209  let Inst{6} = l;
210  let Inst{5} = ra;
211  let Inst{4-0} = 0;
212}
213
214//===----------------------------------------------------------------------===//
215// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
216//===----------------------------------------------------------------------===//
217
218class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
219             list<dag> pattern, InstrItinClass itin>:
220  MipsInst16<outs, ins, asmstr, pattern, itin>
221{
222  bits<3>  rx;
223  bits<3>  ry;
224  bits<5>  imm5;
225
226  let Opcode = op;
227
228
229  let Inst{10-8} = rx;
230  let Inst{7-5} = ry;
231  let Inst{4-0}   = imm5;
232}
233
234//===----------------------------------------------------------------------===//
235// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
236//===----------------------------------------------------------------------===//
237
238class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
239             list<dag> pattern, InstrItinClass itin>:
240  MipsInst16<outs, ins, asmstr, pattern, itin>
241{
242  bits<3>  rx;
243  bits<3>  ry;
244  bits<3>  rz;
245  bits<2>  f;
246
247  let Opcode = 0b11100;
248  let f  = _f;
249
250  let Inst{10-8} = rx;
251  let Inst{7-5} = ry;
252  let Inst{4-2} = rz;
253  let Inst{1-0}   = f;
254}
255
256//===----------------------------------------------------------------------===//
257// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
258//===----------------------------------------------------------------------===//
259
260class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
261               list<dag> pattern, InstrItinClass itin>:
262  MipsInst16<outs, ins, asmstr, pattern, itin>
263{
264  bits<3>  rx;
265  bits<3>  ry;
266  bits<1>  f;
267  bits<4>  imm4;
268
269  let Opcode = 0b01000;
270  let  f = _f;
271
272  let Inst{10-8} = rx;
273  let Inst{7-5} = ry;
274  let Inst{4} = f;
275  let Inst{3-0}   = imm4;
276}
277
278//===----------------------------------------------------------------------===//
279// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
280//===----------------------------------------------------------------------===//
281
282class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
283               list<dag> pattern, InstrItinClass itin>:
284  MipsInst16<outs, ins, asmstr, pattern, itin>
285{
286  bits<3>  rx;
287  bits<3>  ry;
288  bits<3>  sa;
289  bits<2>  f;
290
291  let Opcode = 0b00110;
292  let f  = _f;
293
294  let Inst{10-8} = rx;
295  let Inst{7-5} = ry;
296  let Inst{4-2} = sa;
297  let Inst{1-0}   = f;
298}
299
300//===----------------------------------------------------------------------===//
301// Format i8 instruction class in Mips : <|opcode|funct|imm8>
302//===----------------------------------------------------------------------===//
303
304class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
305            list<dag> pattern, InstrItinClass itin>:
306  MipsInst16<outs, ins, asmstr, pattern, itin>
307{
308  bits<3>  func;
309  bits<8>   imm8;
310
311  let Opcode = 0b01100;
312  let func  = _func;
313
314  let Inst{10-8} = func;
315  let Inst{7-0} = imm8;
316}
317
318//===----------------------------------------------------------------------===//
319// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
320//===----------------------------------------------------------------------===//
321
322class FI8_MOVR3216<dag outs, dag ins, string asmstr,
323                   list<dag> pattern, InstrItinClass itin>:
324  MipsInst16<outs, ins, asmstr, pattern, itin>
325{
326
327  bits<4> ry;
328  bits<4> r32;
329
330  let Opcode = 0b01100;
331
332  let Inst{10-8} = 0b111;
333  let Inst{7-4} = ry;
334  let Inst{3-0} = r32;
335
336}
337
338
339
340//===----------------------------------------------------------------------===//
341// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
342//===----------------------------------------------------------------------===//
343
344class FI8_MOV32R16<dag outs, dag ins, string asmstr,
345                   list<dag> pattern, InstrItinClass itin>:
346  MipsInst16<outs, ins, asmstr, pattern, itin>
347{
348
349  bits<3>  func;
350  bits<5> r32;
351  bits<3> rz;
352
353
354  let Opcode = 0b01100;
355
356  let Inst{10-8} = 0b101;
357  let Inst{7-5} = r32{2-0};
358  let Inst{4-3} = r32{4-3};
359  let Inst{2-0} = rz;
360
361}
362
363//===----------------------------------------------------------------------===//
364// Format i8_SVRS instruction class in Mips :
365//    <|opcode|svrs|s|ra|s0|s1|framesize>
366//===----------------------------------------------------------------------===//
367
368class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
369                 list<dag> pattern, InstrItinClass itin>:
370  MipsInst16<outs, ins, asmstr, pattern, itin>
371{
372  bits<1> s;
373  bits<1> ra = 0;
374  bits<1> s0 = 0;
375  bits<1> s1 = 0;
376  bits<4> framesize = 0;
377
378  let s =_s;
379  let Opcode = 0b01100;
380
381  let Inst{10-8} = 0b100;
382  let Inst{7} = s;
383  let Inst{6} = ra;
384  let Inst{5} = s0;
385  let Inst{4} = s1;
386  let Inst{3-0} = framesize;
387
388}
389
390//===----------------------------------------------------------------------===//
391// Format JAL instruction class in Mips16 :
392//    <|opcode|svrs|s|ra|s0|s1|framesize>
393//===----------------------------------------------------------------------===//
394
395class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
396             list<dag> pattern, InstrItinClass itin>:
397  MipsInst16_32<outs, ins, asmstr, pattern, itin>
398{
399  bits<1> X;
400  bits<26> imm26;
401
402
403  let X = _X;
404
405  let Inst{31-27} = 0b00011;
406  let Inst{26} = X;
407  let Inst{25-21} = imm26{20-16};
408  let Inst{20-16} = imm26{25-21};
409  let Inst{15-0}  = imm26{15-0};
410
411}
412
413//===----------------------------------------------------------------------===//
414// Format EXT-I instruction class in Mips16 :
415//     <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
416//===----------------------------------------------------------------------===//
417
418class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
419               list<dag> pattern, InstrItinClass itin>:
420  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
421{
422  bits<16> imm16;
423  bits<5> eop;
424
425  let eop = _eop;
426
427  let Inst{26-21} = imm16{10-5};
428  let Inst{20-16} = imm16{15-11};
429  let Inst{15-11} = eop;
430  let Inst{10-5} = 0;
431  let Inst{4-0} = imm16{4-0};
432
433}
434
435//===----------------------------------------------------------------------===//
436// Format ASMACRO instruction class in Mips16 :
437//    <EXTEND|select|p4|p3|RRR|p2|p1|p0>
438//===----------------------------------------------------------------------===//
439
440class FASMACRO16<dag outs, dag ins, string asmstr,
441                 list<dag> pattern, InstrItinClass itin>:
442  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
443{
444  bits<3> select;
445  bits<3> p4;
446  bits<5> p3;
447  bits<5> RRR = 0b11100;
448  bits<3> p2;
449  bits<3> p1;
450  bits<5> p0;
451
452
453  let Inst{26-24} = select;
454  let Inst{23-21} = p4;
455  let Inst{20-16} = p3;
456  let Inst{15-11} = RRR;
457  let Inst{10-8} = p2;
458  let Inst{7-5} = p1;
459  let Inst{4-0} = p0;
460
461}
462
463
464//===----------------------------------------------------------------------===//
465// Format EXT-RI instruction class in Mips16 :
466//    <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
467//===----------------------------------------------------------------------===//
468
469class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
470                list<dag> pattern, InstrItinClass itin>:
471  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
472{
473  bits<16> imm16;
474  bits<5> op;
475  bits<3> rx;
476
477  let op = _op;
478
479  let Inst{26-21} = imm16{10-5};
480  let Inst{20-16} = imm16{15-11};
481  let Inst{15-11} = op;
482  let Inst{10-8} = rx;
483  let Inst{7-5} = 0;
484  let Inst{4-0} = imm16{4-0};
485
486}
487
488//===----------------------------------------------------------------------===//
489// Format EXT-RRI instruction class in Mips16 :
490//     <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
491//===----------------------------------------------------------------------===//
492
493class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
494                 list<dag> pattern, InstrItinClass itin>:
495  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
496{
497  bits<5> op;
498  bits<16> imm16;
499  bits<3> rx;
500  bits<3> ry;
501
502  let op=_op;
503
504  let Inst{26-21} = imm16{10-5};
505  let Inst{20-16} = imm16{15-11};
506  let Inst{15-11} = op;
507  let Inst{10-8} = rx;
508  let Inst{7-5} = ry;
509  let Inst{4-0} = imm16{4-0};
510
511}
512
513//===----------------------------------------------------------------------===//
514// Format EXT-RRI-A instruction class in Mips16 :
515//    <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
516//===----------------------------------------------------------------------===//
517
518class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
519                   list<dag> pattern, InstrItinClass itin>:
520  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
521{
522  bits<15> imm15;
523  bits<3> rx;
524  bits<3> ry;
525  bits<1> f;
526
527  let f = _f;
528
529  let Inst{26-20} = imm15{10-4};
530  let Inst{19-16} = imm15{14-11};
531  let Inst{15-11} = 0b01000;
532  let Inst{10-8} = rx;
533  let Inst{7-5} = ry;
534  let Inst{4} = f;
535  let Inst{3-0} = imm15{3-0};
536
537}
538
539//===----------------------------------------------------------------------===//
540// Format EXT-SHIFT instruction class in Mips16 :
541//    <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
542//===----------------------------------------------------------------------===//
543
544class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
545                   list<dag> pattern, InstrItinClass itin>:
546  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
547{
548  bits<6> sa6;
549  bits<3> rx;
550  bits<3> ry;
551  bits<2> f;
552
553  let f = _f;
554
555  let Inst{26-22} = sa6{4-0};
556  let Inst{21} = sa6{5};
557  let Inst{20-16} = 0;
558  let Inst{15-11} = 0b00110;
559  let Inst{10-8} = rx;
560  let Inst{7-5} = ry;
561  let Inst{4-2} = 0;
562  let Inst{1-0} = f;
563
564}
565
566//===----------------------------------------------------------------------===//
567// Format EXT-I8 instruction class in Mips16 :
568//    <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
569//===----------------------------------------------------------------------===//
570
571class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
572                list<dag> pattern, InstrItinClass itin>:
573  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
574{
575  bits<16> imm16;
576  bits<5> I8;
577  bits<3> funct;
578
579  let funct = _funct;
580  let I8 = 0b0110;
581
582  let Inst{26-21} = imm16{10-5};
583  let Inst{20-16} = imm16{15-11};
584  let Inst{15-11} = I8;
585  let Inst{10-8} = funct;
586  let Inst{7-5} = 0;
587  let Inst{4-0} = imm16{4-0};
588
589}
590
591//===----------------------------------------------------------------------===//
592// Format EXT-I8_SVRS instruction class in Mips16 :
593//    <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
594//===----------------------------------------------------------------------===//
595
596class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
597                     list<dag> pattern, InstrItinClass itin>:
598  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
599{
600  bits<3> xsregs =0;
601  bits<8> framesize =0;
602  bits<3> aregs =0;
603  bits<5> I8 = 0b01100;
604  bits<3> SVRS = 0b100;
605  bits<1> s;
606  bits<1> ra = 0;
607  bits<1> s0 = 0;
608  bits<1> s1 = 0;
609
610  let s= s_;
611
612  let Inst{26-24} = xsregs;
613  let Inst{23-20} = framesize{7-4};
614  let Inst{19} = 0;
615  let Inst{18-16} = aregs;
616  let Inst{15-11} = I8;
617  let Inst{10-8} = SVRS;
618  let Inst{7} = s;
619  let Inst{6} = ra;
620  let Inst{5} = s0;
621  let Inst{4} = s1;
622  let Inst{3-0} = framesize{3-0};
623
624
625}
626
627