Mips16InstrFormats.td revision fef904d0e824a2c587f8c1063b6c4fbf47fec898
1//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// funct or f Function field 16// 17// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or 18// or imm address displacement 19// 20// op 5-bit major operation code 21// 22// rx 3-bit source or destination register 23// 24// ry 3-bit source or destination register 25// 26// rz 3-bit source or destination register 27// 28// sa 3- or 5-bit shift amount 29// 30//===----------------------------------------------------------------------===// 31 32// Format specifies the encoding used by the instruction. This is part of the 33// ad-hoc solution used to emit machine instruction encodings by our machine 34// code emitter. 35// 36class Format16<bits<5> val> { 37 bits<5> Value = val; 38} 39 40def Pseudo16 : Format16<0>; 41def FrmI16 : Format16<1>; 42def FrmRI16 : Format16<2>; 43def FrmRR16 : Format16<3>; 44def FrmRRI16 : Format16<4>; 45def FrmRRR16 : Format16<5>; 46def FrmRRI_A16 : Format16<6>; 47def FrmSHIFT16 : Format16<7>; 48def FrmI8_TYPE16 : Format16<8>; 49def FrmI8_MOVR3216 : Format16<9>; 50def FrmI8_MOV32R16 : Format16<10>; 51def FrmI8_SVRS16 : Format16<11>; 52def FrmJAL16 : Format16<12>; 53def FrmJALX16 : Format16<13>; 54def FrmEXT_I16 : Format16<14>; 55def FrmASMACRO16 : Format16<15>; 56def FrmEXT_RI16 : Format16<16>; 57def FrmEXT_RRI16 : Format16<17>; 58def FrmEXT_RRI_A16 : Format16<18>; 59def FrmEXT_SHIFT16 : Format16<19>; 60def FrmEXT_I816 : Format16<20>; 61def FrmEXT_I8_SVRS16 : Format16<21>; 62def FrmOther16 : Format16<22>; // Instruction w/ a custom format 63 64// Base class for Mips 16 Format 65// This class does not depend on the instruction size 66// 67class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern, 68 InstrItinClass itin, Format16 f>: Instruction 69{ 70 Format16 Form = f; 71 72 let Namespace = "Mips"; 73 74 let OutOperandList = outs; 75 let InOperandList = ins; 76 77 let AsmString = asmstr; 78 let Pattern = pattern; 79 let Itinerary = itin; 80 81 // 82 // Attributes specific to Mips instructions... 83 // 84 bits<5> FormBits = Form.Value; 85 86 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 87 let TSFlags{4-0} = FormBits; 88 89 let Predicates = [InMips16Mode]; 90} 91 92// 93// Generic Mips 16 Format 94// 95class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern, 96 InstrItinClass itin, Format16 f>: 97 MipsInst16_Base<outs, ins, asmstr, pattern, itin, f> 98{ 99 field bits<16> Inst; 100 bits<5> Opcode = 0; 101 102 // Top 5 bits are the 'opcode' field 103 let Inst{15-11} = Opcode; 104} 105 106// 107// For 32 bit extended instruction forms. 108// 109class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern, 110 InstrItinClass itin, Format16 f>: 111 MipsInst16_Base<outs, ins, asmstr, pattern, itin, f> 112{ 113 field bits<32> Inst; 114 115} 116 117class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern, 118 InstrItinClass itin, Format16 f>: 119 MipsInst16_32<outs, ins, asmstr, pattern, itin, f> 120{ 121 let Inst{31-27} = 0b11110; 122} 123 124 125 126// Mips Pseudo Instructions Format 127class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>: 128 MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> { 129 let isCodeGenOnly = 1; 130 let isPseudo = 1; 131} 132 133 134//===----------------------------------------------------------------------===// 135// Format I instruction class in Mips : <|opcode|imm11|> 136//===----------------------------------------------------------------------===// 137 138class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern, 139 InstrItinClass itin>: 140 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI16> 141{ 142 bits<11> imm11; 143 144 let Opcode = op; 145 146 let Inst{10-0} = imm11; 147} 148 149//===----------------------------------------------------------------------===// 150// Format RI instruction class in Mips : <|opcode|rx|imm8|> 151//===----------------------------------------------------------------------===// 152 153class FRI16<bits<5> op, dag outs, dag ins, string asmstr, 154 list<dag> pattern, InstrItinClass itin>: 155 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16> 156{ 157 bits<3> rx; 158 bits<8> imm8; 159 160 let Opcode = op; 161 162 let Inst{10-8} = rx; 163 let Inst{7-0} = imm8; 164} 165 166//===----------------------------------------------------------------------===// 167// Format RR instruction class in Mips : <|opcode|rx|ry|funct|> 168//===----------------------------------------------------------------------===// 169 170class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr, 171 list<dag> pattern, InstrItinClass itin>: 172 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16> 173{ 174 bits<3> rx; 175 bits<3> ry; 176 bits<5> funct; 177 178 let Opcode = 0b11101; 179 let funct = _funct; 180 181 let Inst{10-8} = rx; 182 let Inst{7-5} = ry; 183 let Inst{4-0} = funct; 184} 185 186// 187// For conversion functions. 188// 189class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins, 190 string asmstr, list<dag> pattern, InstrItinClass itin>: 191 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16> 192{ 193 bits<3> rx; 194 bits<3> subfunct; 195 bits<5> funct; 196 197 let Opcode = 0b11101; // RR 198 let funct = _funct; 199 let subfunct = _subfunct; 200 201 let Inst{10-8} = rx; 202 let Inst{7-5} = subfunct; 203 let Inst{4-0} = funct; 204} 205 206// 207// just used for breakpoint (hardware and software) instructions. 208// 209class FC16<bits<5> _funct, dag outs, dag ins, string asmstr, 210 list<dag> pattern, InstrItinClass itin>: 211 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16> 212{ 213 bits<6> _code; // code is a keyword in tablegen 214 bits<5> funct; 215 216 let Opcode = 0b11101; // RR 217 let funct = _funct; 218 219 let Inst{10-5} = _code; 220 let Inst{4-0} = funct; 221} 222 223// 224// J(AL)R(C) subformat 225// 226class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a, 227 dag outs, dag ins, string asmstr, 228 list<dag> pattern, InstrItinClass itin>: 229 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16> 230{ 231 bits<3> rx; 232 bits<1> nd; 233 bits<1> l; 234 bits<1> ra; 235 236 let nd = _nd; 237 let l = _l; 238 let ra = r_a; 239 240 let Opcode = 0b11101; 241 242 let Inst{10-8} = rx; 243 let Inst{7} = nd; 244 let Inst{6} = l; 245 let Inst{5} = ra; 246 let Inst{4-0} = 0; 247} 248 249//===----------------------------------------------------------------------===// 250// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|> 251//===----------------------------------------------------------------------===// 252 253class FRRI16<bits<5> op, dag outs, dag ins, string asmstr, 254 list<dag> pattern, InstrItinClass itin>: 255 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16> 256{ 257 bits<3> rx; 258 bits<3> ry; 259 bits<5> imm5; 260 261 let Opcode = op; 262 263 264 let Inst{10-8} = rx; 265 let Inst{7-5} = ry; 266 let Inst{4-0} = imm5; 267} 268 269//===----------------------------------------------------------------------===// 270// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|> 271//===----------------------------------------------------------------------===// 272 273class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr, 274 list<dag> pattern, InstrItinClass itin>: 275 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16> 276{ 277 bits<3> rx; 278 bits<3> ry; 279 bits<3> rz; 280 bits<2> f; 281 282 let Opcode = 0b11100; 283 let f = _f; 284 285 let Inst{10-8} = rx; 286 let Inst{7-5} = ry; 287 let Inst{4-2} = rz; 288 let Inst{1-0} = f; 289} 290 291//===----------------------------------------------------------------------===// 292// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|> 293//===----------------------------------------------------------------------===// 294 295class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr, 296 list<dag> pattern, InstrItinClass itin>: 297 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16> 298{ 299 bits<3> rx; 300 bits<3> ry; 301 bits<1> f; 302 bits<4> imm4; 303 304 let Opcode = 0b01000; 305 let f = _f; 306 307 let Inst{10-8} = rx; 308 let Inst{7-5} = ry; 309 let Inst{4} = f; 310 let Inst{3-0} = imm4; 311} 312 313//===----------------------------------------------------------------------===// 314// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|> 315//===----------------------------------------------------------------------===// 316 317class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr, 318 list<dag> pattern, InstrItinClass itin>: 319 MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16> 320{ 321 bits<3> rx; 322 bits<3> ry; 323 bits<3> sa; 324 bits<2> f; 325 326 let Opcode = 0b00110; 327 let f = _f; 328 329 let Inst{10-8} = rx; 330 let Inst{7-5} = ry; 331 let Inst{4-2} = sa; 332 let Inst{1-0} = f; 333} 334 335//===----------------------------------------------------------------------===// 336// Format i8 instruction class in Mips : <|opcode|funct|imm8> 337//===----------------------------------------------------------------------===// 338 339class FI816<bits<3> _func, dag outs, dag ins, string asmstr, 340 list<dag> pattern, InstrItinClass itin>: 341 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16> 342{ 343 bits<3> func; 344 bits<8> imm8; 345 346 let Opcode = 0b01100; 347 let func = _func; 348 349 let Inst{10-8} = func; 350 let Inst{7-0} = imm8; 351} 352 353//===----------------------------------------------------------------------===// 354// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32> 355//===----------------------------------------------------------------------===// 356 357class FI8_MOVR3216<dag outs, dag ins, string asmstr, 358 list<dag> pattern, InstrItinClass itin>: 359 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216> 360{ 361 362 bits<4> ry; 363 bits<4> r32; 364 365 let Opcode = 0b01100; 366 367 let Inst{10-8} = 0b111; 368 let Inst{7-4} = ry; 369 let Inst{3-0} = r32; 370 371} 372 373 374 375//===----------------------------------------------------------------------===// 376// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz> 377//===----------------------------------------------------------------------===// 378 379class FI8_MOV32R16<dag outs, dag ins, string asmstr, 380 list<dag> pattern, InstrItinClass itin>: 381 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16> 382{ 383 384 bits<3> func; 385 bits<5> r32; 386 bits<3> rz; 387 388 389 let Opcode = 0b01100; 390 391 let Inst{10-8} = 0b101; 392 let Inst{7-5} = r32{2-0}; 393 let Inst{4-3} = r32{4-3}; 394 let Inst{2-0} = rz; 395 396} 397 398//===----------------------------------------------------------------------===// 399// Format i8_SVRS instruction class in Mips : 400// <|opcode|svrs|s|ra|s0|s1|framesize> 401//===----------------------------------------------------------------------===// 402 403class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr, 404 list<dag> pattern, InstrItinClass itin>: 405 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16> 406{ 407 bits<1> s; 408 bits<1> ra = 0; 409 bits<1> s0 = 0; 410 bits<1> s1 = 0; 411 bits<4> framesize = 0; 412 413 let s =_s; 414 let Opcode = 0b01100; 415 416 let Inst{10-8} = 0b100; 417 let Inst{7} = s; 418 let Inst{6} = ra; 419 let Inst{5} = s0; 420 let Inst{4} = s1; 421 let Inst{3-0} = framesize; 422 423} 424 425//===----------------------------------------------------------------------===// 426// Format JAL instruction class in Mips16 : 427// <|opcode|svrs|s|ra|s0|s1|framesize> 428//===----------------------------------------------------------------------===// 429 430class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr, 431 list<dag> pattern, InstrItinClass itin>: 432 MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16> 433{ 434 bits<1> X; 435 bits<26> imm26; 436 437 438 let X = _X; 439 440 let Inst{31-27} = 0b00011; 441 let Inst{26} = X; 442 let Inst{25-21} = imm26{20-16}; 443 let Inst{20-16} = imm26{25-21}; 444 let Inst{15-0} = imm26{15-0}; 445 446} 447 448//===----------------------------------------------------------------------===// 449// Format EXT-I instruction class in Mips16 : 450// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0> 451//===----------------------------------------------------------------------===// 452 453class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr, 454 list<dag> pattern, InstrItinClass itin>: 455 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16> 456{ 457 bits<16> imm16; 458 bits<5> eop; 459 460 let eop = _eop; 461 462 let Inst{26-21} = imm16{10-5}; 463 let Inst{20-16} = imm16{15-11}; 464 let Inst{15-11} = eop; 465 let Inst{10-5} = 0; 466 let Inst{4-0} = imm16{4-0}; 467 468} 469 470//===----------------------------------------------------------------------===// 471// Format ASMACRO instruction class in Mips16 : 472// <EXTEND|select|p4|p3|RRR|p2|p1|p0> 473//===----------------------------------------------------------------------===// 474 475class FASMACRO16<dag outs, dag ins, string asmstr, 476 list<dag> pattern, InstrItinClass itin>: 477 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmASMACRO16> 478{ 479 bits<3> select; 480 bits<3> p4; 481 bits<5> p3; 482 bits<5> RRR = 0b11100; 483 bits<3> p2; 484 bits<3> p1; 485 bits<5> p0; 486 487 488 let Inst{26-24} = select; 489 let Inst{23-21} = p4; 490 let Inst{20-16} = p3; 491 let Inst{15-11} = RRR; 492 let Inst{10-8} = p2; 493 let Inst{7-5} = p1; 494 let Inst{4-0} = p0; 495 496} 497 498 499//===----------------------------------------------------------------------===// 500// Format EXT-RI instruction class in Mips16 : 501// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0> 502//===----------------------------------------------------------------------===// 503 504class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr, 505 list<dag> pattern, InstrItinClass itin>: 506 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RI16> 507{ 508 bits<16> imm16; 509 bits<5> op; 510 bits<3> rx; 511 512 let op = _op; 513 514 let Inst{26-21} = imm16{10-5}; 515 let Inst{20-16} = imm16{15-11}; 516 let Inst{15-11} = op; 517 let Inst{10-8} = rx; 518 let Inst{7-5} = 0; 519 let Inst{4-0} = imm16{4-0}; 520 521} 522 523//===----------------------------------------------------------------------===// 524// Format EXT-RRI instruction class in Mips16 : 525// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0> 526//===----------------------------------------------------------------------===// 527 528class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr, 529 list<dag> pattern, InstrItinClass itin>: 530 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI16> 531{ 532 bits<16> imm16; 533 bits<3> rx; 534 bits<3> ry; 535 536 537 let Inst{26-21} = imm16{10-5}; 538 let Inst{20-16} = imm16{15-11}; 539 let Inst{15-11} = _op; 540 let Inst{10-8} = rx; 541 let Inst{7-5} = ry; 542 let Inst{4-0} = imm16{4-0}; 543 544} 545 546//===----------------------------------------------------------------------===// 547// Format EXT-RRI-A instruction class in Mips16 : 548// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0> 549//===----------------------------------------------------------------------===// 550 551class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr, 552 list<dag> pattern, InstrItinClass itin>: 553 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI_A16> 554{ 555 bits<15> imm15; 556 bits<3> rx; 557 bits<3> ry; 558 bits<1> f; 559 560 let f = _f; 561 562 let Inst{26-20} = imm15{10-4}; 563 let Inst{19-16} = imm15{14-11}; 564 let Inst{15-11} = 0b01000; 565 let Inst{10-8} = rx; 566 let Inst{7-5} = ry; 567 let Inst{4} = f; 568 let Inst{3-0} = imm15{3-0}; 569 570} 571 572//===----------------------------------------------------------------------===// 573// Format EXT-SHIFT instruction class in Mips16 : 574// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f> 575//===----------------------------------------------------------------------===// 576 577class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr, 578 list<dag> pattern, InstrItinClass itin>: 579 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_SHIFT16> 580{ 581 bits<6> sa6; 582 bits<3> rx; 583 bits<3> ry; 584 bits<2> f; 585 586 let f = _f; 587 588 let Inst{26-22} = sa6{4-0}; 589 let Inst{21} = sa6{5}; 590 let Inst{20-16} = 0; 591 let Inst{15-11} = 0b00110; 592 let Inst{10-8} = rx; 593 let Inst{7-5} = ry; 594 let Inst{4-2} = 0; 595 let Inst{1-0} = f; 596 597} 598 599//===----------------------------------------------------------------------===// 600// Format EXT-I8 instruction class in Mips16 : 601// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0> 602//===----------------------------------------------------------------------===// 603 604class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr, 605 list<dag> pattern, InstrItinClass itin>: 606 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I816> 607{ 608 bits<16> imm16; 609 bits<5> I8; 610 bits<3> funct; 611 612 let funct = _funct; 613 let I8 = 0b0110; 614 615 let Inst{26-21} = imm16{10-5}; 616 let Inst{20-16} = imm16{15-11}; 617 let Inst{15-11} = I8; 618 let Inst{10-8} = funct; 619 let Inst{7-5} = 0; 620 let Inst{4-0} = imm16{4-0}; 621 622} 623 624//===----------------------------------------------------------------------===// 625// Format EXT-I8_SVRS instruction class in Mips16 : 626// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> 627//===----------------------------------------------------------------------===// 628 629class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr, 630 list<dag> pattern, InstrItinClass itin>: 631 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16> 632{ 633 bits<3> xsregs =0; 634 bits<8> framesize =0; 635 bits<3> aregs =0; 636 bits<5> I8 = 0b01100; 637 bits<3> SVRS = 0b100; 638 bits<1> s; 639 bits<1> ra = 0; 640 bits<1> s0 = 0; 641 bits<1> s1 = 0; 642 643 let s= s_; 644 645 let Inst{26-24} = xsregs; 646 let Inst{23-20} = framesize{7-4}; 647 let Inst{19} = 0; 648 let Inst{18-16} = aregs; 649 let Inst{15-11} = I8; 650 let Inst{10-8} = SVRS; 651 let Inst{7} = s; 652 let Inst{6} = ra; 653 let Inst{5} = s0; 654 let Inst{4} = s1; 655 let Inst{3-0} = framesize{3-0}; 656 657 658} 659 660 661 662