Mips16InstrInfo.cpp revision 1858786285139b87961d9ca08de91dcd59364afb 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13#include <stdio.h>
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27
28using namespace llvm;
29
30static cl::opt<bool> NeverUseSaveRestore(
31  "mips16-never-use-save-restore",
32  cl::init(false),
33  cl::desc("For testing ability to adjust stack pointer "
34           "without save/restore instruction"),
35  cl::Hidden);
36
37
38Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39  : MipsInstrInfo(tm, Mips::BimmX16),
40    RI(*tm.getSubtargetImpl()) {}
41
42const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
43  return RI;
44}
45
46/// isLoadFromStackSlot - If the specified machine instruction is a direct
47/// load from a stack slot, return the virtual or physical register number of
48/// the destination along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than loading from the stack slot.
51unsigned Mips16InstrInfo::
52isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57/// isStoreToStackSlot - If the specified machine instruction is a direct
58/// store to a stack slot, return the virtual or physical register number of
59/// the source reg along with the FrameIndex of the loaded stack slot.  If
60/// not, return 0.  This predicate must return 0 if the instruction has
61/// any side effects other than storing to the stack slot.
62unsigned Mips16InstrInfo::
63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
64{
65  return 0;
66}
67
68void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69                                  MachineBasicBlock::iterator I, DebugLoc DL,
70                                  unsigned DestReg, unsigned SrcReg,
71                                  bool KillSrc) const {
72  unsigned Opc = 0;
73
74  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75      Mips::GPR32RegClass.contains(SrcReg))
76    Opc = Mips::MoveR3216;
77  else if (Mips::GPR32RegClass.contains(DestReg) &&
78           Mips::CPU16RegsRegClass.contains(SrcReg))
79    Opc = Mips::Move32R16;
80  else if ((SrcReg == Mips::HI) &&
81           (Mips::CPU16RegsRegClass.contains(DestReg)))
82    Opc = Mips::Mfhi16, SrcReg = 0;
83
84  else if ((SrcReg == Mips::LO) &&
85           (Mips::CPU16RegsRegClass.contains(DestReg)))
86    Opc = Mips::Mflo16, SrcReg = 0;
87
88
89  assert(Opc && "Cannot copy registers");
90
91  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
92
93  if (DestReg)
94    MIB.addReg(DestReg, RegState::Define);
95
96  if (SrcReg)
97    MIB.addReg(SrcReg, getKillRegState(KillSrc));
98}
99
100void Mips16InstrInfo::
101storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102                unsigned SrcReg, bool isKill, int FI,
103                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
104                int64_t Offset) const {
105  DebugLoc DL;
106  if (I != MBB.end()) DL = I->getDebugLoc();
107  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108  unsigned Opc = 0;
109  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110    Opc = Mips::SwRxSpImmX16;
111  assert(Opc && "Register class not handled!");
112  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
113      addFrameIndex(FI).addImm(Offset)
114      .addMemOperand(MMO);
115}
116
117void Mips16InstrInfo::
118loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
119                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
120                 const TargetRegisterInfo *TRI, int64_t Offset) const {
121  DebugLoc DL;
122  if (I != MBB.end()) DL = I->getDebugLoc();
123  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
124  unsigned Opc = 0;
125
126  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127    Opc = Mips::LwRxSpImmX16;
128  assert(Opc && "Register class not handled!");
129  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
130    .addMemOperand(MMO);
131}
132
133bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134  MachineBasicBlock &MBB = *MI->getParent();
135  switch(MI->getDesc().getOpcode()) {
136  default:
137    return false;
138  case Mips::RetRA16:
139    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
140    break;
141  }
142
143  MBB.erase(MI);
144  return true;
145}
146
147/// GetOppositeBranchOpc - Return the inverse of the specified
148/// opcode, e.g. turning BEQ to BNE.
149unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
150  switch (Opc) {
151  default:  llvm_unreachable("Illegal opcode!");
152  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
153  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
154  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
155  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
156  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
157  case Mips::BtnezX16: return Mips::BteqzX16;
158  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
159  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
160  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
161  case Mips::BteqzX16: return Mips::BtnezX16;
162  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
163  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
164  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
165  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
166  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
167  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
168  }
169  assert(false && "Implement this function.");
170  return 0;
171}
172
173// Adjust SP by FrameSize bytes. Save RA, S0, S1
174void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
175                    MachineBasicBlock &MBB,
176                    MachineBasicBlock::iterator I) const {
177  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
178  if (!NeverUseSaveRestore) {
179    if (isUInt<11>(FrameSize))
180      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
181    else {
182      int Base = 2040; // should create template function like isUInt that
183                       // returns largest possible n bit unsigned integer
184      int64_t Remainder = FrameSize - Base;
185      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
186      if (isInt<16>(-Remainder))
187        BuildAddiuSpImm(MBB, I, -Remainder);
188      else
189        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
190    }
191
192  }
193  else {
194    //
195    // sw ra, -4[sp]
196    // sw s1, -8[sp]
197    // sw s0, -12[sp]
198
199    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
200                                       Mips::RA);
201    MIB1.addReg(Mips::SP);
202    MIB1.addImm(-4);
203    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
204                                       Mips::S1);
205    MIB2.addReg(Mips::SP);
206    MIB2.addImm(-8);
207    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
208                                       Mips::S0);
209    MIB3.addReg(Mips::SP);
210    MIB3.addImm(-12);
211    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
212  }
213}
214
215// Adjust SP by FrameSize bytes. Restore RA, S0, S1
216void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
217                                   MachineBasicBlock &MBB,
218                                   MachineBasicBlock::iterator I) const {
219  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
220  if (!NeverUseSaveRestore) {
221    if (isUInt<11>(FrameSize))
222      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
223    else {
224      int Base = 2040; // should create template function like isUInt that
225                       // returns largest possible n bit unsigned integer
226      int64_t Remainder = FrameSize - Base;
227      if (isInt<16>(Remainder))
228        BuildAddiuSpImm(MBB, I, Remainder);
229      else
230        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
231      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
232    }
233  }
234  else {
235    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
236    // lw ra, -4[sp]
237    // lw s1, -8[sp]
238    // lw s0, -12[sp]
239    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
240                                       Mips::A0);
241    MIB1.addReg(Mips::SP);
242    MIB1.addImm(-4);
243    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
244                                       Mips::RA);
245     MIB0.addReg(Mips::A0);
246    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
247                                       Mips::S1);
248    MIB2.addReg(Mips::SP);
249    MIB2.addImm(-8);
250    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
251                                       Mips::S0);
252    MIB3.addReg(Mips::SP);
253    MIB3.addImm(-12);
254  }
255
256}
257
258// Adjust SP by Amount bytes where bytes can be up to 32bit number.
259// This can only be called at times that we know that there is at least one free
260// register.
261// This is clearly safe at prologue and epilogue.
262//
263void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
264                                        MachineBasicBlock &MBB,
265                                        MachineBasicBlock::iterator I,
266                                        unsigned Reg1, unsigned Reg2) const {
267  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
268//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
269//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
270//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
271  //
272  // li reg1, constant
273  // move reg2, sp
274  // add reg1, reg1, reg2
275  // move sp, reg1
276  //
277  //
278  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
279  MIB1.addImm(Amount);
280  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
281  MIB2.addReg(Mips::SP, RegState::Kill);
282  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
283  MIB3.addReg(Reg1);
284  MIB3.addReg(Reg2, RegState::Kill);
285  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
286                                                     Mips::SP);
287  MIB4.addReg(Reg1, RegState::Kill);
288}
289
290void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
291                    MachineBasicBlock &MBB,
292                    MachineBasicBlock::iterator I) const {
293   assert(false && "adjust stack pointer amount exceeded");
294}
295
296/// Adjust SP by Amount bytes.
297void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
298                                     MachineBasicBlock &MBB,
299                                     MachineBasicBlock::iterator I) const {
300  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
301    BuildAddiuSpImm(MBB, I, Amount);
302  else
303    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
304}
305
306/// This function generates the sequence of instructions needed to get the
307/// result of adding register REG and immediate IMM.
308unsigned
309Mips16InstrInfo::loadImmediate(unsigned FrameReg,
310                               int64_t Imm, MachineBasicBlock &MBB,
311                               MachineBasicBlock::iterator II, DebugLoc DL,
312                               unsigned &NewImm) const {
313  //
314  // given original instruction is:
315  // Instr rx, T[offset] where offset is too big.
316  //
317  // lo = offset & 0xFFFF
318  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
319  //
320  // let T = temporary register
321  // li T, hi
322  // shl T, 16
323  // add T, Rx, T
324  //
325  RegScavenger rs;
326  int32_t lo = Imm & 0xFFFF;
327  NewImm = lo;
328  int Reg =0;
329  int SpReg = 0;
330
331  rs.enterBasicBlock(&MBB);
332  rs.forward(II);
333  //
334  // We need to know which registers can be used, in the case where there
335  // are not enough free registers. We exclude all registers that
336  // are used in the instruction that we are helping.
337  //  // Consider all allocatable registers in the register class initially
338  BitVector Candidates =
339      RI.getAllocatableSet
340      (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
341  // Exclude all the registers being used by the instruction.
342  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
343    MachineOperand &MO = II->getOperand(i);
344    if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
345        !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
346      Candidates.reset(MO.getReg());
347  }
348  //
349  // If the same register was used and defined in an instruction, then
350  // it will not be in the list of candidates.
351  //
352  // we need to analyze the instruction that we are helping.
353  // we need to know if it defines register x but register x is not
354  // present as an operand of the instruction. this tells
355  // whether the register is live before the instruction. if it's not
356  // then we don't need to save it in case there are no free registers.
357  //
358  int DefReg = 0;
359  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
360    MachineOperand &MO = II->getOperand(i);
361    if (MO.isReg() && MO.isDef()) {
362      DefReg = MO.getReg();
363      break;
364    }
365  }
366  //
367  BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
368
369  Available &= Candidates;
370  //
371  // we use T0 for the first register, if we need to save something away.
372  // we use T1 for the second register, if we need to save something away.
373  //
374  unsigned FirstRegSaved =0, SecondRegSaved=0;
375  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
376
377
378  Reg = Available.find_first();
379
380  if (Reg == -1) {
381    Reg = Candidates.find_first();
382    Candidates.reset(Reg);
383    if (DefReg != Reg) {
384      FirstRegSaved = Reg;
385      FirstRegSavedTo = Mips::T0;
386      copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
387    }
388  }
389  else
390    Available.reset(Reg);
391  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
392  NewImm = 0;
393  if (FrameReg == Mips::SP) {
394    SpReg = Available.find_first();
395    if (SpReg == -1) {
396      SpReg = Candidates.find_first();
397      // Candidates.reset(SpReg); // not really needed
398      if (DefReg!= SpReg) {
399        SecondRegSaved = SpReg;
400        SecondRegSavedTo = Mips::T1;
401      }
402      if (SecondRegSaved)
403        copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
404    }
405   else
406     Available.reset(SpReg);
407    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
408    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
409      .addReg(Reg);
410  }
411  else
412    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
413      .addReg(Reg, RegState::Kill);
414  if (FirstRegSaved || SecondRegSaved) {
415    II = llvm::next(II);
416    if (FirstRegSaved)
417      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
418    if (SecondRegSaved)
419      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
420  }
421  return Reg;
422}
423
424/// This function generates the sequence of instructions needed to get the
425/// result of adding register REG and immediate IMM.
426unsigned
427Mips16InstrInfo::basicLoadImmediate(
428  unsigned FrameReg,
429  int64_t Imm, MachineBasicBlock &MBB,
430  MachineBasicBlock::iterator II, DebugLoc DL,
431  unsigned &NewImm) const {
432  const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
433  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
434  unsigned Reg = RegInfo.createVirtualRegister(RC);
435  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
436  NewImm = 0;
437  return Reg;
438}
439
440unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
441  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
442          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
443          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
444          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
445          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
446          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
447          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
448          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
449          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
450}
451
452void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
453                                  MachineBasicBlock::iterator I,
454                                  unsigned Opc) const {
455  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
456}
457
458
459const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
460  if (validSpImm8(Imm))
461    return get(Mips::AddiuSpImm16);
462  else
463    return get(Mips::AddiuSpImmX16);
464}
465
466void Mips16InstrInfo::BuildAddiuSpImm
467  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
468  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
469  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
470}
471
472const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
473  return new Mips16InstrInfo(TM);
474}
475
476#include <stdio.h>
477bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
478                                     int64_t Amount) {
479  switch (Opcode) {
480  case Mips::LbRxRyOffMemX16:
481  case Mips::LbuRxRyOffMemX16:
482  case Mips::LhRxRyOffMemX16:
483  case Mips::LhuRxRyOffMemX16:
484  case Mips::SbRxRyOffMemX16:
485  case Mips::ShRxRyOffMemX16:
486  case Mips::LwRxRyOffMemX16:
487  case Mips::SwRxRyOffMemX16:
488  case Mips::SwRxSpImmX16:
489  case Mips::LwRxSpImmX16:
490    return isInt<16>(Amount);
491  case Mips::AddiuRxRyOffMemX16:
492    if ((Reg == Mips::PC) || (Reg == Mips::SP))
493      return isInt<16>(Amount);
494    return isInt<15>(Amount);
495  }
496  printf("Unexpected opcode %i \n", Opcode);
497  llvm_unreachable("unexpected Opcode in validImmediate");
498}
499