Mips16InstrInfo.cpp revision 4df21b14675954ba951ad118d1dc4a4021650078 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13#include <ctype.h>
14#include <stdlib.h>
15#include "Mips16InstrInfo.h"
16#include "InstPrinter/MipsInstPrinter.h"
17#include "MipsMachineFunction.h"
18#include "MipsTargetMachine.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/StringRef.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/RegisterScavenging.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/TargetRegistry.h"
29
30using namespace llvm;
31
32static cl::opt<bool> NeverUseSaveRestore(
33  "mips16-never-use-save-restore",
34  cl::init(false),
35  cl::desc("For testing ability to adjust stack pointer "
36           "without save/restore instruction"),
37  cl::Hidden);
38
39
40Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
41  : MipsInstrInfo(tm, Mips::Bimm16),
42    RI(*tm.getSubtargetImpl()) {}
43
44const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
45  return RI;
46}
47
48/// isLoadFromStackSlot - If the specified machine instruction is a direct
49/// load from a stack slot, return the virtual or physical register number of
50/// the destination along with the FrameIndex of the loaded stack slot.  If
51/// not, return 0.  This predicate must return 0 if the instruction has
52/// any side effects other than loading from the stack slot.
53unsigned Mips16InstrInfo::
54isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
55{
56  return 0;
57}
58
59/// isStoreToStackSlot - If the specified machine instruction is a direct
60/// store to a stack slot, return the virtual or physical register number of
61/// the source reg along with the FrameIndex of the loaded stack slot.  If
62/// not, return 0.  This predicate must return 0 if the instruction has
63/// any side effects other than storing to the stack slot.
64unsigned Mips16InstrInfo::
65isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
66{
67  return 0;
68}
69
70void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
71                                  MachineBasicBlock::iterator I, DebugLoc DL,
72                                  unsigned DestReg, unsigned SrcReg,
73                                  bool KillSrc) const {
74  unsigned Opc = 0;
75
76  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
77      Mips::GPR32RegClass.contains(SrcReg))
78    Opc = Mips::MoveR3216;
79  else if (Mips::GPR32RegClass.contains(DestReg) &&
80           Mips::CPU16RegsRegClass.contains(SrcReg))
81    Opc = Mips::Move32R16;
82  else if ((SrcReg == Mips::HI0) &&
83           (Mips::CPU16RegsRegClass.contains(DestReg)))
84    Opc = Mips::Mfhi16, SrcReg = 0;
85
86  else if ((SrcReg == Mips::LO0) &&
87           (Mips::CPU16RegsRegClass.contains(DestReg)))
88    Opc = Mips::Mflo16, SrcReg = 0;
89
90
91  assert(Opc && "Cannot copy registers");
92
93  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94
95  if (DestReg)
96    MIB.addReg(DestReg, RegState::Define);
97
98  if (SrcReg)
99    MIB.addReg(SrcReg, getKillRegState(KillSrc));
100}
101
102void Mips16InstrInfo::
103storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
104                unsigned SrcReg, bool isKill, int FI,
105                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
106                int64_t Offset) const {
107  DebugLoc DL;
108  if (I != MBB.end()) DL = I->getDebugLoc();
109  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
110  unsigned Opc = 0;
111  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
112    Opc = Mips::SwRxSpImmX16;
113  assert(Opc && "Register class not handled!");
114  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
115      addFrameIndex(FI).addImm(Offset)
116      .addMemOperand(MMO);
117}
118
119void Mips16InstrInfo::
120loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
121                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
122                 const TargetRegisterInfo *TRI, int64_t Offset) const {
123  DebugLoc DL;
124  if (I != MBB.end()) DL = I->getDebugLoc();
125  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
126  unsigned Opc = 0;
127
128  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
129    Opc = Mips::LwRxSpImmX16;
130  assert(Opc && "Register class not handled!");
131  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
132    .addMemOperand(MMO);
133}
134
135bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
136  MachineBasicBlock &MBB = *MI->getParent();
137  switch(MI->getDesc().getOpcode()) {
138  default:
139    return false;
140  case Mips::RetRA16:
141    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
142    break;
143  }
144
145  MBB.erase(MI);
146  return true;
147}
148
149/// GetOppositeBranchOpc - Return the inverse of the specified
150/// opcode, e.g. turning BEQ to BNE.
151unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
152  switch (Opc) {
153  default:  llvm_unreachable("Illegal opcode!");
154  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
155  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
156  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
157  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
158  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
159  case Mips::BtnezX16: return Mips::BteqzX16;
160  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
161  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
162  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
163  case Mips::BteqzX16: return Mips::BtnezX16;
164  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
165  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
166  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
167  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
168  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
169  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
170  }
171  assert(false && "Implement this function.");
172  return 0;
173}
174
175// Adjust SP by FrameSize bytes. Save RA, S0, S1
176void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
177                    MachineBasicBlock &MBB,
178                    MachineBasicBlock::iterator I) const {
179  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
180  if (!NeverUseSaveRestore) {
181    if (isUInt<11>(FrameSize))
182      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
183    else {
184      int Base = 2040; // should create template function like isUInt that
185                       // returns largest possible n bit unsigned integer
186      int64_t Remainder = FrameSize - Base;
187      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
188      if (isInt<16>(-Remainder))
189        BuildAddiuSpImm(MBB, I, -Remainder);
190      else
191        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
192    }
193
194  }
195  else {
196    //
197    // sw ra, -4[sp]
198    // sw s1, -8[sp]
199    // sw s0, -12[sp]
200
201    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
202                                       Mips::RA);
203    MIB1.addReg(Mips::SP);
204    MIB1.addImm(-4);
205    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
206                                       Mips::S1);
207    MIB2.addReg(Mips::SP);
208    MIB2.addImm(-8);
209    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
210                                       Mips::S0);
211    MIB3.addReg(Mips::SP);
212    MIB3.addImm(-12);
213    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
214  }
215}
216
217// Adjust SP by FrameSize bytes. Restore RA, S0, S1
218void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
219                                   MachineBasicBlock &MBB,
220                                   MachineBasicBlock::iterator I) const {
221  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
222  if (!NeverUseSaveRestore) {
223    if (isUInt<11>(FrameSize))
224      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
225    else {
226      int Base = 2040; // should create template function like isUInt that
227                       // returns largest possible n bit unsigned integer
228      int64_t Remainder = FrameSize - Base;
229      if (isInt<16>(Remainder))
230        BuildAddiuSpImm(MBB, I, Remainder);
231      else
232        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
233      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
234    }
235  }
236  else {
237    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
238    // lw ra, -4[sp]
239    // lw s1, -8[sp]
240    // lw s0, -12[sp]
241    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
242                                       Mips::A0);
243    MIB1.addReg(Mips::SP);
244    MIB1.addImm(-4);
245    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
246                                       Mips::RA);
247     MIB0.addReg(Mips::A0);
248    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
249                                       Mips::S1);
250    MIB2.addReg(Mips::SP);
251    MIB2.addImm(-8);
252    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
253                                       Mips::S0);
254    MIB3.addReg(Mips::SP);
255    MIB3.addImm(-12);
256  }
257
258}
259
260// Adjust SP by Amount bytes where bytes can be up to 32bit number.
261// This can only be called at times that we know that there is at least one free
262// register.
263// This is clearly safe at prologue and epilogue.
264//
265void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
266                                        MachineBasicBlock &MBB,
267                                        MachineBasicBlock::iterator I,
268                                        unsigned Reg1, unsigned Reg2) const {
269  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
270//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
271//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
272//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
273  //
274  // li reg1, constant
275  // move reg2, sp
276  // add reg1, reg1, reg2
277  // move sp, reg1
278  //
279  //
280  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
281  MIB1.addImm(Amount);
282  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
283  MIB2.addReg(Mips::SP, RegState::Kill);
284  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
285  MIB3.addReg(Reg1);
286  MIB3.addReg(Reg2, RegState::Kill);
287  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
288                                                     Mips::SP);
289  MIB4.addReg(Reg1, RegState::Kill);
290}
291
292void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
293                    MachineBasicBlock &MBB,
294                    MachineBasicBlock::iterator I) const {
295   assert(false && "adjust stack pointer amount exceeded");
296}
297
298/// Adjust SP by Amount bytes.
299void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
300                                     MachineBasicBlock &MBB,
301                                     MachineBasicBlock::iterator I) const {
302  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
303    BuildAddiuSpImm(MBB, I, Amount);
304  else
305    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
306}
307
308/// This function generates the sequence of instructions needed to get the
309/// result of adding register REG and immediate IMM.
310unsigned
311Mips16InstrInfo::loadImmediate(unsigned FrameReg,
312                               int64_t Imm, MachineBasicBlock &MBB,
313                               MachineBasicBlock::iterator II, DebugLoc DL,
314                               unsigned &NewImm) const {
315  //
316  // given original instruction is:
317  // Instr rx, T[offset] where offset is too big.
318  //
319  // lo = offset & 0xFFFF
320  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
321  //
322  // let T = temporary register
323  // li T, hi
324  // shl T, 16
325  // add T, Rx, T
326  //
327  RegScavenger rs;
328  int32_t lo = Imm & 0xFFFF;
329  NewImm = lo;
330  int Reg =0;
331  int SpReg = 0;
332
333  rs.enterBasicBlock(&MBB);
334  rs.forward(II);
335  //
336  // We need to know which registers can be used, in the case where there
337  // are not enough free registers. We exclude all registers that
338  // are used in the instruction that we are helping.
339  //  // Consider all allocatable registers in the register class initially
340  BitVector Candidates =
341      RI.getAllocatableSet
342      (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
343  // Exclude all the registers being used by the instruction.
344  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
345    MachineOperand &MO = II->getOperand(i);
346    if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
347        !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
348      Candidates.reset(MO.getReg());
349  }
350  //
351  // If the same register was used and defined in an instruction, then
352  // it will not be in the list of candidates.
353  //
354  // we need to analyze the instruction that we are helping.
355  // we need to know if it defines register x but register x is not
356  // present as an operand of the instruction. this tells
357  // whether the register is live before the instruction. if it's not
358  // then we don't need to save it in case there are no free registers.
359  //
360  int DefReg = 0;
361  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
362    MachineOperand &MO = II->getOperand(i);
363    if (MO.isReg() && MO.isDef()) {
364      DefReg = MO.getReg();
365      break;
366    }
367  }
368  //
369  BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
370
371  Available &= Candidates;
372  //
373  // we use T0 for the first register, if we need to save something away.
374  // we use T1 for the second register, if we need to save something away.
375  //
376  unsigned FirstRegSaved =0, SecondRegSaved=0;
377  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
378
379
380  Reg = Available.find_first();
381
382  if (Reg == -1) {
383    Reg = Candidates.find_first();
384    Candidates.reset(Reg);
385    if (DefReg != Reg) {
386      FirstRegSaved = Reg;
387      FirstRegSavedTo = Mips::T0;
388      copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
389    }
390  }
391  else
392    Available.reset(Reg);
393  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
394  NewImm = 0;
395  if (FrameReg == Mips::SP) {
396    SpReg = Available.find_first();
397    if (SpReg == -1) {
398      SpReg = Candidates.find_first();
399      // Candidates.reset(SpReg); // not really needed
400      if (DefReg!= SpReg) {
401        SecondRegSaved = SpReg;
402        SecondRegSavedTo = Mips::T1;
403      }
404      if (SecondRegSaved)
405        copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
406    }
407   else
408     Available.reset(SpReg);
409    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
410    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
411      .addReg(Reg);
412  }
413  else
414    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
415      .addReg(Reg, RegState::Kill);
416  if (FirstRegSaved || SecondRegSaved) {
417    II = llvm::next(II);
418    if (FirstRegSaved)
419      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
420    if (SecondRegSaved)
421      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
422  }
423  return Reg;
424}
425
426/// This function generates the sequence of instructions needed to get the
427/// result of adding register REG and immediate IMM.
428unsigned
429Mips16InstrInfo::basicLoadImmediate(
430  unsigned FrameReg,
431  int64_t Imm, MachineBasicBlock &MBB,
432  MachineBasicBlock::iterator II, DebugLoc DL,
433  unsigned &NewImm) const {
434  const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
435  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
436  unsigned Reg = RegInfo.createVirtualRegister(RC);
437  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
438  NewImm = 0;
439  return Reg;
440}
441
442unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
443  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
444          Opc == Mips::Bimm16  ||
445          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
446          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
447          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
448          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
449          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
450          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
451          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
452          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
453}
454
455void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
456                                  MachineBasicBlock::iterator I,
457                                  unsigned Opc) const {
458  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
459}
460
461
462const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
463  if (validSpImm8(Imm))
464    return get(Mips::AddiuSpImm16);
465  else
466    return get(Mips::AddiuSpImmX16);
467}
468
469void Mips16InstrInfo::BuildAddiuSpImm
470  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
471  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
472  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
473}
474
475const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
476  return new Mips16InstrInfo(TM);
477}
478
479bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
480                                     int64_t Amount) {
481  switch (Opcode) {
482  case Mips::LbRxRyOffMemX16:
483  case Mips::LbuRxRyOffMemX16:
484  case Mips::LhRxRyOffMemX16:
485  case Mips::LhuRxRyOffMemX16:
486  case Mips::SbRxRyOffMemX16:
487  case Mips::ShRxRyOffMemX16:
488  case Mips::LwRxRyOffMemX16:
489  case Mips::SwRxRyOffMemX16:
490  case Mips::SwRxSpImmX16:
491  case Mips::LwRxSpImmX16:
492    return isInt<16>(Amount);
493  case Mips::AddiuRxRyOffMemX16:
494    if ((Reg == Mips::PC) || (Reg == Mips::SP))
495      return isInt<16>(Amount);
496    return isInt<15>(Amount);
497  }
498  llvm_unreachable("unexpected Opcode in validImmediate");
499}
500
501/// Measure the specified inline asm to determine an approximation of its
502/// length.
503/// Comments (which run till the next SeparatorString or newline) do not
504/// count as an instruction.
505/// Any other non-whitespace text is considered an instruction, with
506/// multiple instructions separated by SeparatorString or newlines.
507/// Variable-length instructions are not handled here; this function
508/// may be overloaded in the target code to do that.
509/// We implement the special case of the .space directive taking only an
510/// integer argument, which is the size in bytes. This is used for creating
511/// inline code spacing for testing purposes using inline assembly.
512///
513unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
514                                             const MCAsmInfo &MAI) const {
515
516
517  // Count the number of instructions in the asm.
518  bool atInsnStart = true;
519  unsigned Length = 0;
520  for (; *Str; ++Str) {
521    if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
522                                strlen(MAI.getSeparatorString())) == 0)
523      atInsnStart = true;
524    if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
525      if (strncmp(Str, ".space", 6)==0) {
526        char *EStr; int Sz;
527        Sz = strtol(Str+6, &EStr, 10);
528        while (isspace(*EStr)) ++EStr;
529        if (*EStr=='\0') {
530          DEBUG(dbgs() << "parsed .space " << Sz << '\n');
531          return Sz;
532        }
533      }
534      Length += MAI.getMaxInstLength();
535      atInsnStart = false;
536    }
537    if (atInsnStart && strncmp(Str, MAI.getCommentString(),
538                               strlen(MAI.getCommentString())) == 0)
539      atInsnStart = false;
540  }
541
542  return Length;
543}
544