Mips16InstrInfo.cpp revision 65692c809efa46337bf80f12b1795e785a6e7207 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27
28using namespace llvm;
29
30static cl::opt<bool> NeverUseSaveRestore(
31  "mips16-never-use-save-restore",
32  cl::init(false),
33  cl::desc("For testing ability to adjust stack pointer "
34           "without save/restore instruction"),
35  cl::Hidden);
36
37
38Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39  : MipsInstrInfo(tm, Mips::BimmX16),
40    RI(*tm.getSubtargetImpl(), *this) {}
41
42const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
43  return RI;
44}
45
46/// isLoadFromStackSlot - If the specified machine instruction is a direct
47/// load from a stack slot, return the virtual or physical register number of
48/// the destination along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than loading from the stack slot.
51unsigned Mips16InstrInfo::
52isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57/// isStoreToStackSlot - If the specified machine instruction is a direct
58/// store to a stack slot, return the virtual or physical register number of
59/// the source reg along with the FrameIndex of the loaded stack slot.  If
60/// not, return 0.  This predicate must return 0 if the instruction has
61/// any side effects other than storing to the stack slot.
62unsigned Mips16InstrInfo::
63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
64{
65  return 0;
66}
67
68void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69                                  MachineBasicBlock::iterator I, DebugLoc DL,
70                                  unsigned DestReg, unsigned SrcReg,
71                                  bool KillSrc) const {
72  unsigned Opc = 0;
73
74  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75      Mips::CPURegsRegClass.contains(SrcReg))
76    Opc = Mips::MoveR3216;
77  else if (Mips::CPURegsRegClass.contains(DestReg) &&
78           Mips::CPU16RegsRegClass.contains(SrcReg))
79    Opc = Mips::Move32R16;
80  else if ((SrcReg == Mips::HI) &&
81           (Mips::CPU16RegsRegClass.contains(DestReg)))
82    Opc = Mips::Mfhi16, SrcReg = 0;
83
84  else if ((SrcReg == Mips::LO) &&
85           (Mips::CPU16RegsRegClass.contains(DestReg)))
86    Opc = Mips::Mflo16, SrcReg = 0;
87
88
89  assert(Opc && "Cannot copy registers");
90
91  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
92
93  if (DestReg)
94    MIB.addReg(DestReg, RegState::Define);
95
96  if (SrcReg)
97    MIB.addReg(SrcReg, getKillRegState(KillSrc));
98}
99
100void Mips16InstrInfo::
101storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102                    unsigned SrcReg, bool isKill, int FI,
103                    const TargetRegisterClass *RC,
104                    const TargetRegisterInfo *TRI) const {
105  DebugLoc DL;
106  if (I != MBB.end()) DL = I->getDebugLoc();
107  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108  unsigned Opc = 0;
109  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110    Opc = Mips::SwRxSpImmX16;
111  assert(Opc && "Register class not handled!");
112  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
114}
115
116void Mips16InstrInfo::
117loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118                     unsigned DestReg, int FI,
119                     const TargetRegisterClass *RC,
120                     const TargetRegisterInfo *TRI) const {
121  DebugLoc DL;
122  if (I != MBB.end()) DL = I->getDebugLoc();
123  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
124  unsigned Opc = 0;
125
126  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127    Opc = Mips::LwRxSpImmX16;
128  assert(Opc && "Register class not handled!");
129  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
130    .addMemOperand(MMO);
131}
132
133bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134  MachineBasicBlock &MBB = *MI->getParent();
135  switch(MI->getDesc().getOpcode()) {
136  default:
137    return false;
138  case Mips::BteqzT8CmpX16:
139    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
140    break;
141  case Mips::BteqzT8CmpiX16:
142    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
143                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
144    break;
145  case Mips::BteqzT8SltX16:
146    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
147    break;
148  case Mips::BteqzT8SltiX16:
149    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
150                           Mips::SltiRxImm16, Mips::SltiRxImmX16);
151    break;
152  case Mips::BteqzT8SltuX16:
153    // TBD: figure out a way to get this or remove the instruction
154    // altogether.
155    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
156    break;
157  case Mips::BteqzT8SltiuX16:
158    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
159                           Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
160    break;
161  case Mips::BtnezT8CmpX16:
162    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
163    break;
164  case Mips::BtnezT8CmpiX16:
165    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
166                           Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
167    break;
168  case Mips::BtnezT8SltX16:
169    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
170    break;
171  case Mips::BtnezT8SltiX16:
172    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
173                           Mips::SltiRxImm16, Mips::SltiRxImmX16);
174    break;
175  case Mips::BtnezT8SltuX16:
176    // TBD: figure out a way to get this or remove the instruction
177    // altogether.
178    ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16);
179    break;
180  case Mips::BtnezT8SltiuX16:
181    ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
182                           Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
183    break;
184  case Mips::RetRA16:
185    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
186    break;
187  case Mips::SltCCRxRy16:
188    ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltRxRy16);
189    break;
190  case Mips::SltiCCRxImmX16:
191    ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiRxImm16, Mips::SltiRxImmX16);
192    break;
193  case Mips::SltiuCCRxImmX16:
194    ExpandFEXT_CCRXI16_ins(MBB, MI, Mips::SltiuRxImm16, Mips::SltiuRxImmX16);
195    break;
196  case Mips::SltuCCRxRy16:
197    ExpandFEXT_CCRX16_ins(MBB, MI, Mips::SltuRxRy16);
198    break;
199  }
200
201  MBB.erase(MI);
202  return true;
203}
204
205/// GetOppositeBranchOpc - Return the inverse of the specified
206/// opcode, e.g. turning BEQ to BNE.
207unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
208  switch (Opc) {
209  default:  llvm_unreachable("Illegal opcode!");
210  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
211  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
212  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
213  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
214  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
215  case Mips::BtnezX16: return Mips::BteqzX16;
216  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
217  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
218  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
219  case Mips::BteqzX16: return Mips::BtnezX16;
220  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
221  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
222  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
223  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
224  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
225  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
226  }
227  assert(false && "Implement this function.");
228  return 0;
229}
230
231// Adjust SP by FrameSize bytes. Save RA, S0, S1
232void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
233                    MachineBasicBlock &MBB,
234                    MachineBasicBlock::iterator I) const {
235  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
236  if (!NeverUseSaveRestore) {
237    if (isUInt<11>(FrameSize))
238      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
239    else {
240      int Base = 2040; // should create template function like isUInt that
241                       // returns largest possible n bit unsigned integer
242      int64_t Remainder = FrameSize - Base;
243      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
244      if (isInt<16>(-Remainder))
245        BuildAddiuSpImm(MBB, I, -Remainder);
246      else
247        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
248    }
249
250  }
251  else {
252    //
253    // sw ra, -4[sp]
254    // sw s1, -8[sp]
255    // sw s0, -12[sp]
256
257    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
258                                       Mips::RA);
259    MIB1.addReg(Mips::SP);
260    MIB1.addImm(-4);
261    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
262                                       Mips::S1);
263    MIB2.addReg(Mips::SP);
264    MIB2.addImm(-8);
265    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
266                                       Mips::S0);
267    MIB3.addReg(Mips::SP);
268    MIB3.addImm(-12);
269    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
270  }
271}
272
273// Adjust SP by FrameSize bytes. Restore RA, S0, S1
274void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
275                                   MachineBasicBlock &MBB,
276                                   MachineBasicBlock::iterator I) const {
277  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
278  if (!NeverUseSaveRestore) {
279    if (isUInt<11>(FrameSize))
280      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
281    else {
282      int Base = 2040; // should create template function like isUInt that
283                       // returns largest possible n bit unsigned integer
284      int64_t Remainder = FrameSize - Base;
285      if (isInt<16>(Remainder))
286        BuildAddiuSpImm(MBB, I, Remainder);
287      else
288        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
289      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
290    }
291  }
292  else {
293    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
294    // lw ra, -4[sp]
295    // lw s1, -8[sp]
296    // lw s0, -12[sp]
297    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
298                                       Mips::A0);
299    MIB1.addReg(Mips::SP);
300    MIB1.addImm(-4);
301    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
302                                       Mips::RA);
303     MIB0.addReg(Mips::A0);
304    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
305                                       Mips::S1);
306    MIB2.addReg(Mips::SP);
307    MIB2.addImm(-8);
308    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
309                                       Mips::S0);
310    MIB3.addReg(Mips::SP);
311    MIB3.addImm(-12);
312  }
313
314}
315
316// Adjust SP by Amount bytes where bytes can be up to 32bit number.
317// This can only be called at times that we know that there is at least one free
318// register.
319// This is clearly safe at prologue and epilogue.
320//
321void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
322                                        MachineBasicBlock &MBB,
323                                        MachineBasicBlock::iterator I,
324                                        unsigned Reg1, unsigned Reg2) const {
325  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
326//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
327//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
328//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
329  //
330  // li reg1, constant
331  // move reg2, sp
332  // add reg1, reg1, reg2
333  // move sp, reg1
334  //
335  //
336  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
337  MIB1.addImm(Amount);
338  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
339  MIB2.addReg(Mips::SP, RegState::Kill);
340  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
341  MIB3.addReg(Reg1);
342  MIB3.addReg(Reg2, RegState::Kill);
343  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
344                                                     Mips::SP);
345  MIB4.addReg(Reg1, RegState::Kill);
346}
347
348void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
349                    MachineBasicBlock &MBB,
350                    MachineBasicBlock::iterator I) const {
351   assert(false && "adjust stack pointer amount exceeded");
352}
353
354/// Adjust SP by Amount bytes.
355void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
356                                     MachineBasicBlock &MBB,
357                                     MachineBasicBlock::iterator I) const {
358  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
359    BuildAddiuSpImm(MBB, I, Amount);
360  else
361    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
362}
363
364/// This function generates the sequence of instructions needed to get the
365/// result of adding register REG and immediate IMM.
366unsigned
367Mips16InstrInfo::loadImmediate(unsigned FrameReg,
368                               int64_t Imm, MachineBasicBlock &MBB,
369                               MachineBasicBlock::iterator II, DebugLoc DL,
370                               unsigned &NewImm) const {
371  //
372  // given original instruction is:
373  // Instr rx, T[offset] where offset is too big.
374  //
375  // lo = offset & 0xFFFF
376  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
377  //
378  // let T = temporary register
379  // li T, hi
380  // shl T, 16
381  // add T, Rx, T
382  //
383  RegScavenger rs;
384  int32_t lo = Imm & 0xFFFF;
385  int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
386  NewImm = lo;
387  unsigned Reg =0;
388  unsigned SpReg = 0;
389  rs.enterBasicBlock(&MBB);
390  rs.forward(II);
391  //
392  // we use T0 for the first register, if we need to save something away.
393  // we use T1 for the second register, if we need to save something away.
394  //
395  unsigned FirstRegSaved =0, SecondRegSaved=0;
396  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
397
398  Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
399  if (Reg == 0) {
400    FirstRegSaved = Reg = Mips::V0;
401    FirstRegSavedTo = Mips::T0;
402    copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
403  }
404  else
405    rs.setUsed(Reg);
406  BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
407  BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
408    addImm(16);
409  if (FrameReg == Mips::SP) {
410    SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
411    if (SpReg == 0) {
412      if (Reg != Mips::V1) {
413        SecondRegSaved = SpReg = Mips::V1;
414        SecondRegSavedTo = Mips::T1;
415      }
416      else {
417        SecondRegSaved = SpReg = Mips::V0;
418        SecondRegSavedTo = Mips::T0;
419      }
420      copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
421    }
422    else
423      rs.setUsed(SpReg);
424
425    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
426    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg)
427      .addReg(Reg);
428  }
429  else
430    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
431      .addReg(Reg, RegState::Kill);
432  if (FirstRegSaved || SecondRegSaved) {
433    II = llvm::next(II);
434    if (FirstRegSaved)
435      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
436    if (SecondRegSaved)
437      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
438  }
439  return Reg;
440}
441
442unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
443  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
444          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
445          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
446          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
447          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
448          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
449          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
450          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
451          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
452}
453
454void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
455                                  MachineBasicBlock::iterator I,
456                                  unsigned Opc) const {
457  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
458}
459
460
461void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
462  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
463  unsigned BtOpc, unsigned CmpOpc) const {
464  unsigned regX = I->getOperand(0).getReg();
465  unsigned regY = I->getOperand(1).getReg();
466  MachineBasicBlock *target = I->getOperand(2).getMBB();
467  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY);
468  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
469
470}
471
472void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
473  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
474  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
475  unsigned regX = I->getOperand(0).getReg();
476  int64_t imm = I->getOperand(1).getImm();
477  MachineBasicBlock *target = I->getOperand(2).getMBB();
478  unsigned CmpOpc;
479  if (isUInt<8>(imm))
480    CmpOpc = CmpiOpc;
481  else if (isUInt<16>(imm))
482    CmpOpc = CmpiXOpc;
483  else
484    llvm_unreachable("immediate field not usable");
485  BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
486  BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
487}
488
489void Mips16InstrInfo::ExpandFEXT_CCRX16_ins(
490  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
491  unsigned SltOpc) const {
492  unsigned CC = I->getOperand(0).getReg();
493  unsigned regX = I->getOperand(1).getReg();
494  unsigned regY = I->getOperand(2).getReg();
495  BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addReg(regY);
496  BuildMI(MBB, I, I->getDebugLoc(),
497          get(Mips::MoveR3216), CC).addReg(Mips::T8);
498
499}
500void Mips16InstrInfo::ExpandFEXT_CCRXI16_ins(
501  MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
502  unsigned SltiOpc, unsigned SltiXOpc) const {
503  unsigned CC = I->getOperand(0).getReg();
504  unsigned regX = I->getOperand(1).getReg();
505  int64_t Imm = I->getOperand(2).getImm();
506  unsigned SltOpc = whichOp8u_or_16simm(SltiOpc, SltiXOpc, Imm);
507  BuildMI(MBB, I, I->getDebugLoc(), get(SltOpc)).addReg(regX).addImm(Imm);
508  BuildMI(MBB, I, I->getDebugLoc(),
509          get(Mips::MoveR3216), CC).addReg(Mips::T8);
510
511}
512
513const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
514  if (validSpImm8(Imm))
515    return get(Mips::AddiuSpImm16);
516  else
517    return get(Mips::AddiuSpImmX16);
518}
519
520void Mips16InstrInfo::BuildAddiuSpImm
521  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
522  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
523  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
524}
525
526unsigned Mips16InstrInfo::whichOp8_or_16uimm
527  (unsigned shortOp, unsigned longOp, int64_t Imm) {
528  if (isUInt<8>(Imm))
529    return shortOp;
530  else if (isUInt<16>(Imm))
531    return longOp;
532  else
533    llvm_unreachable("immediate field not usable");
534}
535
536unsigned Mips16InstrInfo::whichOp8u_or_16simm
537  (unsigned shortOp, unsigned longOp, int64_t Imm) {
538  if (isUInt<8>(Imm))
539    return shortOp;
540  else if (isInt<16>(Imm))
541    return longOp;
542  else
543    llvm_unreachable("immediate field not usable");
544}
545
546const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
547  return new Mips16InstrInfo(TM);
548}
549