Mips16InstrInfo.cpp revision 6daba286836e6fb2351e7ebc248e18a5c80e8a31 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/RegisterScavenging.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27
28using namespace llvm;
29
30static cl::opt<bool> NeverUseSaveRestore(
31  "mips16-never-use-save-restore",
32  cl::init(false),
33  cl::desc("For testing ability to adjust stack pointer "
34           "without save/restore instruction"),
35  cl::Hidden);
36
37
38Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39  : MipsInstrInfo(tm, Mips::BimmX16),
40    RI(*tm.getSubtargetImpl(), *this) {}
41
42const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
43  return RI;
44}
45
46/// isLoadFromStackSlot - If the specified machine instruction is a direct
47/// load from a stack slot, return the virtual or physical register number of
48/// the destination along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than loading from the stack slot.
51unsigned Mips16InstrInfo::
52isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57/// isStoreToStackSlot - If the specified machine instruction is a direct
58/// store to a stack slot, return the virtual or physical register number of
59/// the source reg along with the FrameIndex of the loaded stack slot.  If
60/// not, return 0.  This predicate must return 0 if the instruction has
61/// any side effects other than storing to the stack slot.
62unsigned Mips16InstrInfo::
63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
64{
65  return 0;
66}
67
68void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69                                  MachineBasicBlock::iterator I, DebugLoc DL,
70                                  unsigned DestReg, unsigned SrcReg,
71                                  bool KillSrc) const {
72  unsigned Opc = 0;
73
74  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75      Mips::CPURegsRegClass.contains(SrcReg))
76    Opc = Mips::MoveR3216;
77  else if (Mips::CPURegsRegClass.contains(DestReg) &&
78           Mips::CPU16RegsRegClass.contains(SrcReg))
79    Opc = Mips::Move32R16;
80  else if ((SrcReg == Mips::HI) &&
81           (Mips::CPU16RegsRegClass.contains(DestReg)))
82    Opc = Mips::Mfhi16, SrcReg = 0;
83
84  else if ((SrcReg == Mips::LO) &&
85           (Mips::CPU16RegsRegClass.contains(DestReg)))
86    Opc = Mips::Mflo16, SrcReg = 0;
87
88
89  assert(Opc && "Cannot copy registers");
90
91  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
92
93  if (DestReg)
94    MIB.addReg(DestReg, RegState::Define);
95
96  if (SrcReg)
97    MIB.addReg(SrcReg, getKillRegState(KillSrc));
98}
99
100void Mips16InstrInfo::
101storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102                unsigned SrcReg, bool isKill, int FI,
103                const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
104                int64_t Offset) const {
105  DebugLoc DL;
106  if (I != MBB.end()) DL = I->getDebugLoc();
107  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108  unsigned Opc = 0;
109  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110    Opc = Mips::SwRxSpImmX16;
111  assert(Opc && "Register class not handled!");
112  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113    .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
114}
115
116void Mips16InstrInfo::
117loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118                 unsigned DestReg, int FI, const TargetRegisterClass *RC,
119                 const TargetRegisterInfo *TRI, int64_t Offset) const {
120  DebugLoc DL;
121  if (I != MBB.end()) DL = I->getDebugLoc();
122  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
123  unsigned Opc = 0;
124
125  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
126    Opc = Mips::LwRxSpImmX16;
127  assert(Opc && "Register class not handled!");
128  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
129    .addMemOperand(MMO);
130}
131
132bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
133  MachineBasicBlock &MBB = *MI->getParent();
134  switch(MI->getDesc().getOpcode()) {
135  default:
136    return false;
137  case Mips::RetRA16:
138    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
139    break;
140  }
141
142  MBB.erase(MI);
143  return true;
144}
145
146/// GetOppositeBranchOpc - Return the inverse of the specified
147/// opcode, e.g. turning BEQ to BNE.
148unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
149  switch (Opc) {
150  default:  llvm_unreachable("Illegal opcode!");
151  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
152  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
153  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
154  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
155  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
156  case Mips::BtnezX16: return Mips::BteqzX16;
157  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
158  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
159  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
160  case Mips::BteqzX16: return Mips::BtnezX16;
161  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
162  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
163  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
164  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
165  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
166  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
167  }
168  assert(false && "Implement this function.");
169  return 0;
170}
171
172// Adjust SP by FrameSize bytes. Save RA, S0, S1
173void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
174                    MachineBasicBlock &MBB,
175                    MachineBasicBlock::iterator I) const {
176  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
177  if (!NeverUseSaveRestore) {
178    if (isUInt<11>(FrameSize))
179      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
180    else {
181      int Base = 2040; // should create template function like isUInt that
182                       // returns largest possible n bit unsigned integer
183      int64_t Remainder = FrameSize - Base;
184      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
185      if (isInt<16>(-Remainder))
186        BuildAddiuSpImm(MBB, I, -Remainder);
187      else
188        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
189    }
190
191  }
192  else {
193    //
194    // sw ra, -4[sp]
195    // sw s1, -8[sp]
196    // sw s0, -12[sp]
197
198    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
199                                       Mips::RA);
200    MIB1.addReg(Mips::SP);
201    MIB1.addImm(-4);
202    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
203                                       Mips::S1);
204    MIB2.addReg(Mips::SP);
205    MIB2.addImm(-8);
206    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
207                                       Mips::S0);
208    MIB3.addReg(Mips::SP);
209    MIB3.addImm(-12);
210    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
211  }
212}
213
214// Adjust SP by FrameSize bytes. Restore RA, S0, S1
215void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
216                                   MachineBasicBlock &MBB,
217                                   MachineBasicBlock::iterator I) const {
218  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
219  if (!NeverUseSaveRestore) {
220    if (isUInt<11>(FrameSize))
221      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
222    else {
223      int Base = 2040; // should create template function like isUInt that
224                       // returns largest possible n bit unsigned integer
225      int64_t Remainder = FrameSize - Base;
226      if (isInt<16>(Remainder))
227        BuildAddiuSpImm(MBB, I, Remainder);
228      else
229        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
230      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
231    }
232  }
233  else {
234    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
235    // lw ra, -4[sp]
236    // lw s1, -8[sp]
237    // lw s0, -12[sp]
238    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
239                                       Mips::A0);
240    MIB1.addReg(Mips::SP);
241    MIB1.addImm(-4);
242    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
243                                       Mips::RA);
244     MIB0.addReg(Mips::A0);
245    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
246                                       Mips::S1);
247    MIB2.addReg(Mips::SP);
248    MIB2.addImm(-8);
249    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
250                                       Mips::S0);
251    MIB3.addReg(Mips::SP);
252    MIB3.addImm(-12);
253  }
254
255}
256
257// Adjust SP by Amount bytes where bytes can be up to 32bit number.
258// This can only be called at times that we know that there is at least one free
259// register.
260// This is clearly safe at prologue and epilogue.
261//
262void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
263                                        MachineBasicBlock &MBB,
264                                        MachineBasicBlock::iterator I,
265                                        unsigned Reg1, unsigned Reg2) const {
266  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
267//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
268//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
269//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
270  //
271  // li reg1, constant
272  // move reg2, sp
273  // add reg1, reg1, reg2
274  // move sp, reg1
275  //
276  //
277  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
278  MIB1.addImm(Amount);
279  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
280  MIB2.addReg(Mips::SP, RegState::Kill);
281  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
282  MIB3.addReg(Reg1);
283  MIB3.addReg(Reg2, RegState::Kill);
284  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
285                                                     Mips::SP);
286  MIB4.addReg(Reg1, RegState::Kill);
287}
288
289void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
290                    MachineBasicBlock &MBB,
291                    MachineBasicBlock::iterator I) const {
292   assert(false && "adjust stack pointer amount exceeded");
293}
294
295/// Adjust SP by Amount bytes.
296void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
297                                     MachineBasicBlock &MBB,
298                                     MachineBasicBlock::iterator I) const {
299  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
300    BuildAddiuSpImm(MBB, I, Amount);
301  else
302    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
303}
304
305/// This function generates the sequence of instructions needed to get the
306/// result of adding register REG and immediate IMM.
307unsigned
308Mips16InstrInfo::loadImmediate(unsigned FrameReg,
309                               int64_t Imm, MachineBasicBlock &MBB,
310                               MachineBasicBlock::iterator II, DebugLoc DL,
311                               unsigned &NewImm) const {
312  //
313  // given original instruction is:
314  // Instr rx, T[offset] where offset is too big.
315  //
316  // lo = offset & 0xFFFF
317  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
318  //
319  // let T = temporary register
320  // li T, hi
321  // shl T, 16
322  // add T, Rx, T
323  //
324  RegScavenger rs;
325  int32_t lo = Imm & 0xFFFF;
326  int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
327  NewImm = lo;
328  unsigned Reg =0;
329  unsigned SpReg = 0;
330  rs.enterBasicBlock(&MBB);
331  rs.forward(II);
332  //
333  // we use T0 for the first register, if we need to save something away.
334  // we use T1 for the second register, if we need to save something away.
335  //
336  unsigned FirstRegSaved =0, SecondRegSaved=0;
337  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
338
339  Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
340  if (Reg == 0) {
341    FirstRegSaved = Reg = Mips::V0;
342    FirstRegSavedTo = Mips::T0;
343    copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
344  }
345  else
346    rs.setUsed(Reg);
347  BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
348  BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
349    addImm(16);
350  if (FrameReg == Mips::SP) {
351    SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
352    if (SpReg == 0) {
353      if (Reg != Mips::V1) {
354        SecondRegSaved = SpReg = Mips::V1;
355        SecondRegSavedTo = Mips::T1;
356      }
357      else {
358        SecondRegSaved = SpReg = Mips::V0;
359        SecondRegSavedTo = Mips::T0;
360      }
361      copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
362    }
363    else
364      rs.setUsed(SpReg);
365
366    copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
367    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(SpReg)
368      .addReg(Reg);
369  }
370  else
371    BuildMI(MBB, II, DL, get(Mips::  AdduRxRyRz16), Reg).addReg(FrameReg)
372      .addReg(Reg, RegState::Kill);
373  if (FirstRegSaved || SecondRegSaved) {
374    II = llvm::next(II);
375    if (FirstRegSaved)
376      copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
377    if (SecondRegSaved)
378      copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
379  }
380  return Reg;
381}
382
383unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
384  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
385          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
386          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
387          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
388          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
389          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
390          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
391          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
392          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
393}
394
395void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
396                                  MachineBasicBlock::iterator I,
397                                  unsigned Opc) const {
398  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
399}
400
401
402const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
403  if (validSpImm8(Imm))
404    return get(Mips::AddiuSpImm16);
405  else
406    return get(Mips::AddiuSpImmX16);
407}
408
409void Mips16InstrInfo::BuildAddiuSpImm
410  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
411  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
412  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
413}
414
415const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
416  return new Mips16InstrInfo(TM);
417}
418