Mips16InstrInfo.cpp revision c09856b5357af621fcb84a7b2b6bfbf630c244ef 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "MipsTargetMachine.h"
16#include "MipsMachineFunction.h"
17#include "InstPrinter/MipsInstPrinter.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/ADT/StringRef.h"
24
25using namespace llvm;
26
27Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
28  : MipsInstrInfo(tm, Mips::BimmX16),
29    RI(*tm.getSubtargetImpl()) {}
30
31const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
32  return RI;
33}
34
35/// isLoadFromStackSlot - If the specified machine instruction is a direct
36/// load from a stack slot, return the virtual or physical register number of
37/// the destination along with the FrameIndex of the loaded stack slot.  If
38/// not, return 0.  This predicate must return 0 if the instruction has
39/// any side effects other than loading from the stack slot.
40unsigned Mips16InstrInfo::
41isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
42{
43  return 0;
44}
45
46/// isStoreToStackSlot - If the specified machine instruction is a direct
47/// store to a stack slot, return the virtual or physical register number of
48/// the source reg along with the FrameIndex of the loaded stack slot.  If
49/// not, return 0.  This predicate must return 0 if the instruction has
50/// any side effects other than storing to the stack slot.
51unsigned Mips16InstrInfo::
52isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
53{
54  return 0;
55}
56
57void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58                                  MachineBasicBlock::iterator I, DebugLoc DL,
59                                  unsigned DestReg, unsigned SrcReg,
60                                  bool KillSrc) const {
61  unsigned Opc = 0;
62
63  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
64      Mips::CPURegsRegClass.contains(SrcReg))
65    Opc = Mips::MoveR3216;
66  else if (Mips::CPURegsRegClass.contains(DestReg) &&
67           Mips::CPU16RegsRegClass.contains(SrcReg))
68    Opc = Mips::Move32R16;
69  else if ((SrcReg == Mips::HI) &&
70           (Mips::CPU16RegsRegClass.contains(DestReg)))
71    Opc = Mips::Mfhi16, SrcReg = 0;
72
73  else if ((SrcReg == Mips::LO) &&
74           (Mips::CPU16RegsRegClass.contains(DestReg)))
75    Opc = Mips::Mflo16, SrcReg = 0;
76
77
78  assert(Opc && "Cannot copy registers");
79
80  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
81
82  if (DestReg)
83    MIB.addReg(DestReg, RegState::Define);
84
85  if (SrcReg)
86    MIB.addReg(SrcReg, getKillRegState(KillSrc));
87}
88
89void Mips16InstrInfo::
90storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91                    unsigned SrcReg, bool isKill, int FI,
92                    const TargetRegisterClass *RC,
93                    const TargetRegisterInfo *TRI) const {
94  DebugLoc DL;
95  if (I != MBB.end()) DL = I->getDebugLoc();
96  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
97  unsigned Opc = 0;
98  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
99    Opc = Mips::SwRxSpImmX16;
100  assert(Opc && "Register class not handled!");
101  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
102    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
103}
104
105void Mips16InstrInfo::
106loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
107                     unsigned DestReg, int FI,
108                     const TargetRegisterClass *RC,
109                     const TargetRegisterInfo *TRI) const {
110  DebugLoc DL;
111  if (I != MBB.end()) DL = I->getDebugLoc();
112  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
113  unsigned Opc = 0;
114
115  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
116    Opc = Mips::LwRxSpImmX16;
117  assert(Opc && "Register class not handled!");
118  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
119    .addMemOperand(MMO);
120}
121
122bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
123  MachineBasicBlock &MBB = *MI->getParent();
124
125  switch(MI->getDesc().getOpcode()) {
126  default:
127    return false;
128  case Mips::RetRA16:
129    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
130    break;
131  }
132
133  MBB.erase(MI);
134  return true;
135}
136
137/// GetOppositeBranchOpc - Return the inverse of the specified
138/// opcode, e.g. turning BEQ to BNE.
139unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
140  switch (Opc) {
141  default:  llvm_unreachable("Illegal opcode!");
142  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
143  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
144  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
145  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
146  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
147  case Mips::BtnezX16: return Mips::BteqzX16;
148  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
149  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
150  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
151  case Mips::BteqzX16: return Mips::BtnezX16;
152  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
153  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
154  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
155  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
156  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
157  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
158  }
159  assert(false && "Implement this function.");
160  return 0;
161}
162
163unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
164  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
165          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
166          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
167          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
168          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
169          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
170          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
171          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
172          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
173}
174
175void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
176                                  MachineBasicBlock::iterator I,
177                                  unsigned Opc) const {
178  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
179}
180
181const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
182  return new Mips16InstrInfo(TM);
183}
184