Mips16InstrInfo.cpp revision e11dda8631f1e65417971ee0c2f7a661fc7d0fd7 
1//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips16InstrInfo.h"
15#include "InstPrinter/MipsInstPrinter.h"
16#include "MipsMachineFunction.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/TargetRegistry.h"
25
26using namespace llvm;
27
28static cl::opt<bool> NeverUseSaveRestore(
29  "mips16-never-use-save-restore",
30  cl::init(false),
31  cl::desc("For testing ability to adjust stack pointer "
32           "without save/restore instruction"),
33  cl::Hidden);
34
35
36Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
37  : MipsInstrInfo(tm, Mips::BimmX16),
38    RI(*tm.getSubtargetImpl(), *this) {}
39
40const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
41  return RI;
42}
43
44/// isLoadFromStackSlot - If the specified machine instruction is a direct
45/// load from a stack slot, return the virtual or physical register number of
46/// the destination along with the FrameIndex of the loaded stack slot.  If
47/// not, return 0.  This predicate must return 0 if the instruction has
48/// any side effects other than loading from the stack slot.
49unsigned Mips16InstrInfo::
50isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
51{
52  return 0;
53}
54
55/// isStoreToStackSlot - If the specified machine instruction is a direct
56/// store to a stack slot, return the virtual or physical register number of
57/// the source reg along with the FrameIndex of the loaded stack slot.  If
58/// not, return 0.  This predicate must return 0 if the instruction has
59/// any side effects other than storing to the stack slot.
60unsigned Mips16InstrInfo::
61isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
62{
63  return 0;
64}
65
66void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
67                                  MachineBasicBlock::iterator I, DebugLoc DL,
68                                  unsigned DestReg, unsigned SrcReg,
69                                  bool KillSrc) const {
70  unsigned Opc = 0;
71
72  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
73      Mips::CPURegsRegClass.contains(SrcReg))
74    Opc = Mips::MoveR3216;
75  else if (Mips::CPURegsRegClass.contains(DestReg) &&
76           Mips::CPU16RegsRegClass.contains(SrcReg))
77    Opc = Mips::Move32R16;
78  else if ((SrcReg == Mips::HI) &&
79           (Mips::CPU16RegsRegClass.contains(DestReg)))
80    Opc = Mips::Mfhi16, SrcReg = 0;
81
82  else if ((SrcReg == Mips::LO) &&
83           (Mips::CPU16RegsRegClass.contains(DestReg)))
84    Opc = Mips::Mflo16, SrcReg = 0;
85
86
87  assert(Opc && "Cannot copy registers");
88
89  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
90
91  if (DestReg)
92    MIB.addReg(DestReg, RegState::Define);
93
94  if (SrcReg)
95    MIB.addReg(SrcReg, getKillRegState(KillSrc));
96}
97
98void Mips16InstrInfo::
99storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
100                    unsigned SrcReg, bool isKill, int FI,
101                    const TargetRegisterClass *RC,
102                    const TargetRegisterInfo *TRI) const {
103  DebugLoc DL;
104  if (I != MBB.end()) DL = I->getDebugLoc();
105  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
106  unsigned Opc = 0;
107  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
108    Opc = Mips::SwRxSpImmX16;
109  assert(Opc && "Register class not handled!");
110  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
111    .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
112}
113
114void Mips16InstrInfo::
115loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
116                     unsigned DestReg, int FI,
117                     const TargetRegisterClass *RC,
118                     const TargetRegisterInfo *TRI) const {
119  DebugLoc DL;
120  if (I != MBB.end()) DL = I->getDebugLoc();
121  MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
122  unsigned Opc = 0;
123
124  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
125    Opc = Mips::LwRxSpImmX16;
126  assert(Opc && "Register class not handled!");
127  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
128    .addMemOperand(MMO);
129}
130
131bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
132  MachineBasicBlock &MBB = *MI->getParent();
133
134  switch(MI->getDesc().getOpcode()) {
135  default:
136    return false;
137  case Mips::RetRA16:
138    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
139    break;
140  }
141
142  MBB.erase(MI);
143  return true;
144}
145
146/// GetOppositeBranchOpc - Return the inverse of the specified
147/// opcode, e.g. turning BEQ to BNE.
148unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
149  switch (Opc) {
150  default:  llvm_unreachable("Illegal opcode!");
151  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
152  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
153  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
154  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
155  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
156  case Mips::BtnezX16: return Mips::BteqzX16;
157  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
158  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
159  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
160  case Mips::BteqzX16: return Mips::BtnezX16;
161  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
162  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
163  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
164  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
165  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
166  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
167  }
168  assert(false && "Implement this function.");
169  return 0;
170}
171
172// Adjust SP by FrameSize bytes. Save RA, S0, S1
173void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
174                    MachineBasicBlock &MBB,
175                    MachineBasicBlock::iterator I) const {
176  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
177  if (!NeverUseSaveRestore) {
178    if (isUInt<11>(FrameSize))
179      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
180    else {
181      int Base = 2040; // should create template function like isUInt that
182                       // returns largest possible n bit unsigned integer
183      int64_t Remainder = FrameSize - Base;
184      BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
185      if (isInt<16>(-Remainder))
186        BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(-Remainder);
187      else
188        adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
189    }
190
191  }
192  else {
193    //
194    // sw ra, -4[sp]
195    // sw s1, -8[sp]
196    // sw s0, -12[sp]
197
198    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
199                                       Mips::RA);
200    MIB1.addReg(Mips::SP);
201    MIB1.addImm(-4);
202    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
203                                       Mips::S1);
204    MIB2.addReg(Mips::SP);
205    MIB2.addImm(-8);
206    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
207                                       Mips::S0);
208    MIB3.addReg(Mips::SP);
209    MIB3.addImm(-12);
210    adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
211  }
212}
213
214// Adjust SP by FrameSize bytes. Restore RA, S0, S1
215void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
216                                   MachineBasicBlock &MBB,
217                                   MachineBasicBlock::iterator I) const {
218  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
219  if (!NeverUseSaveRestore) {
220    if (isUInt<11>(FrameSize))
221      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
222    else {
223      int Base = 2040; // should create template function like isUInt that
224                       // returns largest possible n bit unsigned integer
225      int64_t Remainder = FrameSize - Base;
226      if (isInt<16>(Remainder))
227        BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(Remainder);
228      else
229        adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
230      BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
231    }
232  }
233  else {
234    adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
235    // lw ra, -4[sp]
236    // lw s1, -8[sp]
237    // lw s0, -12[sp]
238    MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
239                                       Mips::A0);
240    MIB1.addReg(Mips::SP);
241    MIB1.addImm(-4);
242    MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
243                                       Mips::RA);
244     MIB0.addReg(Mips::A0);
245    MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
246                                       Mips::S1);
247    MIB2.addReg(Mips::SP);
248    MIB2.addImm(-8);
249    MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
250                                       Mips::S0);
251    MIB3.addReg(Mips::SP);
252    MIB3.addImm(-12);
253  }
254
255}
256
257// Adjust SP by Amount bytes where bytes can be up to 32bit number.
258// This can only be called at times that we know that there is at least one free
259// register.
260// This is clearly safe at prologue and epilogue.
261//
262void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
263                                        MachineBasicBlock &MBB,
264                                        MachineBasicBlock::iterator I,
265                                        unsigned Reg1, unsigned Reg2) const {
266  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
267//  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
268//  unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
269//  unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
270  //
271  // li reg1, constant
272  // move reg2, sp
273  // add reg1, reg1, reg2
274  // move sp, reg1
275  //
276  //
277  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
278  MIB1.addImm(Amount);
279  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
280  MIB2.addReg(Mips::SP, RegState::Kill);
281  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
282  MIB3.addReg(Reg1);
283  MIB3.addReg(Reg2, RegState::Kill);
284  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
285                                                     Mips::SP);
286  MIB4.addReg(Reg1, RegState::Kill);
287}
288
289void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
290                    MachineBasicBlock &MBB,
291                    MachineBasicBlock::iterator I) const {
292   assert(false && "adjust stack pointer amount exceeded");
293}
294
295/// Adjust SP by Amount bytes.
296void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
297                                     MachineBasicBlock &MBB,
298                                     MachineBasicBlock::iterator I) const {
299  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
300  if (isInt<16>(Amount))  // need to change to addiu sp, ....and isInt<16>
301    BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(Amount);
302  else
303    adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
304}
305
306/// This function generates the sequence of instructions needed to get the
307/// result of adding register REG and immediate IMM.
308unsigned
309Mips16InstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
310                               MachineBasicBlock::iterator II, DebugLoc DL,
311                               unsigned *NewImm) const {
312
313  return 0;
314}
315
316unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
317  return (Opc == Mips::BeqzRxImmX16   || Opc == Mips::BimmX16  ||
318          Opc == Mips::BnezRxImmX16   || Opc == Mips::BteqzX16 ||
319          Opc == Mips::BteqzT8CmpX16  || Opc == Mips::BteqzT8CmpiX16 ||
320          Opc == Mips::BteqzT8SltX16  || Opc == Mips::BteqzT8SltuX16  ||
321          Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
322          Opc == Mips::BtnezX16       || Opc == Mips::BtnezT8CmpX16 ||
323          Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
324          Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
325          Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
326}
327
328void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
329                                  MachineBasicBlock::iterator I,
330                                  unsigned Opc) const {
331  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
332}
333
334const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
335  return new Mips16InstrInfo(TM);
336}
337