Mips16InstrInfo.h revision 0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d 
1//===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips16 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPS16INSTRUCTIONINFO_H
15#define MIPS16INSTRUCTIONINFO_H
16
17#include "MipsInstrInfo.h"
18
19namespace llvm {
20
21class Mips16InstrInfo : public MipsInstrInfo {
22public:
23  explicit Mips16InstrInfo(MipsTargetMachine &TM);
24
25  /// isLoadFromStackSlot - If the specified machine instruction is a direct
26  /// load from a stack slot, return the virtual or physical register number of
27  /// the destination along with the FrameIndex of the loaded stack slot.  If
28  /// not, return 0.  This predicate must return 0 if the instruction has
29  /// any side effects other than loading from the stack slot.
30  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
31                                       int &FrameIndex) const;
32
33  /// isStoreToStackSlot - If the specified machine instruction is a direct
34  /// store to a stack slot, return the virtual or physical register number of
35  /// the source reg along with the FrameIndex of the loaded stack slot.  If
36  /// not, return 0.  This predicate must return 0 if the instruction has
37  /// any side effects other than storing to the stack slot.
38  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
39                                      int &FrameIndex) const;
40
41  virtual void copyPhysReg(MachineBasicBlock &MBB,
42                           MachineBasicBlock::iterator MI, DebugLoc DL,
43                           unsigned DestReg, unsigned SrcReg,
44                           bool KillSrc) const;
45
46  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
47                                   MachineBasicBlock::iterator MBBI,
48                                   unsigned SrcReg, bool isKill, int FrameIndex,
49                                   const TargetRegisterClass *RC,
50                                   const TargetRegisterInfo *TRI) const;
51
52  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
53                                    MachineBasicBlock::iterator MBBI,
54                                    unsigned DestReg, int FrameIndex,
55                                    const TargetRegisterClass *RC,
56                                    const TargetRegisterInfo *TRI) const;
57
58  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
59
60  virtual unsigned GetOppositeBranchOpc(unsigned Opc) const;
61
62private:
63  virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const;
64
65  void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
66                   unsigned Opc) const;
67};
68
69}
70
71#endif
72