Mips16InstrInfo.td revision 0fdf3b029b35f495d7261fe78737e434edc84758
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// RRR-type instruction format 16// 17 18class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 19 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 20 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 21 22// 23// I8_MOVR32 instruction format (used only by the MOVR32 instructio 24// 25class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 26 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 27 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 28 29// 30// I8_MOV32R instruction format (used only by MOV32R instruction) 31// 32class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 33 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 34 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 35 36// 37// EXT-RI instruction format 38// 39 40class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 41 InstrItinClass itin>: 42 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 43 !strconcat(asmstr, asmstr2), [], itin>; 44 45class FEXT_RI16_ins<bits<5> _op, string asmstr, 46 InstrItinClass itin>: 47 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 48 49class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 50 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 51 52 53class FEXT_2RI16_ins<bits<5> _op, string asmstr, 54 InstrItinClass itin>: 55 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 56 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 57 let Constraints = "$rx_ = $rx"; 58} 59 60 61// 62// RR-type instruction format 63// 64 65class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 66 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 67 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 68} 69 70class FRxRxRy16_ins<bits<5> f, string asmstr, 71 InstrItinClass itin> : 72 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 73 !strconcat(asmstr, "\t$rz, $ry"), 74 [], itin> { 75 let Constraints = "$rx = $rz"; 76} 77 78let rx=0 in 79class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 80 string asmstr, InstrItinClass itin>: 81 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 82 [], itin> ; 83 84// 85// EXT-RRI instruction format 86// 87 88class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 89 InstrItinClass itin>: 90 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 91 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 92 93class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 94 InstrItinClass itin>: 95 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 96 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 97 98// 99// EXT-SHIFT instruction format 100// 101class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 102 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 103 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 104 105// 106// Address operand 107def mem16 : Operand<i32> { 108 let PrintMethod = "printMemOperand"; 109 let MIOperandInfo = (ops CPU16Regs, simm16); 110 let EncoderMethod = "getMemEncoding"; 111} 112 113// 114// Some general instruction class info 115// 116// 117 118class ArithLogic16Defs<bit isCom=0> { 119 bits<5> shamt = 0; 120 bit isCommutable = isCom; 121 bit isReMaterializable = 1; 122 bit neverHasSideEffects = 1; 123} 124 125// 126 127// Format: ADDIU rx, immediate MIPS16e 128// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 129// To add a constant to a 32-bit integer. 130// 131def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 132 133def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 134 ArithLogic16Defs<0>; 135 136// 137 138// Format: ADDIU rx, pc, immediate MIPS16e 139// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 140// To add a constant to the program counter. 141// 142def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 143// 144// Format: ADDU rz, rx, ry MIPS16e 145// Purpose: Add Unsigned Word (3-Operand) 146// To add 32-bit integers. 147// 148 149def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 150 151// 152// Format: AND rx, ry MIPS16e 153// Purpose: AND 154// To do a bitwise logical AND. 155 156def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 157 158// 159// Format: JR ra MIPS16e 160// Purpose: Jump Register Through Register ra 161// To execute a branch to the instruction address in the return 162// address register. 163// 164 165def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>; 166 167// 168// Format: LB ry, offset(rx) MIPS16e 169// Purpose: Load Byte (Extended) 170// To load a byte from memory as a signed value. 171// 172def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IIAlu>; 173 174// 175// Format: LBU ry, offset(rx) MIPS16e 176// Purpose: Load Byte Unsigned (Extended) 177// To load a byte from memory as a unsigned value. 178// 179def LbuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IIAlu>; 180 181// 182// Format: LH ry, offset(rx) MIPS16e 183// Purpose: Load Halfword signed (Extended) 184// To load a halfword from memory as a signed value. 185// 186def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IIAlu>; 187 188// 189// Format: LHU ry, offset(rx) MIPS16e 190// Purpose: Load Halfword unsigned (Extended) 191// To load a halfword from memory as an unsigned value. 192// 193def LhuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IIAlu>; 194 195// 196// Format: LI rx, immediate MIPS16e 197// Purpose: Load Immediate (Extended) 198// To load a constant into a GPR. 199// 200def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 201 202// 203// Format: LW ry, offset(rx) MIPS16e 204// Purpose: Load Word (Extended) 205// To load a word from memory as a signed value. 206// 207def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>; 208 209// 210// Format: MOVE r32, rz MIPS16e 211// Purpose: Move 212// To move the contents of a GPR to a GPR. 213// 214def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 215 216// 217// Format: MOVE ry, r32 MIPS16e 218//Purpose: Move 219// To move the contents of a GPR to a GPR. 220// 221def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 222 223// 224// Format: NEG rx, ry MIPS16e 225// Purpose: Negate 226// To negate an integer value. 227// 228def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>; 229 230// 231// Format: NOT rx, ry MIPS16e 232// Purpose: Not 233// To complement an integer value 234// 235def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>; 236 237// 238// Format: OR rx, ry MIPS16e 239// Purpose: Or 240// To do a bitwise logical OR. 241// 242def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 243 244// 245// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 246// (All args are optional) MIPS16e 247// Purpose: Restore Registers and Deallocate Stack Frame 248// To deallocate a stack frame before exit from a subroutine, 249// restoring return address and static registers, and adjusting 250// stack 251// 252 253// fixed form for restoring RA and the frame 254// for direct object emitter, encoding needs to be adjusted for the 255// frame size 256// 257let ra=1, s=0,s0=1,s1=1 in 258def RestoreRaF16: 259 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 260 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad > { 261 let isCodeGenOnly = 1; 262} 263 264// 265// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 266// MIPS16e 267// Purpose: Save Registers and Set Up Stack Frame 268// To set up a stack frame on entry to a subroutine, 269// saving return address and static registers, and adjusting stack 270// 271let ra=1, s=1,s0=1,s1=1 in 272def SaveRaF16: 273 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 274 "save \t$$ra, $$s0, $$s1, $frame_size", [], IILoad > { 275 let isCodeGenOnly = 1; 276} 277// 278// Format: SB ry, offset(rx) MIPS16e 279// Purpose: Store Byte (Extended) 280// To store a byte to memory. 281// 282def SbRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIAlu>; 283 284// 285// Format: SH ry, offset(rx) MIPS16e 286// Purpose: Store Halfword (Extended) 287// To store a halfword to memory. 288// 289def ShRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIAlu>; 290 291// 292// Format: SLL rx, ry, sa MIPS16e 293// Purpose: Shift Word Left Logical (Extended) 294// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 295// 296def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 297 298// 299// Format: SLLV ry, rx MIPS16e 300// Purpose: Shift Word Left Logical Variable 301// To execute a left-shift of a word by a variable number of bits. 302// 303def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 304 305 306// 307// Format: SRAV ry, rx MIPS16e 308// Purpose: Shift Word Right Arithmetic Variable 309// To execute an arithmetic right-shift of a word by a variable 310// number of bits. 311// 312def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 313 314 315// 316// Format: SRA rx, ry, sa MIPS16e 317// Purpose: Shift Word Right Arithmetic (Extended) 318// To execute an arithmetic right-shift of a word by a fixed 319// number of bits—1 to 8 bits. 320// 321def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 322 323 324// 325// Format: SRLV ry, rx MIPS16e 326// Purpose: Shift Word Right Logical Variable 327// To execute a logical right-shift of a word by a variable 328// number of bits. 329// 330def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 331 332 333// 334// Format: SRL rx, ry, sa MIPS16e 335// Purpose: Shift Word Right Logical (Extended) 336// To execute a logical right-shift of a word by a fixed 337// number of bits—1 to 31 bits. 338// 339def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 340 341// 342// Format: SUBU rz, rx, ry MIPS16e 343// Purpose: Subtract Unsigned Word 344// To subtract 32-bit integers 345// 346def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 347 348// 349// Format: SW ry, offset(rx) MIPS16e 350// Purpose: Store Word (Extended) 351// To store a word to memory. 352// 353def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIAlu>; 354 355// 356// Format: XOR rx, ry MIPS16e 357// Purpose: Xor 358// To do a bitwise logical XOR. 359// 360def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 361 362class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 363 let Predicates = [InMips16Mode]; 364} 365 366// Unary Arith/Logic 367// 368class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 369 Mips16Pat<(OpNode CPU16Regs:$r), 370 (I CPU16Regs:$r)>; 371 372def: ArithLogicU_pat<not, NotRxRy16>; 373def: ArithLogicU_pat<ineg, NegRxRy16>; 374 375class ArithLogic16_pat<SDNode OpNode, Instruction I> : 376 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 377 (I CPU16Regs:$l, CPU16Regs:$r)>; 378 379def: ArithLogic16_pat<add, AdduRxRyRz16>; 380def: ArithLogic16_pat<and, AndRxRxRy16>; 381def: ArithLogic16_pat<or, OrRxRxRy16>; 382def: ArithLogic16_pat<sub, SubuRxRyRz16>; 383def: ArithLogic16_pat<xor, XorRxRxRy16>; 384 385// Arithmetic and logical instructions with 2 register operands. 386 387class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 388 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 389 (I CPU16Regs:$in, imm_type:$imm)>; 390 391def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 392def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 393def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 394def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 395 396class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 397 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 398 (I CPU16Regs:$r, CPU16Regs:$ra)>; 399 400def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 401def: shift_rotate_reg16_pat<sra, SravRxRy16>; 402def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 403 404class LoadM16_pat<PatFrag OpNode, Instruction I> : 405 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>; 406 407def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 408def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 409def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 410def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 411def: LoadM16_pat<load, LwRxRyOffMemX16>; 412 413class StoreM16_pat<PatFrag OpNode, Instruction I> : 414 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>; 415 416def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 417def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 418def: StoreM16_pat<store, SwRxRyOffMemX16>; 419 420 421// Jump and Link (Call) 422let isCall=1, hasDelaySlot=1 in 423def JumpLinkReg16: 424 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 425 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 426 427// Mips16 pseudos 428let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 429 hasExtraSrcRegAllocReq = 1 in 430def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 431 432// Small immediates 433def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 434 435def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 436 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 437