Mips16InstrInfo.td revision 182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2 
1//===- Mips16InstrInfo.td - Target Description for Mips16  -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips16 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
15  let Predicates = [InMips16Mode];
16}
17
18// Mips16 pseudos
19let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
20    hasExtraSrcRegAllocReq = 1 in
21def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
22
23def LI16E      : FEXT_RI16<0b01101, (outs CPU16Regs:$rx),
24                           (ins uimm16:$amt),
25                           !strconcat("li", "\t$rx, $amt"),
26                           [(set CPU16Regs:$rx, immZExt16:$amt )],IILoad>;
27
28let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
29    isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0  in
30def RET16 : FRR16_JALRC<(outs), (ins CPURAReg:$target), "jr\t$target", [],
31                        IIBranch>;
32
33// As stack alignment is always done with addiu, we need a 16-bit immediate
34let Defs = [SP], Uses = [SP] in {
35def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
36                                      "!ADJCALLSTACKDOWN $amt",
37                                      [(callseq_start timm:$amt)]>;
38def ADJCALLSTACKUP16   : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
39                                      "!ADJCALLSTACKUP $amt1",
40                                      [(callseq_end timm:$amt1, timm:$amt2)]>;
41}
42
43
44// Jump and Link (Call)
45let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
46def JumpLinkReg16:
47    FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops),
48                "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
49
50// Small immediates
51def : Mips16Pat<(i32 immZExt16:$in), (LI16E immZExt16:$in)>;
52