Mips16InstrInfo.td revision 1858786285139b87961d9ca08de91dcd59364afb
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// 36// I8 instruction format 37// 38 39class FI816_ins_base<bits<3> _func, string asmstr, 40 string asmstr2, InstrItinClass itin>: 41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 42 [], itin>; 43 44 45class FI816_SP_ins<bits<3> _func, string asmstr, 46 InstrItinClass itin>: 47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 48 49// 50// RI instruction format 51// 52 53 54class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 55 InstrItinClass itin>: 56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 57 !strconcat(asmstr, asmstr2), [], itin>; 58 59class FRI16_ins<bits<5> op, string asmstr, 60 InstrItinClass itin>: 61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 62 63class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 64 InstrItinClass itin>: 65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 66 !strconcat(asmstr, asmstr2), [], itin>; 67 68class FRI16R_ins<bits<5> op, string asmstr, 69 InstrItinClass itin>: 70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 71 72class F2RI16_ins<bits<5> _op, string asmstr, 73 InstrItinClass itin>: 74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 76 let Constraints = "$rx_ = $rx"; 77} 78 79class FRI16_B_ins<bits<5> _op, string asmstr, 80 InstrItinClass itin>: 81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 83// 84// Compare a register and immediate and place result in CC 85// Implicit use of T8 86// 87// EXT-CCRR Instruction format 88// 89class FEXT_CCRXI16_ins<string asmstr>: 90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 92 let isCodeGenOnly=1; 93 let usesCustomInserter = 1; 94} 95 96// JAL and JALX instruction format 97// 98class FJAL16_ins<bits<1> _X, string asmstr, 99 InstrItinClass itin>: 100 FJAL16<_X, (outs), (ins simm20:$imm), 101 !strconcat(asmstr, "\t$imm\n\tnop"),[], 102 itin> { 103 let isCodeGenOnly=1; 104} 105// 106// EXT-I instruction format 107// 108class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 109 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 110 !strconcat(asmstr, "\t$imm16"),[], itin>; 111 112// 113// EXT-I8 instruction format 114// 115 116class FEXT_I816_ins_base<bits<3> _func, string asmstr, 117 string asmstr2, InstrItinClass itin>: 118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 119 [], itin>; 120 121class FEXT_I816_ins<bits<3> _func, string asmstr, 122 InstrItinClass itin>: 123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 124 125class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 126 InstrItinClass itin>: 127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 128 129// 130// Assembler formats in alphabetical order. 131// Natural and pseudos are mixed together. 132// 133// Compare two registers and place result in CC 134// Implicit use of T8 135// 136// CC-RR Instruction format 137// 138class FCCRR16_ins<string asmstr> : 139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 141 let isCodeGenOnly=1; 142 let usesCustomInserter = 1; 143} 144 145// 146// EXT-RI instruction format 147// 148 149class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 150 InstrItinClass itin>: 151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 152 !strconcat(asmstr, asmstr2), [], itin>; 153 154class FEXT_RI16_ins<bits<5> _op, string asmstr, 155 InstrItinClass itin>: 156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 157 158class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 159 InstrItinClass itin>: 160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 161 !strconcat(asmstr, asmstr2), [], itin>; 162 163class FEXT_RI16R_ins<bits<5> _op, string asmstr, 164 InstrItinClass itin>: 165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 166 167class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 169 170class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 171 InstrItinClass itin>: 172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 174 175class FEXT_2RI16_ins<bits<5> _op, string asmstr, 176 InstrItinClass itin>: 177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 179 let Constraints = "$rx_ = $rx"; 180} 181 182 183// this has an explicit sp argument that we ignore to work around a problem 184// in the compiler 185class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 186 InstrItinClass itin>: 187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 189 190class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr, 191 InstrItinClass itin>: 192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm), 193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 194 195// 196// EXT-RRI instruction format 197// 198 199class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 200 InstrItinClass itin>: 201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 203 204class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 205 InstrItinClass itin>: 206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 208 209// 210// 211// EXT-RRI-A instruction format 212// 213 214class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 215 InstrItinClass itin>: 216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 218 219// 220// EXT-SHIFT instruction format 221// 222class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 225 226// 227// EXT-T8I8 228// 229class FEXT_T8I816_ins<string asmstr, string asmstr2>: 230 MipsPseudo16<(outs), 231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 233 !strconcat(asmstr, "\t$imm"))),[]> { 234 let isCodeGenOnly=1; 235 let usesCustomInserter = 1; 236} 237 238// 239// EXT-T8I8I 240// 241class FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 242 MipsPseudo16<(outs), 243 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 244 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 245 !strconcat(asmstr, "\t$targ"))), []> { 246 let isCodeGenOnly=1; 247 let usesCustomInserter = 1; 248} 249// 250 251 252// 253// I8_MOVR32 instruction format (used only by the MOVR32 instructio 254// 255class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 256 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32), 257 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 258 259// 260// I8_MOV32R instruction format (used only by MOV32R instruction) 261// 262 263class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 264 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz), 265 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 266 267// 268// This are pseudo formats for multiply 269// This first one can be changed to non pseudo now. 270// 271// MULT 272// 273class FMULT16_ins<string asmstr, InstrItinClass itin> : 274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 275 !strconcat(asmstr, "\t$rx, $ry"), []>; 276 277// 278// MULT-LO 279// 280class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 283 let isCodeGenOnly=1; 284} 285 286// 287// RR-type instruction format 288// 289 290class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 293} 294 295class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : 296 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 297 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 298} 299 300class FRRTR16_ins<string asmstr> : 301 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 302 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 303 304// 305// maybe refactor but need a $zero as a dummy first parameter 306// 307class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 308 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 309 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 310 311class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 312 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 313 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 314 315 316class FRR16_M_ins<bits<5> f, string asmstr, 317 InstrItinClass itin> : 318 FRR16<f, (outs CPU16Regs:$rx), (ins), 319 !strconcat(asmstr, "\t$rx"), [], itin>; 320 321class FRxRxRy16_ins<bits<5> f, string asmstr, 322 InstrItinClass itin> : 323 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 324 !strconcat(asmstr, "\t$rz, $ry"), 325 [], itin> { 326 let Constraints = "$rx = $rz"; 327} 328 329let rx=0 in 330class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 331 string asmstr, InstrItinClass itin>: 332 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 333 [], itin> ; 334 335 336class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 337 string asmstr, InstrItinClass itin>: 338 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 339 !strconcat(asmstr, "\t $rx"), [], itin> ; 340 341// 342// RRR-type instruction format 343// 344 345class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 346 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 347 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 348 349// 350// These Sel patterns support the generation of conditional move 351// pseudo instructions. 352// 353// The nomenclature uses the components making up the pseudo and may 354// be a bit counter intuitive when compared with the end result we seek. 355// For example using a bqez in the example directly below results in the 356// conditional move being done if the tested register is not zero. 357// I considered in easier to check by keeping the pseudo consistent with 358// it's components but it could have been done differently. 359// 360// The simplest case is when can test and operand directly and do the 361// conditional move based on a simple mips16 conditional 362// branch instruction. 363// for example: 364// if $op == beqz or bnez: 365// 366// $op1 $rt, .+4 367// move $rd, $rs 368// 369// if $op == beqz, then if $rt != 0, then the conditional assignment 370// $rd = $rs is done. 371 372// if $op == bnez, then if $rt == 0, then the conditional assignment 373// $rd = $rs is done. 374// 375// So this pseudo class only has one operand, i.e. op 376// 377class Sel<string op>: 378 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 379 CPU16Regs:$rt), 380 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 381 //let isCodeGenOnly=1; 382 let Constraints = "$rd = $rd_"; 383 let usesCustomInserter = 1; 384} 385 386// 387// The next two instruction classes allow for an operand which tests 388// two operands and returns a value in register T8 and 389//then does a conditional branch based on the value of T8 390// 391 392// op2 can be cmpi or slti/sltiu 393// op1 can bteqz or btnez 394// the operands for op2 are a register and a signed constant 395// 396// $op2 $t, $imm ;test register t and branch conditionally 397// $op1 .+4 ;op1 is a conditional branch 398// move $rd, $rs 399// 400// 401class SeliT<string op1, string op2>: 402 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 403 CPU16Regs:$rl, simm16:$imm), 404 !strconcat(op2, 405 !strconcat("\t$rl, $imm\n\t", 406 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 407 let isCodeGenOnly=1; 408 let Constraints = "$rd = $rd_"; 409 let usesCustomInserter = 1; 410} 411 412// 413// op2 can be cmp or slt/sltu 414// op1 can be bteqz or btnez 415// the operands for op2 are two registers 416// op1 is a conditional branch 417// 418// 419// $op2 $rl, $rr ;test registers rl,rr 420// $op1 .+4 ;op2 is a conditional branch 421// move $rd, $rs 422// 423// 424class SelT<string op1, string op2>: 425 MipsPseudo16<(outs CPU16Regs:$rd_), 426 (ins CPU16Regs:$rd, CPU16Regs:$rs, 427 CPU16Regs:$rl, CPU16Regs:$rr), 428 !strconcat(op2, 429 !strconcat("\t$rl, $rr\n\t", 430 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 431 let isCodeGenOnly=1; 432 let Constraints = "$rd = $rd_"; 433 let usesCustomInserter = 1; 434} 435 436// 437// 32 bit constant 438// 439def imm32: Operand<i32>; 440 441def Constant32: 442 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 443 444def LwConstant32: 445 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm), 446 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 447 448 449// 450// Some general instruction class info 451// 452// 453 454class ArithLogic16Defs<bit isCom=0> { 455 bits<5> shamt = 0; 456 bit isCommutable = isCom; 457 bit isReMaterializable = 1; 458 bit neverHasSideEffects = 1; 459} 460 461class branch16 { 462 bit isBranch = 1; 463 bit isTerminator = 1; 464 bit isBarrier = 1; 465} 466 467class cbranch16 { 468 bit isBranch = 1; 469 bit isTerminator = 1; 470} 471 472class MayLoad { 473 bit mayLoad = 1; 474} 475 476class MayStore { 477 bit mayStore = 1; 478} 479// 480 481 482// Format: ADDIU rx, immediate MIPS16e 483// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 484// To add a constant to a 32-bit integer. 485// 486def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 487 488def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 489 ArithLogic16Defs<0> { 490 let AddedComplexity = 5; 491} 492def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 493 ArithLogic16Defs<0> { 494 let isCodeGenOnly = 1; 495} 496 497def AddiuRxRyOffMemX16: 498 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 499 500// 501 502// Format: ADDIU rx, pc, immediate MIPS16e 503// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 504// To add a constant to the program counter. 505// 506def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 507 508// 509// Format: ADDIU sp, immediate MIPS16e 510// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 511// To add a constant to the stack pointer. 512// 513def AddiuSpImm16 514 : FI816_SP_ins<0b011, "addiu", IIAlu> { 515 let Defs = [SP]; 516 let Uses = [SP]; 517 let AddedComplexity = 5; 518} 519 520def AddiuSpImmX16 521 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 522 let Defs = [SP]; 523 let Uses = [SP]; 524} 525 526// 527// Format: ADDU rz, rx, ry MIPS16e 528// Purpose: Add Unsigned Word (3-Operand) 529// To add 32-bit integers. 530// 531 532def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 533 534// 535// Format: AND rx, ry MIPS16e 536// Purpose: AND 537// To do a bitwise logical AND. 538 539def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 540 541 542// 543// Format: BEQZ rx, offset MIPS16e 544// Purpose: Branch on Equal to Zero 545// To test a GPR then do a PC-relative conditional branch. 546// 547def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 548 549 550// 551// Format: BEQZ rx, offset MIPS16e 552// Purpose: Branch on Equal to Zero (Extended) 553// To test a GPR then do a PC-relative conditional branch. 554// 555def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 556 557// Format: B offset MIPS16e 558// Purpose: Unconditional Branch 559// To do an unconditional PC-relative branch. 560// 561def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 562 563// 564// Format: BNEZ rx, offset MIPS16e 565// Purpose: Branch on Not Equal to Zero 566// To test a GPR then do a PC-relative conditional branch. 567// 568def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 569 570// 571// Format: BNEZ rx, offset MIPS16e 572// Purpose: Branch on Not Equal to Zero (Extended) 573// To test a GPR then do a PC-relative conditional branch. 574// 575def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 576 577// 578// Format: BTEQZ offset MIPS16e 579// Purpose: Branch on T Equal to Zero (Extended) 580// To test special register T then do a PC-relative conditional branch. 581// 582def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 583 let Uses = [T8]; 584} 585 586def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 587 588def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 589 cbranch16; 590 591def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 592 593def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 594 595def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 596 597def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 598 cbranch16; 599 600// 601// Format: BTNEZ offset MIPS16e 602// Purpose: Branch on T Not Equal to Zero (Extended) 603// To test special register T then do a PC-relative conditional branch. 604// 605def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 606 let Uses = [T8]; 607} 608 609def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 610 611def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 612 613def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 614 615def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 616 617def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 618 619def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 620 cbranch16; 621 622// 623// Format: CMP rx, ry MIPS16e 624// Purpose: Compare 625// To compare the contents of two GPRs. 626// 627def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> { 628 let Defs = [T8]; 629} 630 631// 632// Format: CMPI rx, immediate MIPS16e 633// Purpose: Compare Immediate 634// To compare a constant with the contents of a GPR. 635// 636def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> { 637 let Defs = [T8]; 638} 639 640// 641// Format: CMPI rx, immediate MIPS16e 642// Purpose: Compare Immediate (Extended) 643// To compare a constant with the contents of a GPR. 644// 645def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> { 646 let Defs = [T8]; 647} 648 649 650// 651// Format: DIV rx, ry MIPS16e 652// Purpose: Divide Word 653// To divide 32-bit signed integers. 654// 655def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 656 let Defs = [HI, LO]; 657} 658 659// 660// Format: DIVU rx, ry MIPS16e 661// Purpose: Divide Unsigned Word 662// To divide 32-bit unsigned integers. 663// 664def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 665 let Defs = [HI, LO]; 666} 667// 668// Format: JAL target MIPS16e 669// Purpose: Jump and Link 670// To execute a procedure call within the current 256 MB-aligned 671// region and preserve the current ISA. 672// 673 674def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 675 let isBranch = 1; 676 let hasDelaySlot = 0; // not true, but we add the nop for now 677 let isTerminator=1; 678 let isBarrier=1; 679 let isCall=1; 680} 681 682// 683// Format: JR ra MIPS16e 684// Purpose: Jump Register Through Register ra 685// To execute a branch to the instruction address in the return 686// address register. 687// 688 689def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 690 let isBranch = 1; 691 let isIndirectBranch = 1; 692 let hasDelaySlot = 1; 693 let isTerminator=1; 694 let isBarrier=1; 695} 696 697def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 698 let isBranch = 1; 699 let isIndirectBranch = 1; 700 let isTerminator=1; 701 let isBarrier=1; 702} 703 704def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 705 let isBranch = 1; 706 let isIndirectBranch = 1; 707 let isTerminator=1; 708 let isBarrier=1; 709} 710// 711// Format: LB ry, offset(rx) MIPS16e 712// Purpose: Load Byte (Extended) 713// To load a byte from memory as a signed value. 714// 715def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 716 let isCodeGenOnly = 1; 717} 718 719// 720// Format: LBU ry, offset(rx) MIPS16e 721// Purpose: Load Byte Unsigned (Extended) 722// To load a byte from memory as a unsigned value. 723// 724def LbuRxRyOffMemX16: 725 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 726 let isCodeGenOnly = 1; 727} 728 729// 730// Format: LH ry, offset(rx) MIPS16e 731// Purpose: Load Halfword signed (Extended) 732// To load a halfword from memory as a signed value. 733// 734def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 735 let isCodeGenOnly = 1; 736} 737 738// 739// Format: LHU ry, offset(rx) MIPS16e 740// Purpose: Load Halfword unsigned (Extended) 741// To load a halfword from memory as an unsigned value. 742// 743def LhuRxRyOffMemX16: 744 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 745 let isCodeGenOnly = 1; 746} 747 748// 749// Format: LI rx, immediate MIPS16e 750// Purpose: Load Immediate 751// To load a constant into a GPR. 752// 753def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 754 755// 756// Format: LI rx, immediate MIPS16e 757// Purpose: Load Immediate (Extended) 758// To load a constant into a GPR. 759// 760def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 761 762// 763// Format: LW ry, offset(rx) MIPS16e 764// Purpose: Load Word (Extended) 765// To load a word from memory as a signed value. 766// 767def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 768 let isCodeGenOnly = 1; 769} 770 771// Format: LW rx, offset(sp) MIPS16e 772// Purpose: Load Word (SP-Relative, Extended) 773// To load an SP-relative word from memory as a signed value. 774// 775def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{ 776 let Uses = [SP]; 777} 778 779// 780// Format: MOVE r32, rz MIPS16e 781// Purpose: Move 782// To move the contents of a GPR to a GPR. 783// 784def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 785 786// 787// Format: MOVE ry, r32 MIPS16e 788//Purpose: Move 789// To move the contents of a GPR to a GPR. 790// 791def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 792 793// 794// Format: MFHI rx MIPS16e 795// Purpose: Move From HI Register 796// To copy the special purpose HI register to a GPR. 797// 798def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 799 let Uses = [HI]; 800 let neverHasSideEffects = 1; 801} 802 803// 804// Format: MFLO rx MIPS16e 805// Purpose: Move From LO Register 806// To copy the special purpose LO register to a GPR. 807// 808def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 809 let Uses = [LO]; 810 let neverHasSideEffects = 1; 811} 812 813// 814// Pseudo Instruction for mult 815// 816def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 817 let isCommutable = 1; 818 let neverHasSideEffects = 1; 819 let Defs = [HI, LO]; 820} 821 822def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 823 let isCommutable = 1; 824 let neverHasSideEffects = 1; 825 let Defs = [HI, LO]; 826} 827 828// 829// Format: MULT rx, ry MIPS16e 830// Purpose: Multiply Word 831// To multiply 32-bit signed integers. 832// 833def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 834 let isCommutable = 1; 835 let neverHasSideEffects = 1; 836 let Defs = [HI, LO]; 837} 838 839// 840// Format: MULTU rx, ry MIPS16e 841// Purpose: Multiply Unsigned Word 842// To multiply 32-bit unsigned integers. 843// 844def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 845 let isCommutable = 1; 846 let neverHasSideEffects = 1; 847 let Defs = [HI, LO]; 848} 849 850// 851// Format: NEG rx, ry MIPS16e 852// Purpose: Negate 853// To negate an integer value. 854// 855def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 856 857// 858// Format: NOT rx, ry MIPS16e 859// Purpose: Not 860// To complement an integer value 861// 862def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 863 864// 865// Format: OR rx, ry MIPS16e 866// Purpose: Or 867// To do a bitwise logical OR. 868// 869def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 870 871// 872// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 873// (All args are optional) MIPS16e 874// Purpose: Restore Registers and Deallocate Stack Frame 875// To deallocate a stack frame before exit from a subroutine, 876// restoring return address and static registers, and adjusting 877// stack 878// 879 880// fixed form for restoring RA and the frame 881// for direct object emitter, encoding needs to be adjusted for the 882// frame size 883// 884let ra=1, s=0,s0=1,s1=1 in 885def RestoreRaF16: 886 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 887 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad { 888 let isCodeGenOnly = 1; 889 let Defs = [S0, S1, S2, RA, SP]; 890 let Uses = [SP]; 891} 892 893// Use Restore to increment SP since SP is not a Mip 16 register, this 894// is an easy way to do that which does not require a register. 895// 896let ra=0, s=0,s0=0,s1=0 in 897def RestoreIncSpF16: 898 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 899 "restore\t$frame_size", [], IILoad >, MayLoad { 900 let isCodeGenOnly = 1; 901 let Defs = [SP]; 902 let Uses = [SP]; 903} 904 905// 906// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 907// MIPS16e 908// Purpose: Save Registers and Set Up Stack Frame 909// To set up a stack frame on entry to a subroutine, 910// saving return address and static registers, and adjusting stack 911// 912let ra=1, s=1,s0=1,s1=1 in 913def SaveRaF16: 914 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 915 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore { 916 let isCodeGenOnly = 1; 917 let Uses = [RA, SP, S0, S1, S2]; 918 let Defs = [SP]; 919} 920 921// 922// Use Save to decrement the SP by a constant since SP is not 923// a Mips16 register. 924// 925let ra=0, s=0,s0=0,s1=0 in 926def SaveDecSpF16: 927 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 928 "save\t$frame_size", [], IIStore >, MayStore { 929 let isCodeGenOnly = 1; 930 let Uses = [SP]; 931 let Defs = [SP]; 932} 933// 934// Format: SB ry, offset(rx) MIPS16e 935// Purpose: Store Byte (Extended) 936// To store a byte to memory. 937// 938def SbRxRyOffMemX16: 939 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 940 941// 942// The Sel(T) instructions are pseudos 943// T means that they use T8 implicitly. 944// 945// 946// Format: SelBeqZ rd, rs, rt 947// Purpose: if rt==0, do nothing 948// else rs = rt 949// 950def SelBeqZ: Sel<"beqz">; 951 952// 953// Format: SelTBteqZCmp rd, rs, rl, rr 954// Purpose: b = Cmp rl, rr. 955// If b==0 then do nothing. 956// if b!=0 then rd = rs 957// 958def SelTBteqZCmp: SelT<"bteqz", "cmp">; 959 960// 961// Format: SelTBteqZCmpi rd, rs, rl, rr 962// Purpose: b = Cmpi rl, imm. 963// If b==0 then do nothing. 964// if b!=0 then rd = rs 965// 966def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 967 968// 969// Format: SelTBteqZSlt rd, rs, rl, rr 970// Purpose: b = Slt rl, rr. 971// If b==0 then do nothing. 972// if b!=0 then rd = rs 973// 974def SelTBteqZSlt: SelT<"bteqz", "slt">; 975 976// 977// Format: SelTBteqZSlti rd, rs, rl, rr 978// Purpose: b = Slti rl, imm. 979// If b==0 then do nothing. 980// if b!=0 then rd = rs 981// 982def SelTBteqZSlti: SeliT<"bteqz", "slti">; 983 984// 985// Format: SelTBteqZSltu rd, rs, rl, rr 986// Purpose: b = Sltu rl, rr. 987// If b==0 then do nothing. 988// if b!=0 then rd = rs 989// 990def SelTBteqZSltu: SelT<"bteqz", "sltu">; 991 992// 993// Format: SelTBteqZSltiu rd, rs, rl, rr 994// Purpose: b = Sltiu rl, imm. 995// If b==0 then do nothing. 996// if b!=0 then rd = rs 997// 998def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 999 1000// 1001// Format: SelBnez rd, rs, rt 1002// Purpose: if rt!=0, do nothing 1003// else rs = rt 1004// 1005def SelBneZ: Sel<"bnez">; 1006 1007// 1008// Format: SelTBtneZCmp rd, rs, rl, rr 1009// Purpose: b = Cmp rl, rr. 1010// If b!=0 then do nothing. 1011// if b0=0 then rd = rs 1012// 1013def SelTBtneZCmp: SelT<"btnez", "cmp">; 1014 1015// 1016// Format: SelTBtnezCmpi rd, rs, rl, rr 1017// Purpose: b = Cmpi rl, imm. 1018// If b!=0 then do nothing. 1019// if b==0 then rd = rs 1020// 1021def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1022 1023// 1024// Format: SelTBtneZSlt rd, rs, rl, rr 1025// Purpose: b = Slt rl, rr. 1026// If b!=0 then do nothing. 1027// if b==0 then rd = rs 1028// 1029def SelTBtneZSlt: SelT<"btnez", "slt">; 1030 1031// 1032// Format: SelTBtneZSlti rd, rs, rl, rr 1033// Purpose: b = Slti rl, imm. 1034// If b!=0 then do nothing. 1035// if b==0 then rd = rs 1036// 1037def SelTBtneZSlti: SeliT<"btnez", "slti">; 1038 1039// 1040// Format: SelTBtneZSltu rd, rs, rl, rr 1041// Purpose: b = Sltu rl, rr. 1042// If b!=0 then do nothing. 1043// if b==0 then rd = rs 1044// 1045def SelTBtneZSltu: SelT<"btnez", "sltu">; 1046 1047// 1048// Format: SelTBtneZSltiu rd, rs, rl, rr 1049// Purpose: b = Slti rl, imm. 1050// If b!=0 then do nothing. 1051// if b==0 then rd = rs 1052// 1053def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1054// 1055// 1056// Format: SH ry, offset(rx) MIPS16e 1057// Purpose: Store Halfword (Extended) 1058// To store a halfword to memory. 1059// 1060def ShRxRyOffMemX16: 1061 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1062 1063// 1064// Format: SLL rx, ry, sa MIPS16e 1065// Purpose: Shift Word Left Logical (Extended) 1066// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 1067// 1068def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1069 1070// 1071// Format: SLLV ry, rx MIPS16e 1072// Purpose: Shift Word Left Logical Variable 1073// To execute a left-shift of a word by a variable number of bits. 1074// 1075def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1076 1077// Format: SLTI rx, immediate MIPS16e 1078// Purpose: Set on Less Than Immediate 1079// To record the result of a less-than comparison with a constant. 1080// 1081// 1082def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1083 let Defs = [T8]; 1084} 1085 1086// 1087// Format: SLTI rx, immediate MIPS16e 1088// Purpose: Set on Less Than Immediate (Extended) 1089// To record the result of a less-than comparison with a constant. 1090// 1091// 1092def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1093 let Defs = [T8]; 1094} 1095 1096def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1097 1098// Format: SLTIU rx, immediate MIPS16e 1099// Purpose: Set on Less Than Immediate Unsigned 1100// To record the result of a less-than comparison with a constant. 1101// 1102// 1103def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1104 let Defs = [T8]; 1105} 1106 1107// 1108// Format: SLTI rx, immediate MIPS16e 1109// Purpose: Set on Less Than Immediate Unsigned (Extended) 1110// To record the result of a less-than comparison with a constant. 1111// 1112// 1113def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1114 let Defs = [T8]; 1115} 1116// 1117// Format: SLTIU rx, immediate MIPS16e 1118// Purpose: Set on Less Than Immediate Unsigned (Extended) 1119// To record the result of a less-than comparison with a constant. 1120// 1121def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1122 1123// 1124// Format: SLT rx, ry MIPS16e 1125// Purpose: Set on Less Than 1126// To record the result of a less-than comparison. 1127// 1128def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{ 1129 let Defs = [T8]; 1130} 1131 1132def SltCCRxRy16: FCCRR16_ins<"slt">; 1133 1134// Format: SLTU rx, ry MIPS16e 1135// Purpose: Set on Less Than Unsigned 1136// To record the result of an unsigned less-than comparison. 1137// 1138def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{ 1139 let Defs = [T8]; 1140} 1141 1142def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1143 let isCodeGenOnly=1; 1144 let Defs = [T8]; 1145} 1146 1147 1148def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1149// 1150// Format: SRAV ry, rx MIPS16e 1151// Purpose: Shift Word Right Arithmetic Variable 1152// To execute an arithmetic right-shift of a word by a variable 1153// number of bits. 1154// 1155def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1156 1157 1158// 1159// Format: SRA rx, ry, sa MIPS16e 1160// Purpose: Shift Word Right Arithmetic (Extended) 1161// To execute an arithmetic right-shift of a word by a fixed 1162// number of bits—1 to 8 bits. 1163// 1164def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1165 1166 1167// 1168// Format: SRLV ry, rx MIPS16e 1169// Purpose: Shift Word Right Logical Variable 1170// To execute a logical right-shift of a word by a variable 1171// number of bits. 1172// 1173def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1174 1175 1176// 1177// Format: SRL rx, ry, sa MIPS16e 1178// Purpose: Shift Word Right Logical (Extended) 1179// To execute a logical right-shift of a word by a fixed 1180// number of bits—1 to 31 bits. 1181// 1182def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1183 1184// 1185// Format: SUBU rz, rx, ry MIPS16e 1186// Purpose: Subtract Unsigned Word 1187// To subtract 32-bit integers 1188// 1189def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1190 1191// 1192// Format: SW ry, offset(rx) MIPS16e 1193// Purpose: Store Word (Extended) 1194// To store a word to memory. 1195// 1196def SwRxRyOffMemX16: 1197 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1198 1199// 1200// Format: SW rx, offset(sp) MIPS16e 1201// Purpose: Store Word rx (SP-Relative) 1202// To store an SP-relative word to memory. 1203// 1204def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins 1205 <0b11010, "sw", IIStore>, MayStore; 1206 1207// 1208// 1209// Format: XOR rx, ry MIPS16e 1210// Purpose: Xor 1211// To do a bitwise logical XOR. 1212// 1213def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1214 1215class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1216 let Predicates = [InMips16Mode]; 1217} 1218 1219// Unary Arith/Logic 1220// 1221class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1222 Mips16Pat<(OpNode CPU16Regs:$r), 1223 (I CPU16Regs:$r)>; 1224 1225def: ArithLogicU_pat<not, NotRxRy16>; 1226def: ArithLogicU_pat<ineg, NegRxRy16>; 1227 1228class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1229 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1230 (I CPU16Regs:$l, CPU16Regs:$r)>; 1231 1232def: ArithLogic16_pat<add, AdduRxRyRz16>; 1233def: ArithLogic16_pat<and, AndRxRxRy16>; 1234def: ArithLogic16_pat<mul, MultRxRyRz16>; 1235def: ArithLogic16_pat<or, OrRxRxRy16>; 1236def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1237def: ArithLogic16_pat<xor, XorRxRxRy16>; 1238 1239// Arithmetic and logical instructions with 2 register operands. 1240 1241class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1242 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1243 (I CPU16Regs:$in, imm_type:$imm)>; 1244 1245def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1246def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1247def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1248def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1249def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1250 1251class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1252 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1253 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1254 1255def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1256def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1257def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1258 1259class LoadM16_pat<PatFrag OpNode, Instruction I> : 1260 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1261 1262def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1263def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1264def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1265def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1266def: LoadM16_pat<load, LwRxRyOffMemX16>; 1267 1268class StoreM16_pat<PatFrag OpNode, Instruction I> : 1269 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1270 (I CPU16Regs:$r, addr16:$addr)>; 1271 1272def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1273def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1274def: StoreM16_pat<store, SwRxRyOffMemX16>; 1275 1276// Unconditional branch 1277class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1278 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1279 let Predicates = [InMips16Mode]; 1280 } 1281 1282def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1283 (Jal16 tglobaladdr:$dst)>; 1284 1285def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1286 (Jal16 texternalsym:$dst)>; 1287 1288// Indirect branch 1289def: Mips16Pat< 1290 (brind CPU16Regs:$rs), 1291 (JrcRx16 CPU16Regs:$rs)>; 1292 1293// Jump and Link (Call) 1294let isCall=1, hasDelaySlot=0 in 1295def JumpLinkReg16: 1296 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1297 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1298 1299// Mips16 pseudos 1300let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1301 hasExtraSrcRegAllocReq = 1 in 1302def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1303 1304 1305// setcc patterns 1306 1307class SetCC_R16<PatFrag cond_op, Instruction I>: 1308 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1309 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1310 1311class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1312 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1313 (I CPU16Regs:$rx, imm_type:$imm16)>; 1314 1315 1316def: Mips16Pat<(i32 addr16:$addr), 1317 (AddiuRxRyOffMemX16 addr16:$addr)>; 1318 1319 1320// Large (>16 bit) immediate loads 1321def : Mips16Pat<(i32 imm:$imm), 1322 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1323 (LiRxImmX16 (LO16 imm:$imm)))>; 1324 1325// Carry MipsPatterns 1326def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1327 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1328def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1329 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1330def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1331 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1332 1333// 1334// Some branch conditional patterns are not generated by llvm at this time. 1335// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1336// comparison they are used and for unsigned a different pattern is used. 1337// I am pushing upstream from the full mips16 port and it seemed that I needed 1338// these earlier and the mips32 port has these but now I cannot create test 1339// cases that use these patterns. While I sort this all out I will leave these 1340// extra patterns commented out and if I can be sure they are really not used, 1341// I will delete the code. I don't want to check the code in uncommented without 1342// a valid test case. In some cases, the compiler is generating patterns with 1343// setcc instead and earlier I had implemented setcc first so may have masked 1344// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1345// figure out how to enable the brcond patterns or else possibly new 1346// combinations of of brcond and setcc. 1347// 1348// 1349// bcond-seteq 1350// 1351def: Mips16Pat 1352 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1353 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1354 >; 1355 1356 1357def: Mips16Pat 1358 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1359 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1360 >; 1361 1362def: Mips16Pat 1363 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1364 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1365 >; 1366 1367// 1368// bcond-setgt (do we need to have this pair of setlt, setgt??) 1369// 1370def: Mips16Pat 1371 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1372 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1373 >; 1374 1375// 1376// bcond-setge 1377// 1378def: Mips16Pat 1379 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1380 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1381 >; 1382 1383// 1384// never called because compiler transforms a >= k to a > (k-1) 1385def: Mips16Pat 1386 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1387 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1388 >; 1389 1390// 1391// bcond-setlt 1392// 1393def: Mips16Pat 1394 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1395 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1396 >; 1397 1398def: Mips16Pat 1399 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1400 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1401 >; 1402 1403// 1404// bcond-setle 1405// 1406def: Mips16Pat 1407 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1408 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1409 >; 1410 1411// 1412// bcond-setne 1413// 1414def: Mips16Pat 1415 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1416 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1417 >; 1418 1419def: Mips16Pat 1420 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1421 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1422 >; 1423 1424def: Mips16Pat 1425 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1426 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1427 >; 1428 1429// 1430// This needs to be there but I forget which code will generate it 1431// 1432def: Mips16Pat 1433 <(brcond CPU16Regs:$rx, bb:$targ16), 1434 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1435 >; 1436 1437// 1438 1439// 1440// bcond-setugt 1441// 1442//def: Mips16Pat 1443// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1444// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1445// >; 1446 1447// 1448// bcond-setuge 1449// 1450//def: Mips16Pat 1451// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1452// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1453// >; 1454 1455 1456// 1457// bcond-setult 1458// 1459//def: Mips16Pat 1460// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1461// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1462// >; 1463 1464def: UncondBranch16_pat<br, BimmX16>; 1465 1466// Small immediates 1467def: Mips16Pat<(i32 immSExt16:$in), 1468 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1469 1470def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1471 1472// 1473// MipsDivRem 1474// 1475def: Mips16Pat 1476 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), 1477 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1478 1479// 1480// MipsDivRemU 1481// 1482def: Mips16Pat 1483 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry), 1484 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1485 1486// signed a,b 1487// x = (a>=b)?x:y 1488// 1489// if !(a < b) x = y 1490// 1491def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1492 CPU16Regs:$x, CPU16Regs:$y), 1493 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1494 CPU16Regs:$a, CPU16Regs:$b)>; 1495 1496// signed a,b 1497// x = (a>b)?x:y 1498// 1499// if (b < a) x = y 1500// 1501def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1502 CPU16Regs:$x, CPU16Regs:$y), 1503 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1504 CPU16Regs:$b, CPU16Regs:$a)>; 1505 1506// unsigned a,b 1507// x = (a>=b)?x:y 1508// 1509// if !(a < b) x = y; 1510// 1511def : Mips16Pat< 1512 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1513 CPU16Regs:$x, CPU16Regs:$y), 1514 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1515 CPU16Regs:$a, CPU16Regs:$b)>; 1516 1517// unsigned a,b 1518// x = (a>b)?x:y 1519// 1520// if (b < a) x = y 1521// 1522def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1523 CPU16Regs:$x, CPU16Regs:$y), 1524 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1525 CPU16Regs:$b, CPU16Regs:$a)>; 1526 1527// signed 1528// x = (a >= k)?x:y 1529// due to an llvm optimization, i don't think that this will ever 1530// be used. This is transformed into x = (a > k-1)?x:y 1531// 1532// 1533 1534//def : Mips16Pat< 1535// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1536// CPU16Regs:$T, CPU16Regs:$F), 1537// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1538// CPU16Regs:$lhs, immSExt16:$rhs)>; 1539 1540//def : Mips16Pat< 1541// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1542// CPU16Regs:$T, CPU16Regs:$F), 1543// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1544// CPU16Regs:$lhs, immSExt16:$rhs)>; 1545 1546// signed 1547// x = (a < k)?x:y 1548// 1549// if !(a < k) x = y; 1550// 1551def : Mips16Pat< 1552 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1553 CPU16Regs:$x, CPU16Regs:$y), 1554 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1555 CPU16Regs:$a, immSExt16:$b)>; 1556 1557 1558// 1559// 1560// signed 1561// x = (a <= b)? x : y 1562// 1563// if (b < a) x = y 1564// 1565def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1566 CPU16Regs:$x, CPU16Regs:$y), 1567 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1568 CPU16Regs:$b, CPU16Regs:$a)>; 1569 1570// 1571// unnsigned 1572// x = (a <= b)? x : y 1573// 1574// if (b < a) x = y 1575// 1576def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1577 CPU16Regs:$x, CPU16Regs:$y), 1578 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1579 CPU16Regs:$b, CPU16Regs:$a)>; 1580 1581// 1582// signed/unsigned 1583// x = (a == b)? x : y 1584// 1585// if (a != b) x = y 1586// 1587def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1588 CPU16Regs:$x, CPU16Regs:$y), 1589 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1590 CPU16Regs:$b, CPU16Regs:$a)>; 1591 1592// 1593// signed/unsigned 1594// x = (a == 0)? x : y 1595// 1596// if (a != 0) x = y 1597// 1598def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1599 CPU16Regs:$x, CPU16Regs:$y), 1600 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1601 CPU16Regs:$a)>; 1602 1603 1604// 1605// signed/unsigned 1606// x = (a == k)? x : y 1607// 1608// if (a != k) x = y 1609// 1610def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1611 CPU16Regs:$x, CPU16Regs:$y), 1612 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1613 CPU16Regs:$a, immZExt16:$k)>; 1614 1615 1616// 1617// signed/unsigned 1618// x = (a != b)? x : y 1619// 1620// if (a == b) x = y 1621// 1622// 1623def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1624 CPU16Regs:$x, CPU16Regs:$y), 1625 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1626 CPU16Regs:$b, CPU16Regs:$a)>; 1627 1628// 1629// signed/unsigned 1630// x = (a != 0)? x : y 1631// 1632// if (a == 0) x = y 1633// 1634def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1635 CPU16Regs:$x, CPU16Regs:$y), 1636 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1637 CPU16Regs:$a)>; 1638 1639// signed/unsigned 1640// x = (a)? x : y 1641// 1642// if (!a) x = y 1643// 1644def : Mips16Pat<(select CPU16Regs:$a, 1645 CPU16Regs:$x, CPU16Regs:$y), 1646 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1647 CPU16Regs:$a)>; 1648 1649 1650// 1651// signed/unsigned 1652// x = (a != k)? x : y 1653// 1654// if (a == k) x = y 1655// 1656def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1657 CPU16Regs:$x, CPU16Regs:$y), 1658 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1659 CPU16Regs:$a, immZExt16:$k)>; 1660 1661// 1662// When writing C code to test setxx these patterns, 1663// some will be transformed into 1664// other things. So we test using C code but using -O3 and -O0 1665// 1666// seteq 1667// 1668def : Mips16Pat 1669 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1670 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1671 1672def : Mips16Pat 1673 <(seteq CPU16Regs:$lhs, 0), 1674 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1675 1676 1677// 1678// setge 1679// 1680 1681def: Mips16Pat 1682 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1683 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1684 (LiRxImmX16 1))>; 1685 1686// 1687// For constants, llvm transforms this to: 1688// x > (k -1) and then reverses the operands to use setlt. So this pattern 1689// is not used now by the compiler. (Presumably checking that k-1 does not 1690// overflow). The compiler never uses this at a the current time, due to 1691// other optimizations. 1692// 1693//def: Mips16Pat 1694// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1695// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1696// (LiRxImmX16 1))>; 1697 1698// This catches the x >= -32768 case by transforming it to x > -32769 1699// 1700def: Mips16Pat 1701 <(setgt CPU16Regs:$lhs, -32769), 1702 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1703 (LiRxImmX16 1))>; 1704 1705// 1706// setgt 1707// 1708// 1709 1710def: Mips16Pat 1711 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1712 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1713 1714// 1715// setle 1716// 1717def: Mips16Pat 1718 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1719 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1720 1721// 1722// setlt 1723// 1724def: SetCC_R16<setlt, SltCCRxRy16>; 1725 1726def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1727 1728// 1729// setne 1730// 1731def : Mips16Pat 1732 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1733 (SltuCCRxRy16 (LiRxImmX16 0), 1734 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1735 1736 1737// 1738// setuge 1739// 1740def: Mips16Pat 1741 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1742 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1743 (LiRxImmX16 1))>; 1744 1745// this pattern will never be used because the compiler will transform 1746// x >= k to x > (k - 1) and then use SLT 1747// 1748//def: Mips16Pat 1749// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1750// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1751// (LiRxImmX16 1))>; 1752 1753// 1754// setugt 1755// 1756def: Mips16Pat 1757 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1758 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1759 1760// 1761// setule 1762// 1763def: Mips16Pat 1764 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1765 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1766 1767// 1768// setult 1769// 1770def: SetCC_R16<setult, SltuCCRxRy16>; 1771 1772def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1773 1774def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1775 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1776 1777// hi/lo relocs 1778 1779def : Mips16Pat<(MipsHi tglobaladdr:$in), 1780 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1781def : Mips16Pat<(MipsHi tjumptable:$in), 1782 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1783def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1784 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1785 1786// wrapper_pic 1787class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1788 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1789 (ADDiuOp RC:$gp, node:$in)>; 1790 1791 1792def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1793def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1794 1795def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1796 (LbuRxRyOffMemX16 addr16:$src)>; 1797def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1798 (LhuRxRyOffMemX16 addr16:$src)>; 1799