Mips16InstrInfo.td revision 1ef90831229a586c2421be4ae9f1e990312a4f95
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// 36// I8 instruction format 37// 38 39class FI816_ins_base<bits<3> _func, string asmstr, 40 string asmstr2, InstrItinClass itin>: 41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 42 [], itin>; 43 44 45class FI816_SP_ins<bits<3> _func, string asmstr, 46 InstrItinClass itin>: 47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 48 49// 50// RI instruction format 51// 52 53 54class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 55 InstrItinClass itin>: 56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 57 !strconcat(asmstr, asmstr2), [], itin>; 58 59class FRI16_ins<bits<5> op, string asmstr, 60 InstrItinClass itin>: 61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 62 63class FRI16_TCP_ins<bits<5> _op, string asmstr, 64 InstrItinClass itin>: 65 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size), 66 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>; 67 68class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 69 InstrItinClass itin>: 70 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 71 !strconcat(asmstr, asmstr2), [], itin>; 72 73class FRI16R_ins<bits<5> op, string asmstr, 74 InstrItinClass itin>: 75 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 76 77class F2RI16_ins<bits<5> _op, string asmstr, 78 InstrItinClass itin>: 79 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 80 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 81 let Constraints = "$rx_ = $rx"; 82} 83 84class FRI16_B_ins<bits<5> _op, string asmstr, 85 InstrItinClass itin>: 86 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 87 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 88// 89// Compare a register and immediate and place result in CC 90// Implicit use of T8 91// 92// EXT-CCRR Instruction format 93// 94class FEXT_CCRXI16_ins<string asmstr>: 95 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 96 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 97 let isCodeGenOnly=1; 98 let usesCustomInserter = 1; 99} 100 101// JAL and JALX instruction format 102// 103class FJAL16_ins<bits<1> _X, string asmstr, 104 InstrItinClass itin>: 105 FJAL16<_X, (outs), (ins simm20:$imm), 106 !strconcat(asmstr, "\t$imm\n\tnop"),[], 107 itin> { 108 let isCodeGenOnly=1; 109} 110// 111// EXT-I instruction format 112// 113class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 114 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 115 !strconcat(asmstr, "\t$imm16"),[], itin>; 116 117// 118// EXT-I8 instruction format 119// 120 121class FEXT_I816_ins_base<bits<3> _func, string asmstr, 122 string asmstr2, InstrItinClass itin>: 123 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 124 [], itin>; 125 126class FEXT_I816_ins<bits<3> _func, string asmstr, 127 InstrItinClass itin>: 128 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 129 130class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 131 InstrItinClass itin>: 132 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 133 134// 135// Assembler formats in alphabetical order. 136// Natural and pseudos are mixed together. 137// 138// Compare two registers and place result in CC 139// Implicit use of T8 140// 141// CC-RR Instruction format 142// 143class FCCRR16_ins<string asmstr> : 144 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 145 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 146 let isCodeGenOnly=1; 147 let usesCustomInserter = 1; 148} 149 150// 151// EXT-RI instruction format 152// 153 154class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 155 InstrItinClass itin>: 156 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 157 !strconcat(asmstr, asmstr2), [], itin>; 158 159class FEXT_RI16_ins<bits<5> _op, string asmstr, 160 InstrItinClass itin>: 161 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 162 163class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 164 InstrItinClass itin>: 165 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 166 !strconcat(asmstr, asmstr2), [], itin>; 167 168class FEXT_RI16R_ins<bits<5> _op, string asmstr, 169 InstrItinClass itin>: 170 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 171 172class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 173 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 174 175class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 176 InstrItinClass itin>: 177 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 178 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 179 180class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr, 181 InstrItinClass itin>: 182 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size), 183 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 184 185class FEXT_2RI16_ins<bits<5> _op, string asmstr, 186 InstrItinClass itin>: 187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 188 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 189 let Constraints = "$rx_ = $rx"; 190} 191 192 193// this has an explicit sp argument that we ignore to work around a problem 194// in the compiler 195class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 196 InstrItinClass itin>: 197 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 198 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 199 200class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr, 201 InstrItinClass itin>: 202 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm), 203 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 204 205// 206// EXT-RRI instruction format 207// 208 209class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 210 InstrItinClass itin>: 211 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 212 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 213 214class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 215 InstrItinClass itin>: 216 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 218 219// 220// 221// EXT-RRI-A instruction format 222// 223 224class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 225 InstrItinClass itin>: 226 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 227 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 228 229// 230// EXT-SHIFT instruction format 231// 232class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 233 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa), 234 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 235 236// 237// EXT-T8I8 238// 239class FEXT_T8I816_ins<string asmstr, string asmstr2>: 240 MipsPseudo16<(outs), 241 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 242 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 243 !strconcat(asmstr, "\t$imm"))),[]> { 244 let isCodeGenOnly=1; 245 let usesCustomInserter = 1; 246} 247 248// 249// EXT-T8I8I 250// 251class FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 252 MipsPseudo16<(outs), 253 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 254 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 255 !strconcat(asmstr, "\t$targ"))), []> { 256 let isCodeGenOnly=1; 257 let usesCustomInserter = 1; 258} 259// 260 261 262// 263// I8_MOVR32 instruction format (used only by the MOVR32 instructio 264// 265class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 266 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32), 267 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 268 269// 270// I8_MOV32R instruction format (used only by MOV32R instruction) 271// 272 273class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 274 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz), 275 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 276 277// 278// This are pseudo formats for multiply 279// This first one can be changed to non pseudo now. 280// 281// MULT 282// 283class FMULT16_ins<string asmstr, InstrItinClass itin> : 284 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 285 !strconcat(asmstr, "\t$rx, $ry"), []>; 286 287// 288// MULT-LO 289// 290class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 291 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 292 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 293 let isCodeGenOnly=1; 294} 295 296// 297// RR-type instruction format 298// 299 300class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 301 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 302 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 303} 304 305class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> : 306 FRRBreak16<(outs), (ins), asmstr, [], itin> { 307 let Code=0; 308} 309 310class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : 311 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 312 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 313} 314 315class FRRTR16_ins<string asmstr> : 316 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 317 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 318 319// 320// maybe refactor but need a $zero as a dummy first parameter 321// 322class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 323 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 324 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 325 326class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 327 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 328 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 329 330 331class FRR16_M_ins<bits<5> f, string asmstr, 332 InstrItinClass itin> : 333 FRR16<f, (outs CPU16Regs:$rx), (ins), 334 !strconcat(asmstr, "\t$rx"), [], itin>; 335 336class FRxRxRy16_ins<bits<5> f, string asmstr, 337 InstrItinClass itin> : 338 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 339 !strconcat(asmstr, "\t$rz, $ry"), 340 [], itin> { 341 let Constraints = "$rx = $rz"; 342} 343 344let rx=0 in 345class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 346 string asmstr, InstrItinClass itin>: 347 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 348 [], itin> ; 349 350 351class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 352 string asmstr, InstrItinClass itin>: 353 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 354 !strconcat(asmstr, "\t $rx"), [], itin> ; 355 356class FRR_SF16_ins 357 <bits<5> _funct, bits<3> _subfunc, 358 string asmstr, InstrItinClass itin>: 359 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_), 360 !strconcat(asmstr, "\t $rx"), 361 [], itin> { 362 let Constraints = "$rx_ = $rx"; 363 } 364// 365// RRR-type instruction format 366// 367 368class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 369 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 370 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 371 372// 373// These Sel patterns support the generation of conditional move 374// pseudo instructions. 375// 376// The nomenclature uses the components making up the pseudo and may 377// be a bit counter intuitive when compared with the end result we seek. 378// For example using a bqez in the example directly below results in the 379// conditional move being done if the tested register is not zero. 380// I considered in easier to check by keeping the pseudo consistent with 381// it's components but it could have been done differently. 382// 383// The simplest case is when can test and operand directly and do the 384// conditional move based on a simple mips16 conditional 385// branch instruction. 386// for example: 387// if $op == beqz or bnez: 388// 389// $op1 $rt, .+4 390// move $rd, $rs 391// 392// if $op == beqz, then if $rt != 0, then the conditional assignment 393// $rd = $rs is done. 394 395// if $op == bnez, then if $rt == 0, then the conditional assignment 396// $rd = $rs is done. 397// 398// So this pseudo class only has one operand, i.e. op 399// 400class Sel<string op>: 401 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 402 CPU16Regs:$rt), 403 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 404 //let isCodeGenOnly=1; 405 let Constraints = "$rd = $rd_"; 406 let usesCustomInserter = 1; 407} 408 409// 410// The next two instruction classes allow for an operand which tests 411// two operands and returns a value in register T8 and 412//then does a conditional branch based on the value of T8 413// 414 415// op2 can be cmpi or slti/sltiu 416// op1 can bteqz or btnez 417// the operands for op2 are a register and a signed constant 418// 419// $op2 $t, $imm ;test register t and branch conditionally 420// $op1 .+4 ;op1 is a conditional branch 421// move $rd, $rs 422// 423// 424class SeliT<string op1, string op2>: 425 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 426 CPU16Regs:$rl, simm16:$imm), 427 !strconcat(op2, 428 !strconcat("\t$rl, $imm\n\t", 429 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 430 let isCodeGenOnly=1; 431 let Constraints = "$rd = $rd_"; 432 let usesCustomInserter = 1; 433} 434 435// 436// op2 can be cmp or slt/sltu 437// op1 can be bteqz or btnez 438// the operands for op2 are two registers 439// op1 is a conditional branch 440// 441// 442// $op2 $rl, $rr ;test registers rl,rr 443// $op1 .+4 ;op2 is a conditional branch 444// move $rd, $rs 445// 446// 447class SelT<string op1, string op2>: 448 MipsPseudo16<(outs CPU16Regs:$rd_), 449 (ins CPU16Regs:$rd, CPU16Regs:$rs, 450 CPU16Regs:$rl, CPU16Regs:$rr), 451 !strconcat(op2, 452 !strconcat("\t$rl, $rr\n\t", 453 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 454 let isCodeGenOnly=1; 455 let Constraints = "$rd = $rd_"; 456 let usesCustomInserter = 1; 457} 458 459// 460// 32 bit constant 461// 462def imm32: Operand<i32>; 463 464def Constant32: 465 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 466 467def LwConstant32: 468 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid), 469 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 470 471 472// 473// Some general instruction class info 474// 475// 476 477class ArithLogic16Defs<bit isCom=0> { 478 bits<5> shamt = 0; 479 bit isCommutable = isCom; 480 bit isReMaterializable = 1; 481 bit neverHasSideEffects = 1; 482} 483 484class branch16 { 485 bit isBranch = 1; 486 bit isTerminator = 1; 487 bit isBarrier = 1; 488} 489 490class cbranch16 { 491 bit isBranch = 1; 492 bit isTerminator = 1; 493} 494 495class MayLoad { 496 bit mayLoad = 1; 497} 498 499class MayStore { 500 bit mayStore = 1; 501} 502// 503 504 505// Format: ADDIU rx, immediate MIPS16e 506// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 507// To add a constant to a 32-bit integer. 508// 509def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 510 511def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 512 ArithLogic16Defs<0> { 513 let AddedComplexity = 5; 514} 515def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 516 ArithLogic16Defs<0> { 517 let isCodeGenOnly = 1; 518} 519 520def AddiuRxRyOffMemX16: 521 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 522 523// 524 525// Format: ADDIU rx, pc, immediate MIPS16e 526// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 527// To add a constant to the program counter. 528// 529def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 530 531// 532// Format: ADDIU sp, immediate MIPS16e 533// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 534// To add a constant to the stack pointer. 535// 536def AddiuSpImm16 537 : FI816_SP_ins<0b011, "addiu", IIAlu> { 538 let Defs = [SP]; 539 let Uses = [SP]; 540 let AddedComplexity = 5; 541} 542 543def AddiuSpImmX16 544 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 545 let Defs = [SP]; 546 let Uses = [SP]; 547} 548 549// 550// Format: ADDU rz, rx, ry MIPS16e 551// Purpose: Add Unsigned Word (3-Operand) 552// To add 32-bit integers. 553// 554 555def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 556 557// 558// Format: AND rx, ry MIPS16e 559// Purpose: AND 560// To do a bitwise logical AND. 561 562def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 563 564 565// 566// Format: BEQZ rx, offset MIPS16e 567// Purpose: Branch on Equal to Zero 568// To test a GPR then do a PC-relative conditional branch. 569// 570def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 571 572 573// 574// Format: BEQZ rx, offset MIPS16e 575// Purpose: Branch on Equal to Zero (Extended) 576// To test a GPR then do a PC-relative conditional branch. 577// 578def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 579 580// Format: B offset MIPS16e 581// Purpose: Unconditional Branch 582// To do an unconditional PC-relative branch. 583// 584def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 585 586// 587// Format: BNEZ rx, offset MIPS16e 588// Purpose: Branch on Not Equal to Zero 589// To test a GPR then do a PC-relative conditional branch. 590// 591def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 592 593// 594// Format: BNEZ rx, offset MIPS16e 595// Purpose: Branch on Not Equal to Zero (Extended) 596// To test a GPR then do a PC-relative conditional branch. 597// 598def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 599 600 601// 602//Format: BREAK immediate 603// Purpose: Breakpoint 604// To cause a Breakpoint exception. 605 606def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>; 607// 608// Format: BTEQZ offset MIPS16e 609// Purpose: Branch on T Equal to Zero (Extended) 610// To test special register T then do a PC-relative conditional branch. 611// 612def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 613 let Uses = [T8]; 614} 615 616def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 617 618def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 619 cbranch16; 620 621def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 622 623def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 624 625def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 626 627def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 628 cbranch16; 629 630// 631// Format: BTNEZ offset MIPS16e 632// Purpose: Branch on T Not Equal to Zero (Extended) 633// To test special register T then do a PC-relative conditional branch. 634// 635def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 636 let Uses = [T8]; 637} 638 639def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 640 641def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 642 643def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 644 645def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 646 647def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 648 649def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 650 cbranch16; 651 652// 653// Format: CMP rx, ry MIPS16e 654// Purpose: Compare 655// To compare the contents of two GPRs. 656// 657def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> { 658 let Defs = [T8]; 659} 660 661// 662// Format: CMPI rx, immediate MIPS16e 663// Purpose: Compare Immediate 664// To compare a constant with the contents of a GPR. 665// 666def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> { 667 let Defs = [T8]; 668} 669 670// 671// Format: CMPI rx, immediate MIPS16e 672// Purpose: Compare Immediate (Extended) 673// To compare a constant with the contents of a GPR. 674// 675def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> { 676 let Defs = [T8]; 677} 678 679 680// 681// Format: DIV rx, ry MIPS16e 682// Purpose: Divide Word 683// To divide 32-bit signed integers. 684// 685def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 686 let Defs = [HI0, LO0]; 687} 688 689// 690// Format: DIVU rx, ry MIPS16e 691// Purpose: Divide Unsigned Word 692// To divide 32-bit unsigned integers. 693// 694def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 695 let Defs = [HI0, LO0]; 696} 697// 698// Format: JAL target MIPS16e 699// Purpose: Jump and Link 700// To execute a procedure call within the current 256 MB-aligned 701// region and preserve the current ISA. 702// 703 704def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 705 let hasDelaySlot = 0; // not true, but we add the nop for now 706 let isCall=1; 707} 708 709// 710// Format: JR ra MIPS16e 711// Purpose: Jump Register Through Register ra 712// To execute a branch to the instruction address in the return 713// address register. 714// 715 716def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 717 let isBranch = 1; 718 let isIndirectBranch = 1; 719 let hasDelaySlot = 1; 720 let isTerminator=1; 721 let isBarrier=1; 722} 723 724def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 725 let isBranch = 1; 726 let isIndirectBranch = 1; 727 let isTerminator=1; 728 let isBarrier=1; 729} 730 731def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 732 let isBranch = 1; 733 let isIndirectBranch = 1; 734 let isTerminator=1; 735 let isBarrier=1; 736} 737// 738// Format: LB ry, offset(rx) MIPS16e 739// Purpose: Load Byte (Extended) 740// To load a byte from memory as a signed value. 741// 742def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 743 let isCodeGenOnly = 1; 744} 745 746// 747// Format: LBU ry, offset(rx) MIPS16e 748// Purpose: Load Byte Unsigned (Extended) 749// To load a byte from memory as a unsigned value. 750// 751def LbuRxRyOffMemX16: 752 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 753 let isCodeGenOnly = 1; 754} 755 756// 757// Format: LH ry, offset(rx) MIPS16e 758// Purpose: Load Halfword signed (Extended) 759// To load a halfword from memory as a signed value. 760// 761def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 762 let isCodeGenOnly = 1; 763} 764 765// 766// Format: LHU ry, offset(rx) MIPS16e 767// Purpose: Load Halfword unsigned (Extended) 768// To load a halfword from memory as an unsigned value. 769// 770def LhuRxRyOffMemX16: 771 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 772 let isCodeGenOnly = 1; 773} 774 775// 776// Format: LI rx, immediate MIPS16e 777// Purpose: Load Immediate 778// To load a constant into a GPR. 779// 780def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 781 782// 783// Format: LI rx, immediate MIPS16e 784// Purpose: Load Immediate (Extended) 785// To load a constant into a GPR. 786// 787def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 788 789def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> { 790 let isCodeGenOnly = 1; 791} 792 793// 794// Format: LW ry, offset(rx) MIPS16e 795// Purpose: Load Word (Extended) 796// To load a word from memory as a signed value. 797// 798def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 799 let isCodeGenOnly = 1; 800} 801 802// Format: LW rx, offset(sp) MIPS16e 803// Purpose: Load Word (SP-Relative, Extended) 804// To load an SP-relative word from memory as a signed value. 805// 806def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{ 807 let Uses = [SP]; 808} 809 810def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad; 811 812def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad; 813// 814// Format: MOVE r32, rz MIPS16e 815// Purpose: Move 816// To move the contents of a GPR to a GPR. 817// 818def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 819 820// 821// Format: MOVE ry, r32 MIPS16e 822//Purpose: Move 823// To move the contents of a GPR to a GPR. 824// 825def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 826 827// 828// Format: MFHI rx MIPS16e 829// Purpose: Move From HI Register 830// To copy the special purpose HI register to a GPR. 831// 832def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 833 let Uses = [HI0]; 834 let neverHasSideEffects = 1; 835} 836 837// 838// Format: MFLO rx MIPS16e 839// Purpose: Move From LO Register 840// To copy the special purpose LO register to a GPR. 841// 842def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 843 let Uses = [LO0]; 844 let neverHasSideEffects = 1; 845} 846 847// 848// Pseudo Instruction for mult 849// 850def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 851 let isCommutable = 1; 852 let neverHasSideEffects = 1; 853 let Defs = [HI0, LO0]; 854} 855 856def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 857 let isCommutable = 1; 858 let neverHasSideEffects = 1; 859 let Defs = [HI0, LO0]; 860} 861 862// 863// Format: MULT rx, ry MIPS16e 864// Purpose: Multiply Word 865// To multiply 32-bit signed integers. 866// 867def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 868 let isCommutable = 1; 869 let neverHasSideEffects = 1; 870 let Defs = [HI0, LO0]; 871} 872 873// 874// Format: MULTU rx, ry MIPS16e 875// Purpose: Multiply Unsigned Word 876// To multiply 32-bit unsigned integers. 877// 878def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 879 let isCommutable = 1; 880 let neverHasSideEffects = 1; 881 let Defs = [HI0, LO0]; 882} 883 884// 885// Format: NEG rx, ry MIPS16e 886// Purpose: Negate 887// To negate an integer value. 888// 889def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 890 891// 892// Format: NOT rx, ry MIPS16e 893// Purpose: Not 894// To complement an integer value 895// 896def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 897 898// 899// Format: OR rx, ry MIPS16e 900// Purpose: Or 901// To do a bitwise logical OR. 902// 903def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 904 905// 906// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 907// (All args are optional) MIPS16e 908// Purpose: Restore Registers and Deallocate Stack Frame 909// To deallocate a stack frame before exit from a subroutine, 910// restoring return address and static registers, and adjusting 911// stack 912// 913 914// fixed form for restoring RA and the frame 915// for direct object emitter, encoding needs to be adjusted for the 916// frame size 917// 918let ra=1, s=0,s0=1,s1=1 in 919def RestoreRaF16: 920 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 921 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad { 922 let isCodeGenOnly = 1; 923 let Defs = [S0, S1, S2, RA, SP]; 924 let Uses = [SP]; 925} 926 927// Use Restore to increment SP since SP is not a Mip 16 register, this 928// is an easy way to do that which does not require a register. 929// 930let ra=0, s=0,s0=0,s1=0 in 931def RestoreIncSpF16: 932 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 933 "restore\t$frame_size", [], IILoad >, MayLoad { 934 let isCodeGenOnly = 1; 935 let Defs = [SP]; 936 let Uses = [SP]; 937} 938 939// 940// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 941// MIPS16e 942// Purpose: Save Registers and Set Up Stack Frame 943// To set up a stack frame on entry to a subroutine, 944// saving return address and static registers, and adjusting stack 945// 946let ra=1, s=1,s0=1,s1=1 in 947def SaveRaF16: 948 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 949 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore { 950 let isCodeGenOnly = 1; 951 let Uses = [RA, SP, S0, S1, S2]; 952 let Defs = [SP]; 953} 954 955// 956// Use Save to decrement the SP by a constant since SP is not 957// a Mips16 register. 958// 959let ra=0, s=0,s0=0,s1=0 in 960def SaveDecSpF16: 961 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 962 "save\t$frame_size", [], IIStore >, MayStore { 963 let isCodeGenOnly = 1; 964 let Uses = [SP]; 965 let Defs = [SP]; 966} 967// 968// Format: SB ry, offset(rx) MIPS16e 969// Purpose: Store Byte (Extended) 970// To store a byte to memory. 971// 972def SbRxRyOffMemX16: 973 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 974 975// 976// Format: SEB rx MIPS16e 977// Purpose: Sign-Extend Byte 978// Sign-extend least significant byte in register rx. 979// 980def SebRx16 981 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>; 982 983// 984// Format: SEH rx MIPS16e 985// Purpose: Sign-Extend Halfword 986// Sign-extend least significant word in register rx. 987// 988def SehRx16 989 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>; 990 991// 992// The Sel(T) instructions are pseudos 993// T means that they use T8 implicitly. 994// 995// 996// Format: SelBeqZ rd, rs, rt 997// Purpose: if rt==0, do nothing 998// else rs = rt 999// 1000def SelBeqZ: Sel<"beqz">; 1001 1002// 1003// Format: SelTBteqZCmp rd, rs, rl, rr 1004// Purpose: b = Cmp rl, rr. 1005// If b==0 then do nothing. 1006// if b!=0 then rd = rs 1007// 1008def SelTBteqZCmp: SelT<"bteqz", "cmp">; 1009 1010// 1011// Format: SelTBteqZCmpi rd, rs, rl, rr 1012// Purpose: b = Cmpi rl, imm. 1013// If b==0 then do nothing. 1014// if b!=0 then rd = rs 1015// 1016def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 1017 1018// 1019// Format: SelTBteqZSlt rd, rs, rl, rr 1020// Purpose: b = Slt rl, rr. 1021// If b==0 then do nothing. 1022// if b!=0 then rd = rs 1023// 1024def SelTBteqZSlt: SelT<"bteqz", "slt">; 1025 1026// 1027// Format: SelTBteqZSlti rd, rs, rl, rr 1028// Purpose: b = Slti rl, imm. 1029// If b==0 then do nothing. 1030// if b!=0 then rd = rs 1031// 1032def SelTBteqZSlti: SeliT<"bteqz", "slti">; 1033 1034// 1035// Format: SelTBteqZSltu rd, rs, rl, rr 1036// Purpose: b = Sltu rl, rr. 1037// If b==0 then do nothing. 1038// if b!=0 then rd = rs 1039// 1040def SelTBteqZSltu: SelT<"bteqz", "sltu">; 1041 1042// 1043// Format: SelTBteqZSltiu rd, rs, rl, rr 1044// Purpose: b = Sltiu rl, imm. 1045// If b==0 then do nothing. 1046// if b!=0 then rd = rs 1047// 1048def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 1049 1050// 1051// Format: SelBnez rd, rs, rt 1052// Purpose: if rt!=0, do nothing 1053// else rs = rt 1054// 1055def SelBneZ: Sel<"bnez">; 1056 1057// 1058// Format: SelTBtneZCmp rd, rs, rl, rr 1059// Purpose: b = Cmp rl, rr. 1060// If b!=0 then do nothing. 1061// if b0=0 then rd = rs 1062// 1063def SelTBtneZCmp: SelT<"btnez", "cmp">; 1064 1065// 1066// Format: SelTBtnezCmpi rd, rs, rl, rr 1067// Purpose: b = Cmpi rl, imm. 1068// If b!=0 then do nothing. 1069// if b==0 then rd = rs 1070// 1071def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1072 1073// 1074// Format: SelTBtneZSlt rd, rs, rl, rr 1075// Purpose: b = Slt rl, rr. 1076// If b!=0 then do nothing. 1077// if b==0 then rd = rs 1078// 1079def SelTBtneZSlt: SelT<"btnez", "slt">; 1080 1081// 1082// Format: SelTBtneZSlti rd, rs, rl, rr 1083// Purpose: b = Slti rl, imm. 1084// If b!=0 then do nothing. 1085// if b==0 then rd = rs 1086// 1087def SelTBtneZSlti: SeliT<"btnez", "slti">; 1088 1089// 1090// Format: SelTBtneZSltu rd, rs, rl, rr 1091// Purpose: b = Sltu rl, rr. 1092// If b!=0 then do nothing. 1093// if b==0 then rd = rs 1094// 1095def SelTBtneZSltu: SelT<"btnez", "sltu">; 1096 1097// 1098// Format: SelTBtneZSltiu rd, rs, rl, rr 1099// Purpose: b = Slti rl, imm. 1100// If b!=0 then do nothing. 1101// if b==0 then rd = rs 1102// 1103def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1104// 1105// 1106// Format: SH ry, offset(rx) MIPS16e 1107// Purpose: Store Halfword (Extended) 1108// To store a halfword to memory. 1109// 1110def ShRxRyOffMemX16: 1111 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1112 1113// 1114// Format: SLL rx, ry, sa MIPS16e 1115// Purpose: Shift Word Left Logical (Extended) 1116// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits. 1117// 1118def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1119 1120// 1121// Format: SLLV ry, rx MIPS16e 1122// Purpose: Shift Word Left Logical Variable 1123// To execute a left-shift of a word by a variable number of bits. 1124// 1125def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1126 1127// Format: SLTI rx, immediate MIPS16e 1128// Purpose: Set on Less Than Immediate 1129// To record the result of a less-than comparison with a constant. 1130// 1131// 1132def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1133 let Defs = [T8]; 1134} 1135 1136// 1137// Format: SLTI rx, immediate MIPS16e 1138// Purpose: Set on Less Than Immediate (Extended) 1139// To record the result of a less-than comparison with a constant. 1140// 1141// 1142def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1143 let Defs = [T8]; 1144} 1145 1146def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1147 1148// Format: SLTIU rx, immediate MIPS16e 1149// Purpose: Set on Less Than Immediate Unsigned 1150// To record the result of a less-than comparison with a constant. 1151// 1152// 1153def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1154 let Defs = [T8]; 1155} 1156 1157// 1158// Format: SLTI rx, immediate MIPS16e 1159// Purpose: Set on Less Than Immediate Unsigned (Extended) 1160// To record the result of a less-than comparison with a constant. 1161// 1162// 1163def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1164 let Defs = [T8]; 1165} 1166// 1167// Format: SLTIU rx, immediate MIPS16e 1168// Purpose: Set on Less Than Immediate Unsigned (Extended) 1169// To record the result of a less-than comparison with a constant. 1170// 1171def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1172 1173// 1174// Format: SLT rx, ry MIPS16e 1175// Purpose: Set on Less Than 1176// To record the result of a less-than comparison. 1177// 1178def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{ 1179 let Defs = [T8]; 1180} 1181 1182def SltCCRxRy16: FCCRR16_ins<"slt">; 1183 1184// Format: SLTU rx, ry MIPS16e 1185// Purpose: Set on Less Than Unsigned 1186// To record the result of an unsigned less-than comparison. 1187// 1188def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{ 1189 let Defs = [T8]; 1190} 1191 1192def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1193 let isCodeGenOnly=1; 1194 let Defs = [T8]; 1195} 1196 1197 1198def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1199// 1200// Format: SRAV ry, rx MIPS16e 1201// Purpose: Shift Word Right Arithmetic Variable 1202// To execute an arithmetic right-shift of a word by a variable 1203// number of bits. 1204// 1205def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1206 1207 1208// 1209// Format: SRA rx, ry, sa MIPS16e 1210// Purpose: Shift Word Right Arithmetic (Extended) 1211// To execute an arithmetic right-shift of a word by a fixed 1212// number of bits-1 to 8 bits. 1213// 1214def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1215 1216 1217// 1218// Format: SRLV ry, rx MIPS16e 1219// Purpose: Shift Word Right Logical Variable 1220// To execute a logical right-shift of a word by a variable 1221// number of bits. 1222// 1223def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1224 1225 1226// 1227// Format: SRL rx, ry, sa MIPS16e 1228// Purpose: Shift Word Right Logical (Extended) 1229// To execute a logical right-shift of a word by a fixed 1230// number of bits-1 to 31 bits. 1231// 1232def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1233 1234// 1235// Format: SUBU rz, rx, ry MIPS16e 1236// Purpose: Subtract Unsigned Word 1237// To subtract 32-bit integers 1238// 1239def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1240 1241// 1242// Format: SW ry, offset(rx) MIPS16e 1243// Purpose: Store Word (Extended) 1244// To store a word to memory. 1245// 1246def SwRxRyOffMemX16: 1247 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1248 1249// 1250// Format: SW rx, offset(sp) MIPS16e 1251// Purpose: Store Word rx (SP-Relative) 1252// To store an SP-relative word to memory. 1253// 1254def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins 1255 <0b11010, "sw", IIStore>, MayStore; 1256 1257// 1258// 1259// Format: XOR rx, ry MIPS16e 1260// Purpose: Xor 1261// To do a bitwise logical XOR. 1262// 1263def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1264 1265class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1266 let Predicates = [InMips16Mode]; 1267} 1268 1269// Unary Arith/Logic 1270// 1271class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1272 Mips16Pat<(OpNode CPU16Regs:$r), 1273 (I CPU16Regs:$r)>; 1274 1275def: ArithLogicU_pat<not, NotRxRy16>; 1276def: ArithLogicU_pat<ineg, NegRxRy16>; 1277 1278class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1279 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1280 (I CPU16Regs:$l, CPU16Regs:$r)>; 1281 1282def: ArithLogic16_pat<add, AdduRxRyRz16>; 1283def: ArithLogic16_pat<and, AndRxRxRy16>; 1284def: ArithLogic16_pat<mul, MultRxRyRz16>; 1285def: ArithLogic16_pat<or, OrRxRxRy16>; 1286def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1287def: ArithLogic16_pat<xor, XorRxRxRy16>; 1288 1289// Arithmetic and logical instructions with 2 register operands. 1290 1291class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1292 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1293 (I CPU16Regs:$in, imm_type:$imm)>; 1294 1295def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1296def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1297def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1298def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1299def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1300 1301class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1302 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1303 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1304 1305def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1306def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1307def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1308 1309class LoadM16_pat<PatFrag OpNode, Instruction I> : 1310 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1311 1312def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1313def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1314def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1315def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1316def: LoadM16_pat<load, LwRxRyOffMemX16>; 1317 1318class StoreM16_pat<PatFrag OpNode, Instruction I> : 1319 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1320 (I CPU16Regs:$r, addr16:$addr)>; 1321 1322def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1323def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1324def: StoreM16_pat<store, SwRxRyOffMemX16>; 1325 1326// Unconditional branch 1327class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1328 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1329 let Predicates = [InMips16Mode]; 1330 } 1331 1332def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1333 (Jal16 tglobaladdr:$dst)>; 1334 1335def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1336 (Jal16 texternalsym:$dst)>; 1337 1338// Indirect branch 1339def: Mips16Pat< 1340 (brind CPU16Regs:$rs), 1341 (JrcRx16 CPU16Regs:$rs)>; 1342 1343// Jump and Link (Call) 1344let isCall=1, hasDelaySlot=0 in 1345def JumpLinkReg16: 1346 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1347 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1348 1349// Mips16 pseudos 1350let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1351 hasExtraSrcRegAllocReq = 1 in 1352def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1353 1354 1355// setcc patterns 1356 1357class SetCC_R16<PatFrag cond_op, Instruction I>: 1358 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1359 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1360 1361class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1362 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1363 (I CPU16Regs:$rx, imm_type:$imm16)>; 1364 1365 1366def: Mips16Pat<(i32 addr16:$addr), 1367 (AddiuRxRyOffMemX16 addr16:$addr)>; 1368 1369 1370// Large (>16 bit) immediate loads 1371def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>; 1372 1373// Carry MipsPatterns 1374def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1375 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1376def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1377 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1378def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1379 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1380 1381// 1382// Some branch conditional patterns are not generated by llvm at this time. 1383// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1384// comparison they are used and for unsigned a different pattern is used. 1385// I am pushing upstream from the full mips16 port and it seemed that I needed 1386// these earlier and the mips32 port has these but now I cannot create test 1387// cases that use these patterns. While I sort this all out I will leave these 1388// extra patterns commented out and if I can be sure they are really not used, 1389// I will delete the code. I don't want to check the code in uncommented without 1390// a valid test case. In some cases, the compiler is generating patterns with 1391// setcc instead and earlier I had implemented setcc first so may have masked 1392// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1393// figure out how to enable the brcond patterns or else possibly new 1394// combinations of of brcond and setcc. 1395// 1396// 1397// bcond-seteq 1398// 1399def: Mips16Pat 1400 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1401 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1402 >; 1403 1404 1405def: Mips16Pat 1406 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1407 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1408 >; 1409 1410def: Mips16Pat 1411 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1412 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1413 >; 1414 1415// 1416// bcond-setgt (do we need to have this pair of setlt, setgt??) 1417// 1418def: Mips16Pat 1419 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1420 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1421 >; 1422 1423// 1424// bcond-setge 1425// 1426def: Mips16Pat 1427 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1428 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1429 >; 1430 1431// 1432// never called because compiler transforms a >= k to a > (k-1) 1433def: Mips16Pat 1434 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1435 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1436 >; 1437 1438// 1439// bcond-setlt 1440// 1441def: Mips16Pat 1442 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1443 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1444 >; 1445 1446def: Mips16Pat 1447 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1448 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1449 >; 1450 1451// 1452// bcond-setle 1453// 1454def: Mips16Pat 1455 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1456 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1457 >; 1458 1459// 1460// bcond-setne 1461// 1462def: Mips16Pat 1463 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1464 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1465 >; 1466 1467def: Mips16Pat 1468 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1469 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1470 >; 1471 1472def: Mips16Pat 1473 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1474 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1475 >; 1476 1477// 1478// This needs to be there but I forget which code will generate it 1479// 1480def: Mips16Pat 1481 <(brcond CPU16Regs:$rx, bb:$targ16), 1482 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1483 >; 1484 1485// 1486 1487// 1488// bcond-setugt 1489// 1490//def: Mips16Pat 1491// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1492// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1493// >; 1494 1495// 1496// bcond-setuge 1497// 1498//def: Mips16Pat 1499// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1500// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1501// >; 1502 1503 1504// 1505// bcond-setult 1506// 1507//def: Mips16Pat 1508// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1509// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1510// >; 1511 1512def: UncondBranch16_pat<br, BimmX16>; 1513 1514// Small immediates 1515def: Mips16Pat<(i32 immSExt16:$in), 1516 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1517 1518def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1519 1520// 1521// MipsDivRem 1522// 1523def: Mips16Pat 1524 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), 1525 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1526 1527// 1528// MipsDivRemU 1529// 1530def: Mips16Pat 1531 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry), 1532 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1533 1534// signed a,b 1535// x = (a>=b)?x:y 1536// 1537// if !(a < b) x = y 1538// 1539def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1540 CPU16Regs:$x, CPU16Regs:$y), 1541 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1542 CPU16Regs:$a, CPU16Regs:$b)>; 1543 1544// signed a,b 1545// x = (a>b)?x:y 1546// 1547// if (b < a) x = y 1548// 1549def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1550 CPU16Regs:$x, CPU16Regs:$y), 1551 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1552 CPU16Regs:$b, CPU16Regs:$a)>; 1553 1554// unsigned a,b 1555// x = (a>=b)?x:y 1556// 1557// if !(a < b) x = y; 1558// 1559def : Mips16Pat< 1560 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1561 CPU16Regs:$x, CPU16Regs:$y), 1562 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1563 CPU16Regs:$a, CPU16Regs:$b)>; 1564 1565// unsigned a,b 1566// x = (a>b)?x:y 1567// 1568// if (b < a) x = y 1569// 1570def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1571 CPU16Regs:$x, CPU16Regs:$y), 1572 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1573 CPU16Regs:$b, CPU16Regs:$a)>; 1574 1575// signed 1576// x = (a >= k)?x:y 1577// due to an llvm optimization, i don't think that this will ever 1578// be used. This is transformed into x = (a > k-1)?x:y 1579// 1580// 1581 1582//def : Mips16Pat< 1583// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1584// CPU16Regs:$T, CPU16Regs:$F), 1585// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1586// CPU16Regs:$lhs, immSExt16:$rhs)>; 1587 1588//def : Mips16Pat< 1589// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1590// CPU16Regs:$T, CPU16Regs:$F), 1591// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1592// CPU16Regs:$lhs, immSExt16:$rhs)>; 1593 1594// signed 1595// x = (a < k)?x:y 1596// 1597// if !(a < k) x = y; 1598// 1599def : Mips16Pat< 1600 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1601 CPU16Regs:$x, CPU16Regs:$y), 1602 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1603 CPU16Regs:$a, immSExt16:$b)>; 1604 1605 1606// 1607// 1608// signed 1609// x = (a <= b)? x : y 1610// 1611// if (b < a) x = y 1612// 1613def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1614 CPU16Regs:$x, CPU16Regs:$y), 1615 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1616 CPU16Regs:$b, CPU16Regs:$a)>; 1617 1618// 1619// unnsigned 1620// x = (a <= b)? x : y 1621// 1622// if (b < a) x = y 1623// 1624def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1625 CPU16Regs:$x, CPU16Regs:$y), 1626 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1627 CPU16Regs:$b, CPU16Regs:$a)>; 1628 1629// 1630// signed/unsigned 1631// x = (a == b)? x : y 1632// 1633// if (a != b) x = y 1634// 1635def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1636 CPU16Regs:$x, CPU16Regs:$y), 1637 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1638 CPU16Regs:$b, CPU16Regs:$a)>; 1639 1640// 1641// signed/unsigned 1642// x = (a == 0)? x : y 1643// 1644// if (a != 0) x = y 1645// 1646def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1647 CPU16Regs:$x, CPU16Regs:$y), 1648 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1649 CPU16Regs:$a)>; 1650 1651 1652// 1653// signed/unsigned 1654// x = (a == k)? x : y 1655// 1656// if (a != k) x = y 1657// 1658def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1659 CPU16Regs:$x, CPU16Regs:$y), 1660 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1661 CPU16Regs:$a, immZExt16:$k)>; 1662 1663 1664// 1665// signed/unsigned 1666// x = (a != b)? x : y 1667// 1668// if (a == b) x = y 1669// 1670// 1671def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1672 CPU16Regs:$x, CPU16Regs:$y), 1673 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1674 CPU16Regs:$b, CPU16Regs:$a)>; 1675 1676// 1677// signed/unsigned 1678// x = (a != 0)? x : y 1679// 1680// if (a == 0) x = y 1681// 1682def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1683 CPU16Regs:$x, CPU16Regs:$y), 1684 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1685 CPU16Regs:$a)>; 1686 1687// signed/unsigned 1688// x = (a)? x : y 1689// 1690// if (!a) x = y 1691// 1692def : Mips16Pat<(select CPU16Regs:$a, 1693 CPU16Regs:$x, CPU16Regs:$y), 1694 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1695 CPU16Regs:$a)>; 1696 1697 1698// 1699// signed/unsigned 1700// x = (a != k)? x : y 1701// 1702// if (a == k) x = y 1703// 1704def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1705 CPU16Regs:$x, CPU16Regs:$y), 1706 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1707 CPU16Regs:$a, immZExt16:$k)>; 1708 1709// 1710// When writing C code to test setxx these patterns, 1711// some will be transformed into 1712// other things. So we test using C code but using -O3 and -O0 1713// 1714// seteq 1715// 1716def : Mips16Pat 1717 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1718 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1719 1720def : Mips16Pat 1721 <(seteq CPU16Regs:$lhs, 0), 1722 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1723 1724 1725// 1726// setge 1727// 1728 1729def: Mips16Pat 1730 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1731 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1732 (LiRxImmX16 1))>; 1733 1734// 1735// For constants, llvm transforms this to: 1736// x > (k -1) and then reverses the operands to use setlt. So this pattern 1737// is not used now by the compiler. (Presumably checking that k-1 does not 1738// overflow). The compiler never uses this at a the current time, due to 1739// other optimizations. 1740// 1741//def: Mips16Pat 1742// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1743// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1744// (LiRxImmX16 1))>; 1745 1746// This catches the x >= -32768 case by transforming it to x > -32769 1747// 1748def: Mips16Pat 1749 <(setgt CPU16Regs:$lhs, -32769), 1750 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1751 (LiRxImmX16 1))>; 1752 1753// 1754// setgt 1755// 1756// 1757 1758def: Mips16Pat 1759 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1760 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1761 1762// 1763// setle 1764// 1765def: Mips16Pat 1766 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1767 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1768 1769// 1770// setlt 1771// 1772def: SetCC_R16<setlt, SltCCRxRy16>; 1773 1774def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1775 1776// 1777// setne 1778// 1779def : Mips16Pat 1780 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1781 (SltuCCRxRy16 (LiRxImmX16 0), 1782 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1783 1784 1785// 1786// setuge 1787// 1788def: Mips16Pat 1789 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1790 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1791 (LiRxImmX16 1))>; 1792 1793// this pattern will never be used because the compiler will transform 1794// x >= k to x > (k - 1) and then use SLT 1795// 1796//def: Mips16Pat 1797// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1798// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1799// (LiRxImmX16 1))>; 1800 1801// 1802// setugt 1803// 1804def: Mips16Pat 1805 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1806 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1807 1808// 1809// setule 1810// 1811def: Mips16Pat 1812 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1813 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1814 1815// 1816// setult 1817// 1818def: SetCC_R16<setult, SltuCCRxRy16>; 1819 1820def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1821 1822def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1823 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1824 1825// hi/lo relocs 1826def : Mips16Pat<(MipsHi tblockaddress:$in), 1827 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>; 1828def : Mips16Pat<(MipsHi tglobaladdr:$in), 1829 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1830def : Mips16Pat<(MipsHi tjumptable:$in), 1831 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1832def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1833 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1834 1835def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>; 1836 1837// wrapper_pic 1838class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1839 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1840 (ADDiuOp RC:$gp, node:$in)>; 1841 1842 1843def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1844def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1845 1846def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1847 (LbuRxRyOffMemX16 addr16:$src)>; 1848def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1849 (LhuRxRyOffMemX16 addr16:$src)>; 1850 1851def: Mips16Pat<(trap), (Break16)>; 1852 1853def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8), 1854 (SebRx16 CPU16Regs:$val)>; 1855 1856def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16), 1857 (SehRx16 CPU16Regs:$val)>; 1858 1859def GotPrologue16: 1860 MipsPseudo16< 1861 (outs CPU16Regs:$rh, CPU16Regs:$rl), 1862 (ins simm16:$immHi, simm16:$immLo), 1863 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ; 1864 1865// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 1866def cpinst_operand : Operand<i32> { 1867 // let PrintMethod = "printCPInstOperand"; 1868} 1869 1870// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1871// the function. The first operand is the ID# for this instruction, the second 1872// is the index into the MachineConstantPool that this is, the third is the 1873// size in bytes of this constant pool entry. 1874// 1875let neverHasSideEffects = 1, isNotDuplicable = 1 in 1876def CONSTPOOL_ENTRY : 1877MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1878 i32imm:$size), "foo", []>; 1879 1880