Mips16InstrInfo.td revision 24e79e55daa5d2812d2a5ea0a282ebe48ef465e6
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// RRR-type instruction format 16// 17 18class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 19 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 20 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 21 22// 23// I8_MOV32R instruction format (used only by MOV32R instruction) 24// 25class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 26 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 27 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 28 29// 30// EXT-RI instruction format 31// 32 33class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 34 InstrItinClass itin>: 35 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 36 !strconcat(asmstr, asmstr2), [], itin>; 37 38class FEXT_RI16_ins<bits<5> _op, string asmstr, 39 InstrItinClass itin>: 40 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 41 42class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 43 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 44 45 46class FEXT_2RI16_ins<bits<5> _op, string asmstr, 47 InstrItinClass itin>: 48 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 49 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 50 let Constraints = "$rx_ = $rx"; 51} 52 53 54// 55// RR-type instruction format 56// 57 58class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 59 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 60 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 61} 62 63class FRxRxRy16_ins<bits<5> f, string asmstr, 64 InstrItinClass itin> : 65 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 66 !strconcat(asmstr, "\t$rz, $ry"), 67 [], itin> { 68 let Constraints = "$rx = $rz"; 69} 70 71let rx=0 in 72class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 73 string asmstr, InstrItinClass itin>: 74 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 75 [], itin> ; 76 77// 78// EXT-RRI instruction format 79// 80 81class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 82 InstrItinClass itin>: 83 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 84 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 85 86class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 87 InstrItinClass itin>: 88 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 89 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 90 91// 92// EXT-SHIFT instruction format 93// 94class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 95 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 96 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 97 98// 99// Address operand 100def mem16 : Operand<i32> { 101 let PrintMethod = "printMemOperand"; 102 let MIOperandInfo = (ops CPU16Regs, simm16); 103 let EncoderMethod = "getMemEncoding"; 104} 105 106// 107// Some general instruction class info 108// 109// 110 111class ArithLogic16Defs<bit isCom=0> { 112 bits<5> shamt = 0; 113 bit isCommutable = isCom; 114 bit isReMaterializable = 1; 115 bit neverHasSideEffects = 1; 116} 117 118// 119 120// Format: ADDIU rx, immediate MIPS16e 121// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 122// To add a constant to a 32-bit integer. 123// 124def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 125 126def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 127 ArithLogic16Defs<0>; 128 129// 130 131// Format: ADDIU rx, pc, immediate MIPS16e 132// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 133// To add a constant to the program counter. 134// 135def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 136// 137// Format: ADDU rz, rx, ry MIPS16e 138// Purpose: Add Unsigned Word (3-Operand) 139// To add 32-bit integers. 140// 141 142def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 143 144// 145// Format: AND rx, ry MIPS16e 146// Purpose: AND 147// To do a bitwise logical AND. 148 149def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 150 151// 152// Format: JR ra MIPS16e 153// Purpose: Jump Register Through Register ra 154// To execute a branch to the instruction address in the return 155// address register. 156// 157 158def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>; 159 160// 161// Format: LB ry, offset(rx) MIPS16e 162// Purpose: Load Byte (Extended) 163// To load a byte from memory as a signed value. 164// 165def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IIAlu>; 166 167// 168// Format: LBU ry, offset(rx) MIPS16e 169// Purpose: Load Byte Unsigned (Extended) 170// To load a byte from memory as a unsigned value. 171// 172def LbuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IIAlu>; 173 174// 175// Format: LH ry, offset(rx) MIPS16e 176// Purpose: Load Halfword signed (Extended) 177// To load a halfword from memory as a signed value. 178// 179def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IIAlu>; 180 181// 182// Format: LHU ry, offset(rx) MIPS16e 183// Purpose: Load Halfword unsigned (Extended) 184// To load a halfword from memory as an unsigned value. 185// 186def LhuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IIAlu>; 187 188// 189// Format: LI rx, immediate MIPS16e 190// Purpose: Load Immediate (Extended) 191// To load a constant into a GPR. 192// 193def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 194 195// 196// Format: LW ry, offset(rx) MIPS16e 197// Purpose: Load Word (Extended) 198// To load a word from memory as a signed value. 199// 200def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>; 201 202// 203// Format: MOVE r32, rz MIPS16e 204// Purpose: Move 205// To move the contents of a GPR to a GPR. 206// 207def Mov32R16: FI8_MOV32R16_ins<"move", IIAlu>; 208 209// 210// Format: NEG rx, ry MIPS16e 211// Purpose: Negate 212// To negate an integer value. 213// 214def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>; 215 216// 217// Format: NOT rx, ry MIPS16e 218// Purpose: Not 219// To complement an integer value 220// 221def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>; 222 223// 224// Format: OR rx, ry MIPS16e 225// Purpose: Or 226// To do a bitwise logical OR. 227// 228def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 229 230// 231// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 232// (All args are optional) MIPS16e 233// Purpose: Restore Registers and Deallocate Stack Frame 234// To deallocate a stack frame before exit from a subroutine, 235// restoring return address and static registers, and adjusting 236// stack 237// 238 239// fixed form for restoring RA and the frame 240// for direct object emitter, encoding needs to be adjusted for the 241// frame size 242// 243let ra=1, s=0,s0=0,s1=0 in 244def RestoreRaF16: 245 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 246 "restore \t$$ra, $frame_size", [], IILoad >; 247 248// 249// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 250// MIPS16e 251// Purpose: Save Registers and Set Up Stack Frame 252// To set up a stack frame on entry to a subroutine, 253// saving return address and static registers, and adjusting stack 254// 255let ra=1, s=1,s0=0,s1=0 in 256def SaveRaF16: 257 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 258 "save \t$$ra, $frame_size", [], IILoad >; 259 260// 261// Format: SB ry, offset(rx) MIPS16e 262// Purpose: Store Byte (Extended) 263// To store a byte to memory. 264// 265def SbRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIAlu>; 266 267// 268// Format: SH ry, offset(rx) MIPS16e 269// Purpose: Store Halfword (Extended) 270// To store a halfword to memory. 271// 272def ShRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIAlu>; 273 274// 275// Format: SLL rx, ry, sa MIPS16e 276// Purpose: Shift Word Left Logical (Extended) 277// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 278// 279def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 280 281// 282// Format: SLLV ry, rx MIPS16e 283// Purpose: Shift Word Left Logical Variable 284// To execute a left-shift of a word by a variable number of bits. 285// 286def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 287 288 289// 290// Format: SRAV ry, rx MIPS16e 291// Purpose: Shift Word Right Arithmetic Variable 292// To execute an arithmetic right-shift of a word by a variable 293// number of bits. 294// 295def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 296 297 298// 299// Format: SRA rx, ry, sa MIPS16e 300// Purpose: Shift Word Right Arithmetic (Extended) 301// To execute an arithmetic right-shift of a word by a fixed 302// number of bits—1 to 8 bits. 303// 304def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 305 306 307// 308// Format: SRLV ry, rx MIPS16e 309// Purpose: Shift Word Right Logical Variable 310// To execute a logical right-shift of a word by a variable 311// number of bits. 312// 313def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 314 315 316// 317// Format: SRL rx, ry, sa MIPS16e 318// Purpose: Shift Word Right Logical (Extended) 319// To execute a logical right-shift of a word by a fixed 320// number of bits—1 to 31 bits. 321// 322def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 323 324// 325// Format: SUBU rz, rx, ry MIPS16e 326// Purpose: Subtract Unsigned Word 327// To subtract 32-bit integers 328// 329def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 330 331// 332// Format: SW ry, offset(rx) MIPS16e 333// Purpose: Store Word (Extended) 334// To store a word to memory. 335// 336def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIAlu>; 337 338// 339// Format: XOR rx, ry MIPS16e 340// Purpose: Xor 341// To do a bitwise logical XOR. 342// 343def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 344 345class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 346 let Predicates = [InMips16Mode]; 347} 348 349// Unary Arith/Logic 350// 351class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 352 Mips16Pat<(OpNode CPU16Regs:$r), 353 (I CPU16Regs:$r)>; 354 355def: ArithLogicU_pat<not, NotRxRy16>; 356def: ArithLogicU_pat<ineg, NegRxRy16>; 357 358class ArithLogic16_pat<SDNode OpNode, Instruction I> : 359 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 360 (I CPU16Regs:$l, CPU16Regs:$r)>; 361 362def: ArithLogic16_pat<add, AdduRxRyRz16>; 363def: ArithLogic16_pat<and, AndRxRxRy16>; 364def: ArithLogic16_pat<or, OrRxRxRy16>; 365def: ArithLogic16_pat<sub, SubuRxRyRz16>; 366def: ArithLogic16_pat<xor, XorRxRxRy16>; 367 368// Arithmetic and logical instructions with 2 register operands. 369 370class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 371 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 372 (I CPU16Regs:$in, imm_type:$imm)>; 373 374def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 375def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 376def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 377def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 378 379class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 380 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 381 (I CPU16Regs:$r, CPU16Regs:$ra)>; 382 383def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 384def: shift_rotate_reg16_pat<sra, SravRxRy16>; 385def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 386 387class LoadM16_pat<PatFrag OpNode, Instruction I> : 388 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>; 389 390def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 391def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 392def: LoadM16_pat<sextloadi16_a, LhRxRyOffMemX16>; 393def: LoadM16_pat<zextloadi16_a, LhuRxRyOffMemX16>; 394def: LoadM16_pat<load_a, LwRxRyOffMemX16>; 395 396class StoreM16_pat<PatFrag OpNode, Instruction I> : 397 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>; 398 399def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 400def: StoreM16_pat<truncstorei16_a, ShRxRyOffMemX16>; 401def: StoreM16_pat<store_a, SwRxRyOffMemX16>; 402 403 404// Jump and Link (Call) 405let isCall=1, hasDelaySlot=1 in 406def JumpLinkReg16: 407 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 408 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 409 410// Mips16 pseudos 411let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 412 hasExtraSrcRegAllocReq = 1 in 413def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 414 415// Small immediates 416def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 417 418def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 419 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 420