Mips16InstrInfo.td revision 3a9f4568fbb974844afacd12ab9b62e8844fd8ad
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16Regs, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// Compare a register and immediate and place result in CC 36// Implicit use of T8 37// 38// EXT-CCRR Instruction format 39// 40class FEXT_CCRXI16_ins<bits<5> _op, string asmstr, 41 InstrItinClass itin>: 42 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 43 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> { 44 let isCodeGenOnly=1; 45} 46 47// 48// EXT-I instruction format 49// 50class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 51 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 52 !strconcat(asmstr, "\t$imm16"),[], itin>; 53 54// 55// EXT-I8 instruction format 56// 57 58class FEXT_I816_ins_base<bits<3> _func, string asmstr, 59 string asmstr2, InstrItinClass itin>: 60 FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2), 61 [], itin>; 62 63class FEXT_I816_ins<bits<3> _func, string asmstr, 64 InstrItinClass itin>: 65 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 66 67// 68// Assembler formats in alphabetical order. 69// Natural and pseudos are mixed together. 70// 71// Compare two registers and place result in CC 72// Implicit use of T8 73// 74// CC-RR Instruction format 75// 76class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 77 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 78 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> { 79 let isCodeGenOnly=1; 80} 81 82// 83// EXT-RI instruction format 84// 85 86class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 87 InstrItinClass itin>: 88 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 89 !strconcat(asmstr, asmstr2), [], itin>; 90 91class FEXT_RI16_ins<bits<5> _op, string asmstr, 92 InstrItinClass itin>: 93 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 94 95class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 96 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 97 98class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 99 InstrItinClass itin>: 100 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 101 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 102 103class FEXT_2RI16_ins<bits<5> _op, string asmstr, 104 InstrItinClass itin>: 105 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 106 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 107 let Constraints = "$rx_ = $rx"; 108} 109 110 111// this has an explicit sp argument that we ignore to work around a problem 112// in the compiler 113class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 114 InstrItinClass itin>: 115 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 116 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 117 118// 119// EXT-RRI instruction format 120// 121 122class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 123 InstrItinClass itin>: 124 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 125 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 126 127class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 128 InstrItinClass itin>: 129 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 130 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 131 132// 133// 134// EXT-RRI-A instruction format 135// 136 137class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 138 InstrItinClass itin>: 139 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 140 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 141 142// 143// EXT-SHIFT instruction format 144// 145class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 146 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 147 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 148 149// 150// EXT-T8I8 151// 152class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2, 153 InstrItinClass itin>: 154 FEXT_I816<_func, (outs), 155 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 156 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 157 !strconcat(asmstr, "\t$imm"))),[], itin> { 158 let isCodeGenOnly=1; 159} 160 161// 162// EXT-T8I8I 163// 164class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2, 165 InstrItinClass itin>: 166 FEXT_I816<_func, (outs), 167 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 168 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 169 !strconcat(asmstr, "\t$targ"))), [], itin> { 170 let isCodeGenOnly=1; 171} 172// 173 174 175// 176// I8_MOVR32 instruction format (used only by the MOVR32 instructio 177// 178class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 179 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 180 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 181 182// 183// I8_MOV32R instruction format (used only by MOV32R instruction) 184// 185 186class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 187 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 188 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 189 190// 191// This are pseudo formats for multiply 192// This first one can be changed to non pseudo now. 193// 194// MULT 195// 196class FMULT16_ins<string asmstr, InstrItinClass itin> : 197 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 198 !strconcat(asmstr, "\t$rx, $ry"), []>; 199 200// 201// MULT-LO 202// 203class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 204 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 205 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 206 let isCodeGenOnly=1; 207} 208 209// 210// RR-type instruction format 211// 212 213class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 214 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 215 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 216} 217 218class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 219 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 220 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ; 221 222// 223// maybe refactor but need a $zero as a dummy first parameter 224// 225class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 226 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 227 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 228 229class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 230 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 231 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 232 233 234class FRR16_M_ins<bits<5> f, string asmstr, 235 InstrItinClass itin> : 236 FRR16<f, (outs CPU16Regs:$rx), (ins), 237 !strconcat(asmstr, "\t$rx"), [], itin>; 238 239class FRxRxRy16_ins<bits<5> f, string asmstr, 240 InstrItinClass itin> : 241 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 242 !strconcat(asmstr, "\t$rz, $ry"), 243 [], itin> { 244 let Constraints = "$rx = $rz"; 245} 246 247let rx=0 in 248class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 249 string asmstr, InstrItinClass itin>: 250 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 251 [], itin> ; 252 253 254class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 255 string asmstr, InstrItinClass itin>: 256 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 257 !strconcat(asmstr, "\t $rx"), [], itin> ; 258 259// 260// RRR-type instruction format 261// 262 263class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 264 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 265 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 266 267// 268// These Sel patterns support the generation of conditional move 269// pseudo instructions. 270// 271// The nomenclature uses the components making up the pseudo and may 272// be a bit counter intuitive when compared with the end result we seek. 273// For example using a bqez in the example directly below results in the 274// conditional move being done if the tested register is not zero. 275// I considered in easier to check by keeping the pseudo consistent with 276// it's components but it could have been done differently. 277// 278// The simplest case is when can test and operand directly and do the 279// conditional move based on a simple mips16 conditional 280// branch instruction. 281// for example: 282// if $op == beqz or bnez: 283// 284// $op1 $rt, .+4 285// move $rd, $rs 286// 287// if $op == beqz, then if $rt != 0, then the conditional assignment 288// $rd = $rs is done. 289 290// if $op == bnez, then if $rt == 0, then the conditional assignment 291// $rd = $rs is done. 292// 293// So this pseudo class only has one operand, i.e. op 294// 295class Sel<bits<5> f1, string op, InstrItinClass itin>: 296 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 297 CPU16Regs:$rt), 298 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin, 299 Pseudo16> { 300 let isCodeGenOnly=1; 301 let Constraints = "$rd = $rd_"; 302} 303 304// 305// The next two instruction classes allow for an operand which tests 306// two operands and returns a value in register T8 and 307//then does a conditional branch based on the value of T8 308// 309 310// op2 can be cmpi or slti/sltiu 311// op1 can bteqz or btnez 312// the operands for op2 are a register and a signed constant 313// 314// $op2 $t, $imm ;test register t and branch conditionally 315// $op1 .+4 ;op1 is a conditional branch 316// move $rd, $rs 317// 318// 319class SeliT<bits<5> f1, string op1, bits<5> f2, string op2, 320 InstrItinClass itin>: 321 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 322 CPU16Regs:$rl, simm16:$imm), 323 !strconcat(op2, 324 !strconcat("\t$rl, $imm\n\t", 325 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 326 Pseudo16> { 327 let isCodeGenOnly=1; 328 let Constraints = "$rd = $rd_"; 329} 330 331// 332// op2 can be cmp or slt/sltu 333// op1 can be bteqz or btnez 334// the operands for op2 are two registers 335// op1 is a conditional branch 336// 337// 338// $op2 $rl, $rr ;test registers rl,rr 339// $op1 .+4 ;op2 is a conditional branch 340// move $rd, $rs 341// 342// 343class SelT<bits<5> f1, string op1, bits<5> f2, string op2, 344 InstrItinClass itin>: 345 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 346 CPU16Regs:$rl, CPU16Regs:$rr), 347 !strconcat(op2, 348 !strconcat("\t$rl, $rr\n\t", 349 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 350 Pseudo16> { 351 let isCodeGenOnly=1; 352 let Constraints = "$rd = $rd_"; 353} 354 355 356// 357// Some general instruction class info 358// 359// 360 361class ArithLogic16Defs<bit isCom=0> { 362 bits<5> shamt = 0; 363 bit isCommutable = isCom; 364 bit isReMaterializable = 1; 365 bit neverHasSideEffects = 1; 366} 367 368class branch16 { 369 bit isBranch = 1; 370 bit isTerminator = 1; 371 bit isBarrier = 1; 372} 373 374class cbranch16 { 375 bit isBranch = 1; 376 bit isTerminator = 1; 377} 378 379class MayLoad { 380 bit mayLoad = 1; 381} 382 383class MayStore { 384 bit mayStore = 1; 385} 386// 387 388// Format: ADDIU rx, immediate MIPS16e 389// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 390// To add a constant to a 32-bit integer. 391// 392def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 393 394def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 395 ArithLogic16Defs<0>; 396 397def AddiuRxRyOffMemX16: 398 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 399 400// 401 402// Format: ADDIU rx, pc, immediate MIPS16e 403// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 404// To add a constant to the program counter. 405// 406def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 407// 408// Format: ADDU rz, rx, ry MIPS16e 409// Purpose: Add Unsigned Word (3-Operand) 410// To add 32-bit integers. 411// 412 413def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 414 415// 416// Format: AND rx, ry MIPS16e 417// Purpose: AND 418// To do a bitwise logical AND. 419 420def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 421 422 423// 424// Format: BEQZ rx, offset MIPS16e 425// Purpose: Branch on Equal to Zero (Extended) 426// To test a GPR then do a PC-relative conditional branch. 427// 428def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 429 430// Format: B offset MIPS16e 431// Purpose: Unconditional Branch 432// To do an unconditional PC-relative branch. 433// 434def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 435 436// 437// Format: BNEZ rx, offset MIPS16e 438// Purpose: Branch on Not Equal to Zero (Extended) 439// To test a GPR then do a PC-relative conditional branch. 440// 441def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 442 443// 444// Format: BTEQZ offset MIPS16e 445// Purpose: Branch on T Equal to Zero (Extended) 446// To test special register T then do a PC-relative conditional branch. 447// 448def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; 449 450def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16; 451 452def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>, 453 cbranch16; 454 455def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16; 456 457def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16; 458 459def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16; 460 461def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>, 462 cbranch16; 463 464// 465// Format: BTNEZ offset MIPS16e 466// Purpose: Branch on T Not Equal to Zero (Extended) 467// To test special register T then do a PC-relative conditional branch. 468// 469def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; 470 471def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16; 472 473def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16; 474 475def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16; 476 477def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16; 478 479def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16; 480 481def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>, 482 cbranch16; 483 484// 485// Format: DIV rx, ry MIPS16e 486// Purpose: Divide Word 487// To divide 32-bit signed integers. 488// 489def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 490 let Defs = [HI, LO]; 491} 492 493// 494// Format: DIVU rx, ry MIPS16e 495// Purpose: Divide Unsigned Word 496// To divide 32-bit unsigned integers. 497// 498def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 499 let Defs = [HI, LO]; 500} 501 502 503// 504// Format: JR ra MIPS16e 505// Purpose: Jump Register Through Register ra 506// To execute a branch to the instruction address in the return 507// address register. 508// 509 510def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 511 let isBranch = 1; 512 let isIndirectBranch = 1; 513 let hasDelaySlot = 1; 514 let isTerminator=1; 515 let isBarrier=1; 516} 517 518def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 519 let isBranch = 1; 520 let isIndirectBranch = 1; 521 let isTerminator=1; 522 let isBarrier=1; 523} 524// 525// Format: LB ry, offset(rx) MIPS16e 526// Purpose: Load Byte (Extended) 527// To load a byte from memory as a signed value. 528// 529def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; 530 531// 532// Format: LBU ry, offset(rx) MIPS16e 533// Purpose: Load Byte Unsigned (Extended) 534// To load a byte from memory as a unsigned value. 535// 536def LbuRxRyOffMemX16: 537 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad; 538 539// 540// Format: LH ry, offset(rx) MIPS16e 541// Purpose: Load Halfword signed (Extended) 542// To load a halfword from memory as a signed value. 543// 544def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; 545 546// 547// Format: LHU ry, offset(rx) MIPS16e 548// Purpose: Load Halfword unsigned (Extended) 549// To load a halfword from memory as an unsigned value. 550// 551def LhuRxRyOffMemX16: 552 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad; 553 554// 555// Format: LI rx, immediate MIPS16e 556// Purpose: Load Immediate (Extended) 557// To load a constant into a GPR. 558// 559def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 560 561// 562// Format: LW ry, offset(rx) MIPS16e 563// Purpose: Load Word (Extended) 564// To load a word from memory as a signed value. 565// 566def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad; 567 568// Format: LW rx, offset(sp) MIPS16e 569// Purpose: Load Word (SP-Relative, Extended) 570// To load an SP-relative word from memory as a signed value. 571// 572def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad; 573 574// 575// Format: MOVE r32, rz MIPS16e 576// Purpose: Move 577// To move the contents of a GPR to a GPR. 578// 579def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 580 581// 582// Format: MOVE ry, r32 MIPS16e 583//Purpose: Move 584// To move the contents of a GPR to a GPR. 585// 586def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 587 588// 589// Format: MFHI rx MIPS16e 590// Purpose: Move From HI Register 591// To copy the special purpose HI register to a GPR. 592// 593def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 594 let Uses = [HI]; 595 let neverHasSideEffects = 1; 596} 597 598// 599// Format: MFLO rx MIPS16e 600// Purpose: Move From LO Register 601// To copy the special purpose LO register to a GPR. 602// 603def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 604 let Uses = [LO]; 605 let neverHasSideEffects = 1; 606} 607 608// 609// Pseudo Instruction for mult 610// 611def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 612 let isCommutable = 1; 613 let neverHasSideEffects = 1; 614 let Defs = [HI, LO]; 615} 616 617def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 618 let isCommutable = 1; 619 let neverHasSideEffects = 1; 620 let Defs = [HI, LO]; 621} 622 623// 624// Format: MULT rx, ry MIPS16e 625// Purpose: Multiply Word 626// To multiply 32-bit signed integers. 627// 628def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 629 let isCommutable = 1; 630 let neverHasSideEffects = 1; 631 let Defs = [HI, LO]; 632} 633 634// 635// Format: MULTU rx, ry MIPS16e 636// Purpose: Multiply Unsigned Word 637// To multiply 32-bit unsigned integers. 638// 639def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 640 let isCommutable = 1; 641 let neverHasSideEffects = 1; 642 let Defs = [HI, LO]; 643} 644 645// 646// Format: NEG rx, ry MIPS16e 647// Purpose: Negate 648// To negate an integer value. 649// 650def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 651 652// 653// Format: NOT rx, ry MIPS16e 654// Purpose: Not 655// To complement an integer value 656// 657def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 658 659// 660// Format: OR rx, ry MIPS16e 661// Purpose: Or 662// To do a bitwise logical OR. 663// 664def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 665 666// 667// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 668// (All args are optional) MIPS16e 669// Purpose: Restore Registers and Deallocate Stack Frame 670// To deallocate a stack frame before exit from a subroutine, 671// restoring return address and static registers, and adjusting 672// stack 673// 674 675// fixed form for restoring RA and the frame 676// for direct object emitter, encoding needs to be adjusted for the 677// frame size 678// 679let ra=1, s=0,s0=1,s1=1 in 680def RestoreRaF16: 681 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 682 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 683 let isCodeGenOnly = 1; 684} 685 686// 687// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 688// MIPS16e 689// Purpose: Save Registers and Set Up Stack Frame 690// To set up a stack frame on entry to a subroutine, 691// saving return address and static registers, and adjusting stack 692// 693let ra=1, s=1,s0=1,s1=1 in 694def SaveRaF16: 695 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 696 "save \t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 697 let isCodeGenOnly = 1; 698} 699// 700// Format: SB ry, offset(rx) MIPS16e 701// Purpose: Store Byte (Extended) 702// To store a byte to memory. 703// 704def SbRxRyOffMemX16: 705 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 706 707// 708// The Sel(T) instructions are pseudos 709// T means that they use T8 implicitly. 710// 711// 712// Format: SelBeqZ rd, rs, rt 713// Purpose: if rt==0, do nothing 714// else rs = rt 715// 716def SelBeqZ: Sel<0b00100, "beqz", IIAlu>; 717 718// 719// Format: SelTBteqZCmp rd, rs, rl, rr 720// Purpose: b = Cmp rl, rr. 721// If b==0 then do nothing. 722// if b!=0 then rd = rs 723// 724def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>; 725 726// 727// Format: SelTBteqZCmpi rd, rs, rl, rr 728// Purpose: b = Cmpi rl, imm. 729// If b==0 then do nothing. 730// if b!=0 then rd = rs 731// 732def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>; 733 734// 735// Format: SelTBteqZSlt rd, rs, rl, rr 736// Purpose: b = Slt rl, rr. 737// If b==0 then do nothing. 738// if b!=0 then rd = rs 739// 740def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>; 741 742// 743// Format: SelTBteqZSlti rd, rs, rl, rr 744// Purpose: b = Slti rl, imm. 745// If b==0 then do nothing. 746// if b!=0 then rd = rs 747// 748def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>; 749 750// 751// Format: SelTBteqZSltu rd, rs, rl, rr 752// Purpose: b = Sltu rl, rr. 753// If b==0 then do nothing. 754// if b!=0 then rd = rs 755// 756def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>; 757 758// 759// Format: SelTBteqZSltiu rd, rs, rl, rr 760// Purpose: b = Sltiu rl, imm. 761// If b==0 then do nothing. 762// if b!=0 then rd = rs 763// 764def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>; 765 766// 767// Format: SelBnez rd, rs, rt 768// Purpose: if rt!=0, do nothing 769// else rs = rt 770// 771def SelBneZ: Sel<0b00101, "bnez", IIAlu>; 772 773// 774// Format: SelTBtneZCmp rd, rs, rl, rr 775// Purpose: b = Cmp rl, rr. 776// If b!=0 then do nothing. 777// if b0=0 then rd = rs 778// 779def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>; 780 781// 782// Format: SelTBtnezCmpi rd, rs, rl, rr 783// Purpose: b = Cmpi rl, imm. 784// If b!=0 then do nothing. 785// if b==0 then rd = rs 786// 787def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>; 788 789// 790// Format: SelTBtneZSlt rd, rs, rl, rr 791// Purpose: b = Slt rl, rr. 792// If b!=0 then do nothing. 793// if b==0 then rd = rs 794// 795def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>; 796 797// 798// Format: SelTBtneZSlti rd, rs, rl, rr 799// Purpose: b = Slti rl, imm. 800// If b!=0 then do nothing. 801// if b==0 then rd = rs 802// 803def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>; 804 805// 806// Format: SelTBtneZSltu rd, rs, rl, rr 807// Purpose: b = Sltu rl, rr. 808// If b!=0 then do nothing. 809// if b==0 then rd = rs 810// 811def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>; 812 813// 814// Format: SelTBtneZSltiu rd, rs, rl, rr 815// Purpose: b = Slti rl, imm. 816// If b!=0 then do nothing. 817// if b==0 then rd = rs 818// 819def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>; 820// 821// 822// Format: SH ry, offset(rx) MIPS16e 823// Purpose: Store Halfword (Extended) 824// To store a halfword to memory. 825// 826def ShRxRyOffMemX16: 827 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 828 829// 830// Format: SLL rx, ry, sa MIPS16e 831// Purpose: Shift Word Left Logical (Extended) 832// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 833// 834def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 835 836// 837// Format: SLLV ry, rx MIPS16e 838// Purpose: Shift Word Left Logical Variable 839// To execute a left-shift of a word by a variable number of bits. 840// 841def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 842 843// 844// Format: SLTI rx, immediate MIPS16e 845// Purpose: Set on Less Than Immediate (Extended) 846// To record the result of a less-than comparison with a constant. 847// 848def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>; 849 850// 851// Format: SLTIU rx, immediate MIPS16e 852// Purpose: Set on Less Than Immediate Unsigned (Extended) 853// To record the result of a less-than comparison with a constant. 854// 855def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>; 856 857// 858// Format: SLT rx, ry MIPS16e 859// Purpose: Set on Less Than 860// To record the result of a less-than comparison. 861// 862def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; 863 864def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>; 865 866// Format: SLTU rx, ry MIPS16e 867// Purpose: Set on Less Than Unsigned 868// To record the result of an unsigned less-than comparison. 869// 870def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> { 871 let isCodeGenOnly=1; 872} 873 874 875def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>; 876// 877// Format: SRAV ry, rx MIPS16e 878// Purpose: Shift Word Right Arithmetic Variable 879// To execute an arithmetic right-shift of a word by a variable 880// number of bits. 881// 882def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 883 884 885// 886// Format: SRA rx, ry, sa MIPS16e 887// Purpose: Shift Word Right Arithmetic (Extended) 888// To execute an arithmetic right-shift of a word by a fixed 889// number of bits—1 to 8 bits. 890// 891def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 892 893 894// 895// Format: SRLV ry, rx MIPS16e 896// Purpose: Shift Word Right Logical Variable 897// To execute a logical right-shift of a word by a variable 898// number of bits. 899// 900def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 901 902 903// 904// Format: SRL rx, ry, sa MIPS16e 905// Purpose: Shift Word Right Logical (Extended) 906// To execute a logical right-shift of a word by a fixed 907// number of bits—1 to 31 bits. 908// 909def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 910 911// 912// Format: SUBU rz, rx, ry MIPS16e 913// Purpose: Subtract Unsigned Word 914// To subtract 32-bit integers 915// 916def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 917 918// 919// Format: SW ry, offset(rx) MIPS16e 920// Purpose: Store Word (Extended) 921// To store a word to memory. 922// 923def SwRxRyOffMemX16: 924 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 925 926// 927// Format: SW rx, offset(sp) MIPS16e 928// Purpose: Store Word rx (SP-Relative) 929// To store an SP-relative word to memory. 930// 931def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 932 933// 934// 935// Format: XOR rx, ry MIPS16e 936// Purpose: Xor 937// To do a bitwise logical XOR. 938// 939def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 940 941class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 942 let Predicates = [InMips16Mode]; 943} 944 945// Unary Arith/Logic 946// 947class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 948 Mips16Pat<(OpNode CPU16Regs:$r), 949 (I CPU16Regs:$r)>; 950 951def: ArithLogicU_pat<not, NotRxRy16>; 952def: ArithLogicU_pat<ineg, NegRxRy16>; 953 954class ArithLogic16_pat<SDNode OpNode, Instruction I> : 955 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 956 (I CPU16Regs:$l, CPU16Regs:$r)>; 957 958def: ArithLogic16_pat<add, AdduRxRyRz16>; 959def: ArithLogic16_pat<and, AndRxRxRy16>; 960def: ArithLogic16_pat<mul, MultRxRyRz16>; 961def: ArithLogic16_pat<or, OrRxRxRy16>; 962def: ArithLogic16_pat<sub, SubuRxRyRz16>; 963def: ArithLogic16_pat<xor, XorRxRxRy16>; 964 965// Arithmetic and logical instructions with 2 register operands. 966 967class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 968 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 969 (I CPU16Regs:$in, imm_type:$imm)>; 970 971def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 972def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 973def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 974def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 975 976class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 977 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 978 (I CPU16Regs:$r, CPU16Regs:$ra)>; 979 980def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 981def: shift_rotate_reg16_pat<sra, SravRxRy16>; 982def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 983 984class LoadM16_pat<PatFrag OpNode, Instruction I> : 985 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 986 987def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 988def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 989def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 990def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 991def: LoadM16_pat<load, LwRxRyOffMemX16>; 992 993class StoreM16_pat<PatFrag OpNode, Instruction I> : 994 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 995 (I CPU16Regs:$r, addr16:$addr)>; 996 997def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 998def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 999def: StoreM16_pat<store, SwRxRyOffMemX16>; 1000 1001// Unconditional branch 1002class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1003 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1004 let Predicates = [RelocPIC, InMips16Mode]; 1005 } 1006 1007// Indirect branch 1008def: Mips16Pat< 1009 (brind CPU16Regs:$rs), 1010 (JrcRx16 CPU16Regs:$rs)>; 1011 1012 1013// Jump and Link (Call) 1014let isCall=1, hasDelaySlot=1 in 1015def JumpLinkReg16: 1016 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1017 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1018 1019// Mips16 pseudos 1020let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1021 hasExtraSrcRegAllocReq = 1 in 1022def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1023 1024 1025// setcc patterns 1026 1027class SetCC_R16<PatFrag cond_op, Instruction I>: 1028 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1029 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1030 1031class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1032 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1033 (I CPU16Regs:$rx, imm_type:$imm16)>; 1034 1035 1036def: Mips16Pat<(i32 addr16:$addr), 1037 (AddiuRxRyOffMemX16 addr16:$addr)>; 1038 1039 1040// Large (>16 bit) immediate loads 1041def : Mips16Pat<(i32 imm:$imm), 1042 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1043 (LiRxImmX16 (LO16 imm:$imm)))>; 1044 1045// Carry MipsPatterns 1046def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1047 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1048def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1049 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1050def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1051 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1052 1053// 1054// Some branch conditional patterns are not generated by llvm at this time. 1055// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1056// comparison they are used and for unsigned a different pattern is used. 1057// I am pushing upstream from the full mips16 port and it seemed that I needed 1058// these earlier and the mips32 port has these but now I cannot create test 1059// cases that use these patterns. While I sort this all out I will leave these 1060// extra patterns commented out and if I can be sure they are really not used, 1061// I will delete the code. I don't want to check the code in uncommented without 1062// a valid test case. In some cases, the compiler is generating patterns with 1063// setcc instead and earlier I had implemented setcc first so may have masked 1064// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1065// figure out how to enable the brcond patterns or else possibly new 1066// combinations of of brcond and setcc. 1067// 1068// 1069// bcond-seteq 1070// 1071def: Mips16Pat 1072 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1073 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1074 >; 1075 1076 1077def: Mips16Pat 1078 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1079 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1080 >; 1081 1082def: Mips16Pat 1083 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1084 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1085 >; 1086 1087// 1088// bcond-setgt (do we need to have this pair of setlt, setgt??) 1089// 1090def: Mips16Pat 1091 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1092 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1093 >; 1094 1095// 1096// bcond-setge 1097// 1098def: Mips16Pat 1099 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1100 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1101 >; 1102 1103// 1104// never called because compiler transforms a >= k to a > (k-1) 1105def: Mips16Pat 1106 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1107 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1108 >; 1109 1110// 1111// bcond-setlt 1112// 1113def: Mips16Pat 1114 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1115 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1116 >; 1117 1118def: Mips16Pat 1119 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1120 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1121 >; 1122 1123// 1124// bcond-setle 1125// 1126def: Mips16Pat 1127 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1128 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1129 >; 1130 1131// 1132// bcond-setne 1133// 1134def: Mips16Pat 1135 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1136 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1137 >; 1138 1139def: Mips16Pat 1140 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1141 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1142 >; 1143 1144def: Mips16Pat 1145 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1146 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1147 >; 1148 1149// 1150// This needs to be there but I forget which code will generate it 1151// 1152def: Mips16Pat 1153 <(brcond CPU16Regs:$rx, bb:$targ16), 1154 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1155 >; 1156 1157// 1158 1159// 1160// bcond-setugt 1161// 1162//def: Mips16Pat 1163// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1164// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1165// >; 1166 1167// 1168// bcond-setuge 1169// 1170//def: Mips16Pat 1171// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1172// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1173// >; 1174 1175 1176// 1177// bcond-setult 1178// 1179//def: Mips16Pat 1180// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1181// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1182// >; 1183 1184def: UncondBranch16_pat<br, BimmX16>; 1185 1186// Small immediates 1187def: Mips16Pat<(i32 immSExt16:$in), 1188 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1189 1190def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1191 1192// 1193// MipsDivRem 1194// 1195def: Mips16Pat 1196 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry), 1197 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1198 1199// 1200// MipsDivRemU 1201// 1202def: Mips16Pat 1203 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry), 1204 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1205 1206// signed a,b 1207// x = (a>=b)?x:y 1208// 1209// if !(a < b) x = y 1210// 1211def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1212 CPU16Regs:$x, CPU16Regs:$y), 1213 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1214 CPU16Regs:$a, CPU16Regs:$b)>; 1215 1216// signed a,b 1217// x = (a>b)?x:y 1218// 1219// if (b < a) x = y 1220// 1221def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1222 CPU16Regs:$x, CPU16Regs:$y), 1223 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1224 CPU16Regs:$b, CPU16Regs:$a)>; 1225 1226// unsigned a,b 1227// x = (a>=b)?x:y 1228// 1229// if !(a < b) x = y; 1230// 1231def : Mips16Pat< 1232 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1233 CPU16Regs:$x, CPU16Regs:$y), 1234 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1235 CPU16Regs:$a, CPU16Regs:$b)>; 1236 1237// unsigned a,b 1238// x = (a>b)?x:y 1239// 1240// if (b < a) x = y 1241// 1242def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1243 CPU16Regs:$x, CPU16Regs:$y), 1244 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1245 CPU16Regs:$b, CPU16Regs:$a)>; 1246 1247// signed 1248// x = (a >= k)?x:y 1249// due to an llvm optimization, i don't think that this will ever 1250// be used. This is transformed into x = (a > k-1)?x:y 1251// 1252// 1253 1254//def : Mips16Pat< 1255// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1256// CPU16Regs:$T, CPU16Regs:$F), 1257// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1258// CPU16Regs:$lhs, immSExt16:$rhs)>; 1259 1260//def : Mips16Pat< 1261// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1262// CPU16Regs:$T, CPU16Regs:$F), 1263// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1264// CPU16Regs:$lhs, immSExt16:$rhs)>; 1265 1266// signed 1267// x = (a < k)?x:y 1268// 1269// if !(a < k) x = y; 1270// 1271def : Mips16Pat< 1272 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1273 CPU16Regs:$x, CPU16Regs:$y), 1274 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1275 CPU16Regs:$a, immSExt16:$b)>; 1276 1277 1278// 1279// 1280// signed 1281// x = (a <= b)? x : y 1282// 1283// if (b < a) x = y 1284// 1285def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1286 CPU16Regs:$x, CPU16Regs:$y), 1287 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1288 CPU16Regs:$b, CPU16Regs:$a)>; 1289 1290// 1291// unnsigned 1292// x = (a <= b)? x : y 1293// 1294// if (b < a) x = y 1295// 1296def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1297 CPU16Regs:$x, CPU16Regs:$y), 1298 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1299 CPU16Regs:$b, CPU16Regs:$a)>; 1300 1301// 1302// signed/unsigned 1303// x = (a == b)? x : y 1304// 1305// if (a != b) x = y 1306// 1307def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1308 CPU16Regs:$x, CPU16Regs:$y), 1309 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1310 CPU16Regs:$b, CPU16Regs:$a)>; 1311 1312// 1313// signed/unsigned 1314// x = (a == 0)? x : y 1315// 1316// if (a != 0) x = y 1317// 1318def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1319 CPU16Regs:$x, CPU16Regs:$y), 1320 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1321 CPU16Regs:$a)>; 1322 1323 1324// 1325// signed/unsigned 1326// x = (a == k)? x : y 1327// 1328// if (a != k) x = y 1329// 1330def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1331 CPU16Regs:$x, CPU16Regs:$y), 1332 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1333 CPU16Regs:$a, immZExt16:$k)>; 1334 1335 1336// 1337// signed/unsigned 1338// x = (a != b)? x : y 1339// 1340// if (a == b) x = y 1341// 1342// 1343def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1344 CPU16Regs:$x, CPU16Regs:$y), 1345 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1346 CPU16Regs:$b, CPU16Regs:$a)>; 1347 1348// 1349// signed/unsigned 1350// x = (a != 0)? x : y 1351// 1352// if (a == 0) x = y 1353// 1354def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1355 CPU16Regs:$x, CPU16Regs:$y), 1356 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1357 CPU16Regs:$a)>; 1358 1359// signed/unsigned 1360// x = (a)? x : y 1361// 1362// if (!a) x = y 1363// 1364def : Mips16Pat<(select CPU16Regs:$a, 1365 CPU16Regs:$x, CPU16Regs:$y), 1366 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1367 CPU16Regs:$a)>; 1368 1369 1370// 1371// signed/unsigned 1372// x = (a != k)? x : y 1373// 1374// if (a == k) x = y 1375// 1376def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1377 CPU16Regs:$x, CPU16Regs:$y), 1378 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1379 CPU16Regs:$a, immZExt16:$k)>; 1380 1381// 1382// When writing C code to test setxx these patterns, 1383// some will be transformed into 1384// other things. So we test using C code but using -O3 and -O0 1385// 1386// seteq 1387// 1388def : Mips16Pat 1389 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1390 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1391 1392def : Mips16Pat 1393 <(seteq CPU16Regs:$lhs, 0), 1394 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1395 1396 1397// 1398// setge 1399// 1400 1401def: Mips16Pat 1402 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1403 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1404 (LiRxImmX16 1))>; 1405 1406// 1407// For constants, llvm transforms this to: 1408// x > (k -1) and then reverses the operands to use setlt. So this pattern 1409// is not used now by the compiler. (Presumably checking that k-1 does not 1410// overflow). The compiler never uses this at a the current time, due to 1411// other optimizations. 1412// 1413//def: Mips16Pat 1414// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1415// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1416// (LiRxImmX16 1))>; 1417 1418// This catches the x >= -32768 case by transforming it to x > -32769 1419// 1420def: Mips16Pat 1421 <(setgt CPU16Regs:$lhs, -32769), 1422 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1423 (LiRxImmX16 1))>; 1424 1425// 1426// setgt 1427// 1428// 1429 1430def: Mips16Pat 1431 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1432 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1433 1434// 1435// setle 1436// 1437def: Mips16Pat 1438 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1439 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1440 1441// 1442// setlt 1443// 1444def: SetCC_R16<setlt, SltCCRxRy16>; 1445 1446def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1447 1448// 1449// setne 1450// 1451def : Mips16Pat 1452 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1453 (SltuCCRxRy16 (LiRxImmX16 0), 1454 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1455 1456 1457// 1458// setuge 1459// 1460def: Mips16Pat 1461 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1462 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1463 (LiRxImmX16 1))>; 1464 1465// this pattern will never be used because the compiler will transform 1466// x >= k to x > (k - 1) and then use SLT 1467// 1468//def: Mips16Pat 1469// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1470// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1471// (LiRxImmX16 1))>; 1472 1473// 1474// setugt 1475// 1476def: Mips16Pat 1477 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1478 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1479 1480// 1481// setule 1482// 1483def: Mips16Pat 1484 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1485 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1486 1487// 1488// setult 1489// 1490def: SetCC_R16<setult, SltuCCRxRy16>; 1491 1492def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1493 1494def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1495 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1496 1497// hi/lo relocs 1498 1499def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1500 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1501 1502// wrapper_pic 1503class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1504 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1505 (ADDiuOp RC:$gp, node:$in)>; 1506 1507 1508def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1509def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1510 1511