Mips16InstrInfo.td revision 3ee306cbc0a295409c464ffaad5ef694de8eb09a
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 83551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file describes Mips16 instructions. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)def uimm5 : Operand<i8> { 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) let DecoderMethod= "DecodeSimm16"; 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// RRR-type instruction format 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 273551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// I8_MOV32R instruction format (used only by MOV32R instruction) 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 303551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 313551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// EXT-RI instruction format 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 38 InstrItinClass itin>: 39 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 40 !strconcat(asmstr, asmstr2), [], itin>; 41 42class FEXT_RI16_ins<bits<5> _op, string asmstr, 43 InstrItinClass itin>: 44 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 45 46class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 47 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 48 49// 50// RR-type instruction format 51// 52let rx=0 in 53class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 54 string asmstr, InstrItinClass itin>: 55 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 56 [], itin> ; 57 58// 59// EXT-RRI instruction format 60// 61 62class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 63 InstrItinClass itin>: 64 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 65 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 66 67// 68// EXT-SHIFT instruction format 69// 70class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 71 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa), 72 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 73 74// 75// Address operand 76def mem16 : Operand<i32> { 77 let PrintMethod = "printMemOperand"; 78 let MIOperandInfo = (ops CPU16Regs, simm16); 79 let EncoderMethod = "getMemEncoding"; 80} 81 82// 83// Format: ADDIU rx, pc, immediate MIPS16e 84// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 85// To add a constant to the program counter. 86// 87class AddiuRxPcImmX16_base : FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 88def AddiuRxPcImmX16 : AddiuRxPcImmX16_base; 89// 90// Format: ADDU rz, rx, ry MIPS16e 91// Purpose: Add Unsigned Word (3-Operand) 92// To add 32-bit integers. 93// 94 95class AdduRxRyRz16_base: FRRR16_ins<01, "addu", IIAlu>; 96def AdduRxRyRz16: AdduRxRyRz16_base; 97 98// 99// Format: JR ra MIPS16e 100// Purpose: Jump Register Through Register ra 101// To execute a branch to the instruction address in the return 102// address register. 103// 104 105def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>; 106 107// 108// Format: LI rx, immediate MIPS16e 109// Purpose: Load Immediate (Extended) 110// To load a constant into a GPR. 111// 112def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 113 114// 115// Format: LW ry, offset(rx) MIPS16e 116// Purpose: Load Word (Extended) 117// To load a word from memory as a signed value. 118// 119class LwRxRyOffMemX16_base: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>; 120def LwRxRyOffMemX16: LwRxRyOffMemX16_base; 121 122// 123// Format: MOVE r32, rz MIPS16e 124// Purpose: Move 125// To move the contents of a GPR to a GPR. 126// 127def Mov32R16: FI8_MOV32R16_ins<"move", IIAlu>; 128// 129// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 130// (All args are optional) MIPS16e 131// Purpose: Restore Registers and Deallocate Stack Frame 132// To deallocate a stack frame before exit from a subroutine, 133// restoring return address and static registers, and adjusting 134// stack 135// 136 137// fixed form for restoring RA and the frame 138// for direct object emitter, encoding needs to be adjusted for the 139// frame size 140// 141let ra=1, s=0,s0=0,s1=0 in 142def RestoreRaF16: 143 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 144 "restore \t$$ra, $frame_size", [], IILoad >; 145 146// 147// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 148// MIPS16e 149// Purpose: Save Registers and Set Up Stack Frame 150// To set up a stack frame on entry to a subroutine, 151// saving return address and static registers, and adjusting stack 152// 153let ra=1, s=1,s0=0,s1=0 in 154def SaveRaF16: 155 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 156 "save \t$$ra, $frame_size", [], IILoad >; 157 158// 159// Format: SLL rx, ry, sa MIPS16e 160// Purpose: Shift Word Left Logical (Extended) 161// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 162// 163def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 164 165// 166// Format: SW ry, offset(rx) MIPS16e 167// Purpose: Store Word (Extended) 168// To store a word to memory. 169// 170class SwRxRyOffMemX16_base: FEXT_RRI16_mem_ins<0b11011, "sw", mem16, IIAlu>; 171def SwRxRyOffMemX16: SwRxRyOffMemX16_base; 172 173class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [InMips16Mode]; 175} 176 177class ArithLogicR16Defs<SDNode OpNode, bit isComm = 0> { 178 dag OutOperandList = (outs CPU16Regs:$rz); 179 dag InOperandList = (ins CPU16Regs:$rx, CPU16Regs:$ry); 180 list<dag> Pattern = [(set CPU16Regs:$rz, 181 (OpNode CPU16Regs:$rx, CPU16Regs:$ry))]; 182} 183 184multiclass ArithLogicR16_base { 185 def _add: AdduRxRyRz16_base, ArithLogicR16Defs<add, 1>; 186} 187 188defm ArithLogicR16_patt : ArithLogicR16_base; 189 190class LoadM16Defs<PatFrag OpNode, Operand _MemOpnd, bit Pseudo=0> { 191 bit isPseudo = Pseudo; 192 Operand MemOpnd = _MemOpnd; 193 dag OutOperandList = (outs CPU16Regs:$ry); 194 dag InOperandList = (ins MemOpnd:$addr); 195 list<dag> Pattern = [(set CPU16Regs:$ry, (OpNode addr:$addr))]; 196} 197 198multiclass LoadM16_base { 199 def _LwRxRyOffMemX16: LwRxRyOffMemX16_base, LoadM16Defs<load_a, mem16>; 200} 201 202defm LoadM16: LoadM16_base; 203 204class StoreM16Defs<PatFrag OpNode, Operand _MemOpnd, bit Pseudo=0> { 205 bit isPseudo = Pseudo; 206 Operand MemOpnd = _MemOpnd; 207 dag OutOperandList = (outs ); 208 dag InOperandList = (ins CPU16Regs:$ry, MemOpnd:$addr); 209 list<dag> Pattern = [(OpNode CPU16Regs:$ry, addr:$addr)]; 210} 211 212multiclass StoreM16_base { 213 def _SwRxRyOffMemX16: SwRxRyOffMemX16_base, StoreM16Defs<store_a, mem16>; 214} 215 216defm StoreM16: StoreM16_base; 217 218// Jump and Link (Call) 219let isCall=1, hasDelaySlot=1 in 220def JumpLinkReg16: 221 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 222 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 223 224// Mips16 pseudos 225let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 226 hasExtraSrcRegAllocReq = 1 in 227def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 228 229// As stack alignment is always done with addiu, we need a 16-bit immediate 230// This is basically deprecated code but needs to be there for things 231// to work. 232let Defs = [SP], Uses = [SP] in { 233def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt), 234 ";", 235 [(callseq_start timm:$amt)]>; 236def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), 237 ";", 238 [(callseq_end timm:$amt1, timm:$amt2)]>; 239} 240 241// Small immediates 242def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 243def : Mips16Pat<(MipsLo tglobaladdr:$in), (LiRxImmX16 tglobaladdr:$in)>; 244