Mips16InstrInfo.td revision 50354a3f4a5c9e3689d502a935430f2a57a44af2
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16Regs, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// 36// I8 instruction format 37// 38 39class FI816_ins_base<bits<3> _func, string asmstr, 40 string asmstr2, InstrItinClass itin>: 41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 42 [], itin>; 43 44 45class FI816_SP_ins<bits<3> _func, string asmstr, 46 InstrItinClass itin>: 47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 48 49// 50// RI instruction format 51// 52 53 54class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 55 InstrItinClass itin>: 56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 57 !strconcat(asmstr, asmstr2), [], itin>; 58 59class FRI16_ins<bits<5> op, string asmstr, 60 InstrItinClass itin>: 61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 62 63class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 64 InstrItinClass itin>: 65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 66 !strconcat(asmstr, asmstr2), [], itin>; 67 68class FRI16R_ins<bits<5> op, string asmstr, 69 InstrItinClass itin>: 70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 71 72class F2RI16_ins<bits<5> _op, string asmstr, 73 InstrItinClass itin>: 74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 76 let Constraints = "$rx_ = $rx"; 77} 78 79class FRI16_B_ins<bits<5> _op, string asmstr, 80 InstrItinClass itin>: 81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 83// 84// Compare a register and immediate and place result in CC 85// Implicit use of T8 86// 87// EXT-CCRR Instruction format 88// 89class FEXT_CCRXI16_ins<string asmstr>: 90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 92 let isCodeGenOnly=1; 93} 94 95// JAL and JALX instruction format 96// 97class FJAL16_ins<bits<1> _X, string asmstr, 98 InstrItinClass itin>: 99 FJAL16<_X, (outs), (ins simm20:$imm), 100 !strconcat(asmstr, "\t$imm\n\tnop"),[], 101 itin> { 102 let isCodeGenOnly=1; 103} 104// 105// EXT-I instruction format 106// 107class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 108 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 109 !strconcat(asmstr, "\t$imm16"),[], itin>; 110 111// 112// EXT-I8 instruction format 113// 114 115class FEXT_I816_ins_base<bits<3> _func, string asmstr, 116 string asmstr2, InstrItinClass itin>: 117 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 118 [], itin>; 119 120class FEXT_I816_ins<bits<3> _func, string asmstr, 121 InstrItinClass itin>: 122 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 123 124class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 125 InstrItinClass itin>: 126 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 127 128// 129// Assembler formats in alphabetical order. 130// Natural and pseudos are mixed together. 131// 132// Compare two registers and place result in CC 133// Implicit use of T8 134// 135// CC-RR Instruction format 136// 137class FCCRR16_ins<string asmstr> : 138 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 139 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 140 let isCodeGenOnly=1; 141} 142 143// 144// EXT-RI instruction format 145// 146 147class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 148 InstrItinClass itin>: 149 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 150 !strconcat(asmstr, asmstr2), [], itin>; 151 152class FEXT_RI16_ins<bits<5> _op, string asmstr, 153 InstrItinClass itin>: 154 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 155 156class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 157 InstrItinClass itin>: 158 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 159 !strconcat(asmstr, asmstr2), [], itin>; 160 161class FEXT_RI16R_ins<bits<5> _op, string asmstr, 162 InstrItinClass itin>: 163 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 164 165class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 166 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 167 168class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 169 InstrItinClass itin>: 170 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 171 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 172 173class FEXT_2RI16_ins<bits<5> _op, string asmstr, 174 InstrItinClass itin>: 175 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 176 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 177 let Constraints = "$rx_ = $rx"; 178} 179 180 181// this has an explicit sp argument that we ignore to work around a problem 182// in the compiler 183class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 184 InstrItinClass itin>: 185 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 186 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 187 188// 189// EXT-RRI instruction format 190// 191 192class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 193 InstrItinClass itin>: 194 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 195 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 196 197class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 198 InstrItinClass itin>: 199 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 200 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 201 202// 203// 204// EXT-RRI-A instruction format 205// 206 207class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 208 InstrItinClass itin>: 209 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 210 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 211 212// 213// EXT-SHIFT instruction format 214// 215class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 216 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 217 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 218 219// 220// EXT-T8I8 221// 222class FEXT_T8I816_ins<string asmstr, string asmstr2>: 223 MipsPseudo16<(outs), 224 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 225 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 226 !strconcat(asmstr, "\t$imm"))),[]> { 227 let isCodeGenOnly=1; 228} 229 230// 231// EXT-T8I8I 232// 233class FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 234 MipsPseudo16<(outs), 235 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 236 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 237 !strconcat(asmstr, "\t$targ"))), []> { 238 let isCodeGenOnly=1; 239} 240// 241 242 243// 244// I8_MOVR32 instruction format (used only by the MOVR32 instructio 245// 246class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 247 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 248 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 249 250// 251// I8_MOV32R instruction format (used only by MOV32R instruction) 252// 253 254class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 255 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 256 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 257 258// 259// This are pseudo formats for multiply 260// This first one can be changed to non pseudo now. 261// 262// MULT 263// 264class FMULT16_ins<string asmstr, InstrItinClass itin> : 265 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 266 !strconcat(asmstr, "\t$rx, $ry"), []>; 267 268// 269// MULT-LO 270// 271class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 272 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 273 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 274 let isCodeGenOnly=1; 275} 276 277// 278// RR-type instruction format 279// 280 281class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 282 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 283 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 284} 285 286class FRRTR16_ins<string asmstr> : 287 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 288 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 289 290// 291// maybe refactor but need a $zero as a dummy first parameter 292// 293class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 294 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 295 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 296 297class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 298 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 299 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 300 301 302class FRR16_M_ins<bits<5> f, string asmstr, 303 InstrItinClass itin> : 304 FRR16<f, (outs CPU16Regs:$rx), (ins), 305 !strconcat(asmstr, "\t$rx"), [], itin>; 306 307class FRxRxRy16_ins<bits<5> f, string asmstr, 308 InstrItinClass itin> : 309 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 310 !strconcat(asmstr, "\t$rz, $ry"), 311 [], itin> { 312 let Constraints = "$rx = $rz"; 313} 314 315let rx=0 in 316class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 317 string asmstr, InstrItinClass itin>: 318 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 319 [], itin> ; 320 321 322class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 323 string asmstr, InstrItinClass itin>: 324 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 325 !strconcat(asmstr, "\t $rx"), [], itin> ; 326 327// 328// RRR-type instruction format 329// 330 331class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 332 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 333 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 334 335// 336// These Sel patterns support the generation of conditional move 337// pseudo instructions. 338// 339// The nomenclature uses the components making up the pseudo and may 340// be a bit counter intuitive when compared with the end result we seek. 341// For example using a bqez in the example directly below results in the 342// conditional move being done if the tested register is not zero. 343// I considered in easier to check by keeping the pseudo consistent with 344// it's components but it could have been done differently. 345// 346// The simplest case is when can test and operand directly and do the 347// conditional move based on a simple mips16 conditional 348// branch instruction. 349// for example: 350// if $op == beqz or bnez: 351// 352// $op1 $rt, .+4 353// move $rd, $rs 354// 355// if $op == beqz, then if $rt != 0, then the conditional assignment 356// $rd = $rs is done. 357 358// if $op == bnez, then if $rt == 0, then the conditional assignment 359// $rd = $rs is done. 360// 361// So this pseudo class only has one operand, i.e. op 362// 363class Sel<string op>: 364 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 365 CPU16Regs:$rt), 366 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 367 //let isCodeGenOnly=1; 368 let Constraints = "$rd = $rd_"; 369 let usesCustomInserter = 1; 370} 371 372// 373// The next two instruction classes allow for an operand which tests 374// two operands and returns a value in register T8 and 375//then does a conditional branch based on the value of T8 376// 377 378// op2 can be cmpi or slti/sltiu 379// op1 can bteqz or btnez 380// the operands for op2 are a register and a signed constant 381// 382// $op2 $t, $imm ;test register t and branch conditionally 383// $op1 .+4 ;op1 is a conditional branch 384// move $rd, $rs 385// 386// 387class SeliT<string op1, string op2>: 388 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 389 CPU16Regs:$rl, simm16:$imm), 390 !strconcat(op2, 391 !strconcat("\t$rl, $imm\n\t", 392 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 393 let isCodeGenOnly=1; 394 let Constraints = "$rd = $rd_"; 395 let usesCustomInserter = 1; 396} 397 398// 399// op2 can be cmp or slt/sltu 400// op1 can be bteqz or btnez 401// the operands for op2 are two registers 402// op1 is a conditional branch 403// 404// 405// $op2 $rl, $rr ;test registers rl,rr 406// $op1 .+4 ;op2 is a conditional branch 407// move $rd, $rs 408// 409// 410class SelT<string op1, string op2>: 411 MipsPseudo16<(outs CPU16Regs:$rd_), 412 (ins CPU16Regs:$rd, CPU16Regs:$rs, 413 CPU16Regs:$rl, CPU16Regs:$rr), 414 !strconcat(op2, 415 !strconcat("\t$rl, $rr\n\t", 416 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 417 let isCodeGenOnly=1; 418 let Constraints = "$rd = $rd_"; 419 let usesCustomInserter = 1; 420} 421 422// 423// 32 bit constant 424// 425def imm32: Operand<i32>; 426 427def Constant32: 428 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 429 430def LwConstant32: 431 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm), 432 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 433 434 435// 436// Some general instruction class info 437// 438// 439 440class ArithLogic16Defs<bit isCom=0> { 441 bits<5> shamt = 0; 442 bit isCommutable = isCom; 443 bit isReMaterializable = 1; 444 bit neverHasSideEffects = 1; 445} 446 447class branch16 { 448 bit isBranch = 1; 449 bit isTerminator = 1; 450 bit isBarrier = 1; 451} 452 453class cbranch16 { 454 bit isBranch = 1; 455 bit isTerminator = 1; 456} 457 458class MayLoad { 459 bit mayLoad = 1; 460} 461 462class MayStore { 463 bit mayStore = 1; 464} 465// 466 467 468// Format: ADDIU rx, immediate MIPS16e 469// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 470// To add a constant to a 32-bit integer. 471// 472def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 473 474def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 475 ArithLogic16Defs<0> { 476 let AddedComplexity = 5; 477} 478def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 479 ArithLogic16Defs<0> { 480 let isCodeGenOnly = 1; 481} 482 483def AddiuRxRyOffMemX16: 484 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 485 486// 487 488// Format: ADDIU rx, pc, immediate MIPS16e 489// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 490// To add a constant to the program counter. 491// 492def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 493 494// 495// Format: ADDIU sp, immediate MIPS16e 496// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 497// To add a constant to the stack pointer. 498// 499def AddiuSpImm16 500 : FI816_SP_ins<0b011, "addiu", IIAlu> { 501 let Defs = [SP]; 502 let Uses = [SP]; 503 let AddedComplexity = 5; 504} 505 506def AddiuSpImmX16 507 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 508 let Defs = [SP]; 509 let Uses = [SP]; 510} 511 512// 513// Format: ADDU rz, rx, ry MIPS16e 514// Purpose: Add Unsigned Word (3-Operand) 515// To add 32-bit integers. 516// 517 518def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 519 520// 521// Format: AND rx, ry MIPS16e 522// Purpose: AND 523// To do a bitwise logical AND. 524 525def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 526 527 528// 529// Format: BEQZ rx, offset MIPS16e 530// Purpose: Branch on Equal to Zero 531// To test a GPR then do a PC-relative conditional branch. 532// 533def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 534 535 536// 537// Format: BEQZ rx, offset MIPS16e 538// Purpose: Branch on Equal to Zero (Extended) 539// To test a GPR then do a PC-relative conditional branch. 540// 541def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 542 543// Format: B offset MIPS16e 544// Purpose: Unconditional Branch 545// To do an unconditional PC-relative branch. 546// 547def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 548 549// 550// Format: BNEZ rx, offset MIPS16e 551// Purpose: Branch on Not Equal to Zero 552// To test a GPR then do a PC-relative conditional branch. 553// 554def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 555 556// 557// Format: BNEZ rx, offset MIPS16e 558// Purpose: Branch on Not Equal to Zero (Extended) 559// To test a GPR then do a PC-relative conditional branch. 560// 561def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 562 563// 564// Format: BTEQZ offset MIPS16e 565// Purpose: Branch on T Equal to Zero (Extended) 566// To test special register T then do a PC-relative conditional branch. 567// 568def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 569 let Uses = [T8]; 570} 571 572def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 573 574def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 575 cbranch16; 576 577def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 578 579def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 580 581def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 582 583def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 584 cbranch16; 585 586// 587// Format: BTNEZ offset MIPS16e 588// Purpose: Branch on T Not Equal to Zero (Extended) 589// To test special register T then do a PC-relative conditional branch. 590// 591def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 592 let Uses = [T8]; 593} 594 595def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 596 597def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 598 599def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 600 601def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 602 603def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 604 605def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 606 cbranch16; 607 608// 609// Format: CMP rx, ry MIPS16e 610// Purpose: Compare 611// To compare the contents of two GPRs. 612// 613def CmpRxRy16: FRR16_ins<0b01010, "cmp", IIAlu> { 614 let Defs = [T8]; 615} 616 617// 618// Format: CMPI rx, immediate MIPS16e 619// Purpose: Compare Immediate 620// To compare a constant with the contents of a GPR. 621// 622def CmpiRxImm16: FRI16_ins<0b01110, "cmpi", IIAlu> { 623 let Defs = [T8]; 624} 625 626// 627// Format: CMPI rx, immediate MIPS16e 628// Purpose: Compare Immediate (Extended) 629// To compare a constant with the contents of a GPR. 630// 631def CmpiRxImmX16: FEXT_RI16_ins<0b01110, "cmpi", IIAlu> { 632 let Defs = [T8]; 633} 634 635 636// 637// Format: DIV rx, ry MIPS16e 638// Purpose: Divide Word 639// To divide 32-bit signed integers. 640// 641def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 642 let Defs = [HI, LO]; 643} 644 645// 646// Format: DIVU rx, ry MIPS16e 647// Purpose: Divide Unsigned Word 648// To divide 32-bit unsigned integers. 649// 650def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 651 let Defs = [HI, LO]; 652} 653// 654// Format: JAL target MIPS16e 655// Purpose: Jump and Link 656// To execute a procedure call within the current 256 MB-aligned 657// region and preserve the current ISA. 658// 659 660def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 661 let isBranch = 1; 662 let hasDelaySlot = 0; // not true, but we add the nop for now 663 let isTerminator=1; 664 let isBarrier=1; 665} 666 667// 668// Format: JR ra MIPS16e 669// Purpose: Jump Register Through Register ra 670// To execute a branch to the instruction address in the return 671// address register. 672// 673 674def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 675 let isBranch = 1; 676 let isIndirectBranch = 1; 677 let hasDelaySlot = 1; 678 let isTerminator=1; 679 let isBarrier=1; 680} 681 682def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 683 let isBranch = 1; 684 let isIndirectBranch = 1; 685 let isTerminator=1; 686 let isBarrier=1; 687} 688 689def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 690 let isBranch = 1; 691 let isIndirectBranch = 1; 692 let isTerminator=1; 693 let isBarrier=1; 694} 695// 696// Format: LB ry, offset(rx) MIPS16e 697// Purpose: Load Byte (Extended) 698// To load a byte from memory as a signed value. 699// 700def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 701 let isCodeGenOnly = 1; 702} 703 704// 705// Format: LBU ry, offset(rx) MIPS16e 706// Purpose: Load Byte Unsigned (Extended) 707// To load a byte from memory as a unsigned value. 708// 709def LbuRxRyOffMemX16: 710 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 711 let isCodeGenOnly = 1; 712} 713 714// 715// Format: LH ry, offset(rx) MIPS16e 716// Purpose: Load Halfword signed (Extended) 717// To load a halfword from memory as a signed value. 718// 719def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 720 let isCodeGenOnly = 1; 721} 722 723// 724// Format: LHU ry, offset(rx) MIPS16e 725// Purpose: Load Halfword unsigned (Extended) 726// To load a halfword from memory as an unsigned value. 727// 728def LhuRxRyOffMemX16: 729 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 730 let isCodeGenOnly = 1; 731} 732 733// 734// Format: LI rx, immediate MIPS16e 735// Purpose: Load Immediate 736// To load a constant into a GPR. 737// 738def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 739 740// 741// Format: LI rx, immediate MIPS16e 742// Purpose: Load Immediate (Extended) 743// To load a constant into a GPR. 744// 745def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 746 747// 748// Format: LW ry, offset(rx) MIPS16e 749// Purpose: Load Word (Extended) 750// To load a word from memory as a signed value. 751// 752def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 753 let isCodeGenOnly = 1; 754} 755 756// Format: LW rx, offset(sp) MIPS16e 757// Purpose: Load Word (SP-Relative, Extended) 758// To load an SP-relative word from memory as a signed value. 759// 760def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{ 761 let Uses = [SP]; 762} 763 764// 765// Format: MOVE r32, rz MIPS16e 766// Purpose: Move 767// To move the contents of a GPR to a GPR. 768// 769def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 770 771// 772// Format: MOVE ry, r32 MIPS16e 773//Purpose: Move 774// To move the contents of a GPR to a GPR. 775// 776def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 777 778// 779// Format: MFHI rx MIPS16e 780// Purpose: Move From HI Register 781// To copy the special purpose HI register to a GPR. 782// 783def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 784 let Uses = [HI]; 785 let neverHasSideEffects = 1; 786} 787 788// 789// Format: MFLO rx MIPS16e 790// Purpose: Move From LO Register 791// To copy the special purpose LO register to a GPR. 792// 793def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 794 let Uses = [LO]; 795 let neverHasSideEffects = 1; 796} 797 798// 799// Pseudo Instruction for mult 800// 801def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 802 let isCommutable = 1; 803 let neverHasSideEffects = 1; 804 let Defs = [HI, LO]; 805} 806 807def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 808 let isCommutable = 1; 809 let neverHasSideEffects = 1; 810 let Defs = [HI, LO]; 811} 812 813// 814// Format: MULT rx, ry MIPS16e 815// Purpose: Multiply Word 816// To multiply 32-bit signed integers. 817// 818def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 819 let isCommutable = 1; 820 let neverHasSideEffects = 1; 821 let Defs = [HI, LO]; 822} 823 824// 825// Format: MULTU rx, ry MIPS16e 826// Purpose: Multiply Unsigned Word 827// To multiply 32-bit unsigned integers. 828// 829def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 830 let isCommutable = 1; 831 let neverHasSideEffects = 1; 832 let Defs = [HI, LO]; 833} 834 835// 836// Format: NEG rx, ry MIPS16e 837// Purpose: Negate 838// To negate an integer value. 839// 840def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 841 842// 843// Format: NOT rx, ry MIPS16e 844// Purpose: Not 845// To complement an integer value 846// 847def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 848 849// 850// Format: OR rx, ry MIPS16e 851// Purpose: Or 852// To do a bitwise logical OR. 853// 854def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 855 856// 857// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 858// (All args are optional) MIPS16e 859// Purpose: Restore Registers and Deallocate Stack Frame 860// To deallocate a stack frame before exit from a subroutine, 861// restoring return address and static registers, and adjusting 862// stack 863// 864 865// fixed form for restoring RA and the frame 866// for direct object emitter, encoding needs to be adjusted for the 867// frame size 868// 869let ra=1, s=0,s0=1,s1=1 in 870def RestoreRaF16: 871 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 872 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 873 let isCodeGenOnly = 1; 874 let Defs = [S0, S1, RA, SP]; 875 let Uses = [SP]; 876} 877 878// Use Restore to increment SP since SP is not a Mip 16 register, this 879// is an easy way to do that which does not require a register. 880// 881let ra=0, s=0,s0=0,s1=0 in 882def RestoreIncSpF16: 883 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 884 "restore\t$frame_size", [], IILoad >, MayLoad { 885 let isCodeGenOnly = 1; 886 let Defs = [SP]; 887 let Uses = [SP]; 888} 889 890// 891// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 892// MIPS16e 893// Purpose: Save Registers and Set Up Stack Frame 894// To set up a stack frame on entry to a subroutine, 895// saving return address and static registers, and adjusting stack 896// 897let ra=1, s=1,s0=1,s1=1 in 898def SaveRaF16: 899 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 900 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 901 let isCodeGenOnly = 1; 902 let Uses = [RA, SP, S0, S1]; 903 let Defs = [SP]; 904} 905 906// 907// Use Save to decrement the SP by a constant since SP is not 908// a Mips16 register. 909// 910let ra=0, s=0,s0=0,s1=0 in 911def SaveDecSpF16: 912 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 913 "save\t$frame_size", [], IIStore >, MayStore { 914 let isCodeGenOnly = 1; 915 let Uses = [SP]; 916 let Defs = [SP]; 917} 918// 919// Format: SB ry, offset(rx) MIPS16e 920// Purpose: Store Byte (Extended) 921// To store a byte to memory. 922// 923def SbRxRyOffMemX16: 924 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 925 926// 927// The Sel(T) instructions are pseudos 928// T means that they use T8 implicitly. 929// 930// 931// Format: SelBeqZ rd, rs, rt 932// Purpose: if rt==0, do nothing 933// else rs = rt 934// 935def SelBeqZ: Sel<"beqz">; 936 937// 938// Format: SelTBteqZCmp rd, rs, rl, rr 939// Purpose: b = Cmp rl, rr. 940// If b==0 then do nothing. 941// if b!=0 then rd = rs 942// 943def SelTBteqZCmp: SelT<"bteqz", "cmp">; 944 945// 946// Format: SelTBteqZCmpi rd, rs, rl, rr 947// Purpose: b = Cmpi rl, imm. 948// If b==0 then do nothing. 949// if b!=0 then rd = rs 950// 951def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 952 953// 954// Format: SelTBteqZSlt rd, rs, rl, rr 955// Purpose: b = Slt rl, rr. 956// If b==0 then do nothing. 957// if b!=0 then rd = rs 958// 959def SelTBteqZSlt: SelT<"bteqz", "slt">; 960 961// 962// Format: SelTBteqZSlti rd, rs, rl, rr 963// Purpose: b = Slti rl, imm. 964// If b==0 then do nothing. 965// if b!=0 then rd = rs 966// 967def SelTBteqZSlti: SeliT<"bteqz", "slti">; 968 969// 970// Format: SelTBteqZSltu rd, rs, rl, rr 971// Purpose: b = Sltu rl, rr. 972// If b==0 then do nothing. 973// if b!=0 then rd = rs 974// 975def SelTBteqZSltu: SelT<"bteqz", "sltu">; 976 977// 978// Format: SelTBteqZSltiu rd, rs, rl, rr 979// Purpose: b = Sltiu rl, imm. 980// If b==0 then do nothing. 981// if b!=0 then rd = rs 982// 983def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 984 985// 986// Format: SelBnez rd, rs, rt 987// Purpose: if rt!=0, do nothing 988// else rs = rt 989// 990def SelBneZ: Sel<"bnez">; 991 992// 993// Format: SelTBtneZCmp rd, rs, rl, rr 994// Purpose: b = Cmp rl, rr. 995// If b!=0 then do nothing. 996// if b0=0 then rd = rs 997// 998def SelTBtneZCmp: SelT<"btnez", "cmp">; 999 1000// 1001// Format: SelTBtnezCmpi rd, rs, rl, rr 1002// Purpose: b = Cmpi rl, imm. 1003// If b!=0 then do nothing. 1004// if b==0 then rd = rs 1005// 1006def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1007 1008// 1009// Format: SelTBtneZSlt rd, rs, rl, rr 1010// Purpose: b = Slt rl, rr. 1011// If b!=0 then do nothing. 1012// if b==0 then rd = rs 1013// 1014def SelTBtneZSlt: SelT<"btnez", "slt">; 1015 1016// 1017// Format: SelTBtneZSlti rd, rs, rl, rr 1018// Purpose: b = Slti rl, imm. 1019// If b!=0 then do nothing. 1020// if b==0 then rd = rs 1021// 1022def SelTBtneZSlti: SeliT<"btnez", "slti">; 1023 1024// 1025// Format: SelTBtneZSltu rd, rs, rl, rr 1026// Purpose: b = Sltu rl, rr. 1027// If b!=0 then do nothing. 1028// if b==0 then rd = rs 1029// 1030def SelTBtneZSltu: SelT<"btnez", "sltu">; 1031 1032// 1033// Format: SelTBtneZSltiu rd, rs, rl, rr 1034// Purpose: b = Slti rl, imm. 1035// If b!=0 then do nothing. 1036// if b==0 then rd = rs 1037// 1038def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1039// 1040// 1041// Format: SH ry, offset(rx) MIPS16e 1042// Purpose: Store Halfword (Extended) 1043// To store a halfword to memory. 1044// 1045def ShRxRyOffMemX16: 1046 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1047 1048// 1049// Format: SLL rx, ry, sa MIPS16e 1050// Purpose: Shift Word Left Logical (Extended) 1051// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 1052// 1053def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1054 1055// 1056// Format: SLLV ry, rx MIPS16e 1057// Purpose: Shift Word Left Logical Variable 1058// To execute a left-shift of a word by a variable number of bits. 1059// 1060def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1061 1062// Format: SLTI rx, immediate MIPS16e 1063// Purpose: Set on Less Than Immediate 1064// To record the result of a less-than comparison with a constant. 1065// 1066// 1067def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1068 let Defs = [T8]; 1069} 1070 1071// 1072// Format: SLTI rx, immediate MIPS16e 1073// Purpose: Set on Less Than Immediate (Extended) 1074// To record the result of a less-than comparison with a constant. 1075// 1076// 1077def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1078 let Defs = [T8]; 1079} 1080 1081def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1082 1083// Format: SLTIU rx, immediate MIPS16e 1084// Purpose: Set on Less Than Immediate Unsigned 1085// To record the result of a less-than comparison with a constant. 1086// 1087// 1088def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1089 let Defs = [T8]; 1090} 1091 1092// 1093// Format: SLTI rx, immediate MIPS16e 1094// Purpose: Set on Less Than Immediate Unsigned (Extended) 1095// To record the result of a less-than comparison with a constant. 1096// 1097// 1098def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1099 let Defs = [T8]; 1100} 1101// 1102// Format: SLTIU rx, immediate MIPS16e 1103// Purpose: Set on Less Than Immediate Unsigned (Extended) 1104// To record the result of a less-than comparison with a constant. 1105// 1106def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1107 1108// 1109// Format: SLT rx, ry MIPS16e 1110// Purpose: Set on Less Than 1111// To record the result of a less-than comparison. 1112// 1113def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>{ 1114 let Defs = [T8]; 1115} 1116 1117def SltCCRxRy16: FCCRR16_ins<"slt">; 1118 1119// Format: SLTU rx, ry MIPS16e 1120// Purpose: Set on Less Than Unsigned 1121// To record the result of an unsigned less-than comparison. 1122// 1123def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>{ 1124 let Defs = [T8]; 1125} 1126 1127def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1128 let isCodeGenOnly=1; 1129 let Defs = [T8]; 1130} 1131 1132 1133def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1134// 1135// Format: SRAV ry, rx MIPS16e 1136// Purpose: Shift Word Right Arithmetic Variable 1137// To execute an arithmetic right-shift of a word by a variable 1138// number of bits. 1139// 1140def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1141 1142 1143// 1144// Format: SRA rx, ry, sa MIPS16e 1145// Purpose: Shift Word Right Arithmetic (Extended) 1146// To execute an arithmetic right-shift of a word by a fixed 1147// number of bits—1 to 8 bits. 1148// 1149def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1150 1151 1152// 1153// Format: SRLV ry, rx MIPS16e 1154// Purpose: Shift Word Right Logical Variable 1155// To execute a logical right-shift of a word by a variable 1156// number of bits. 1157// 1158def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1159 1160 1161// 1162// Format: SRL rx, ry, sa MIPS16e 1163// Purpose: Shift Word Right Logical (Extended) 1164// To execute a logical right-shift of a word by a fixed 1165// number of bits—1 to 31 bits. 1166// 1167def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1168 1169// 1170// Format: SUBU rz, rx, ry MIPS16e 1171// Purpose: Subtract Unsigned Word 1172// To subtract 32-bit integers 1173// 1174def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1175 1176// 1177// Format: SW ry, offset(rx) MIPS16e 1178// Purpose: Store Word (Extended) 1179// To store a word to memory. 1180// 1181def SwRxRyOffMemX16: 1182 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1183 1184// 1185// Format: SW rx, offset(sp) MIPS16e 1186// Purpose: Store Word rx (SP-Relative) 1187// To store an SP-relative word to memory. 1188// 1189def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 1190 1191// 1192// 1193// Format: XOR rx, ry MIPS16e 1194// Purpose: Xor 1195// To do a bitwise logical XOR. 1196// 1197def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1198 1199class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1200 let Predicates = [InMips16Mode]; 1201} 1202 1203// Unary Arith/Logic 1204// 1205class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1206 Mips16Pat<(OpNode CPU16Regs:$r), 1207 (I CPU16Regs:$r)>; 1208 1209def: ArithLogicU_pat<not, NotRxRy16>; 1210def: ArithLogicU_pat<ineg, NegRxRy16>; 1211 1212class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1213 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1214 (I CPU16Regs:$l, CPU16Regs:$r)>; 1215 1216def: ArithLogic16_pat<add, AdduRxRyRz16>; 1217def: ArithLogic16_pat<and, AndRxRxRy16>; 1218def: ArithLogic16_pat<mul, MultRxRyRz16>; 1219def: ArithLogic16_pat<or, OrRxRxRy16>; 1220def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1221def: ArithLogic16_pat<xor, XorRxRxRy16>; 1222 1223// Arithmetic and logical instructions with 2 register operands. 1224 1225class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1226 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1227 (I CPU16Regs:$in, imm_type:$imm)>; 1228 1229def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1230def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1231def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1232def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1233def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1234 1235class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1236 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1237 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1238 1239def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1240def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1241def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1242 1243class LoadM16_pat<PatFrag OpNode, Instruction I> : 1244 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1245 1246def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1247def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1248def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1249def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1250def: LoadM16_pat<load, LwRxRyOffMemX16>; 1251 1252class StoreM16_pat<PatFrag OpNode, Instruction I> : 1253 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1254 (I CPU16Regs:$r, addr16:$addr)>; 1255 1256def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1257def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1258def: StoreM16_pat<store, SwRxRyOffMemX16>; 1259 1260// Unconditional branch 1261class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1262 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1263 let Predicates = [InMips16Mode]; 1264 } 1265 1266def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1267 (Jal16 tglobaladdr:$dst)>; 1268 1269def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1270 (Jal16 texternalsym:$dst)>; 1271 1272// Indirect branch 1273def: Mips16Pat< 1274 (brind CPU16Regs:$rs), 1275 (JrcRx16 CPU16Regs:$rs)>; 1276 1277// Jump and Link (Call) 1278let isCall=1, hasDelaySlot=0 in 1279def JumpLinkReg16: 1280 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1281 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1282 1283// Mips16 pseudos 1284let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1285 hasExtraSrcRegAllocReq = 1 in 1286def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1287 1288 1289// setcc patterns 1290 1291class SetCC_R16<PatFrag cond_op, Instruction I>: 1292 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1293 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1294 1295class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1296 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1297 (I CPU16Regs:$rx, imm_type:$imm16)>; 1298 1299 1300def: Mips16Pat<(i32 addr16:$addr), 1301 (AddiuRxRyOffMemX16 addr16:$addr)>; 1302 1303 1304// Large (>16 bit) immediate loads 1305def : Mips16Pat<(i32 imm:$imm), 1306 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1307 (LiRxImmX16 (LO16 imm:$imm)))>; 1308 1309// Carry MipsPatterns 1310def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1311 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1312def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1313 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1314def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1315 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1316 1317// 1318// Some branch conditional patterns are not generated by llvm at this time. 1319// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1320// comparison they are used and for unsigned a different pattern is used. 1321// I am pushing upstream from the full mips16 port and it seemed that I needed 1322// these earlier and the mips32 port has these but now I cannot create test 1323// cases that use these patterns. While I sort this all out I will leave these 1324// extra patterns commented out and if I can be sure they are really not used, 1325// I will delete the code. I don't want to check the code in uncommented without 1326// a valid test case. In some cases, the compiler is generating patterns with 1327// setcc instead and earlier I had implemented setcc first so may have masked 1328// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1329// figure out how to enable the brcond patterns or else possibly new 1330// combinations of of brcond and setcc. 1331// 1332// 1333// bcond-seteq 1334// 1335def: Mips16Pat 1336 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1337 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1338 >; 1339 1340 1341def: Mips16Pat 1342 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1343 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1344 >; 1345 1346def: Mips16Pat 1347 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1348 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1349 >; 1350 1351// 1352// bcond-setgt (do we need to have this pair of setlt, setgt??) 1353// 1354def: Mips16Pat 1355 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1356 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1357 >; 1358 1359// 1360// bcond-setge 1361// 1362def: Mips16Pat 1363 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1364 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1365 >; 1366 1367// 1368// never called because compiler transforms a >= k to a > (k-1) 1369def: Mips16Pat 1370 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1371 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1372 >; 1373 1374// 1375// bcond-setlt 1376// 1377def: Mips16Pat 1378 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1379 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1380 >; 1381 1382def: Mips16Pat 1383 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1384 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1385 >; 1386 1387// 1388// bcond-setle 1389// 1390def: Mips16Pat 1391 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1392 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1393 >; 1394 1395// 1396// bcond-setne 1397// 1398def: Mips16Pat 1399 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1400 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1401 >; 1402 1403def: Mips16Pat 1404 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1405 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1406 >; 1407 1408def: Mips16Pat 1409 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1410 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1411 >; 1412 1413// 1414// This needs to be there but I forget which code will generate it 1415// 1416def: Mips16Pat 1417 <(brcond CPU16Regs:$rx, bb:$targ16), 1418 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1419 >; 1420 1421// 1422 1423// 1424// bcond-setugt 1425// 1426//def: Mips16Pat 1427// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1428// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1429// >; 1430 1431// 1432// bcond-setuge 1433// 1434//def: Mips16Pat 1435// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1436// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1437// >; 1438 1439 1440// 1441// bcond-setult 1442// 1443//def: Mips16Pat 1444// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1445// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1446// >; 1447 1448def: UncondBranch16_pat<br, BimmX16>; 1449 1450// Small immediates 1451def: Mips16Pat<(i32 immSExt16:$in), 1452 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1453 1454def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1455 1456// 1457// MipsDivRem 1458// 1459def: Mips16Pat 1460 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry), 1461 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1462 1463// 1464// MipsDivRemU 1465// 1466def: Mips16Pat 1467 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry), 1468 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1469 1470// signed a,b 1471// x = (a>=b)?x:y 1472// 1473// if !(a < b) x = y 1474// 1475def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1476 CPU16Regs:$x, CPU16Regs:$y), 1477 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1478 CPU16Regs:$a, CPU16Regs:$b)>; 1479 1480// signed a,b 1481// x = (a>b)?x:y 1482// 1483// if (b < a) x = y 1484// 1485def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1486 CPU16Regs:$x, CPU16Regs:$y), 1487 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1488 CPU16Regs:$b, CPU16Regs:$a)>; 1489 1490// unsigned a,b 1491// x = (a>=b)?x:y 1492// 1493// if !(a < b) x = y; 1494// 1495def : Mips16Pat< 1496 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1497 CPU16Regs:$x, CPU16Regs:$y), 1498 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1499 CPU16Regs:$a, CPU16Regs:$b)>; 1500 1501// unsigned a,b 1502// x = (a>b)?x:y 1503// 1504// if (b < a) x = y 1505// 1506def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1507 CPU16Regs:$x, CPU16Regs:$y), 1508 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1509 CPU16Regs:$b, CPU16Regs:$a)>; 1510 1511// signed 1512// x = (a >= k)?x:y 1513// due to an llvm optimization, i don't think that this will ever 1514// be used. This is transformed into x = (a > k-1)?x:y 1515// 1516// 1517 1518//def : Mips16Pat< 1519// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1520// CPU16Regs:$T, CPU16Regs:$F), 1521// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1522// CPU16Regs:$lhs, immSExt16:$rhs)>; 1523 1524//def : Mips16Pat< 1525// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1526// CPU16Regs:$T, CPU16Regs:$F), 1527// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1528// CPU16Regs:$lhs, immSExt16:$rhs)>; 1529 1530// signed 1531// x = (a < k)?x:y 1532// 1533// if !(a < k) x = y; 1534// 1535def : Mips16Pat< 1536 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1537 CPU16Regs:$x, CPU16Regs:$y), 1538 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1539 CPU16Regs:$a, immSExt16:$b)>; 1540 1541 1542// 1543// 1544// signed 1545// x = (a <= b)? x : y 1546// 1547// if (b < a) x = y 1548// 1549def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1550 CPU16Regs:$x, CPU16Regs:$y), 1551 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1552 CPU16Regs:$b, CPU16Regs:$a)>; 1553 1554// 1555// unnsigned 1556// x = (a <= b)? x : y 1557// 1558// if (b < a) x = y 1559// 1560def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1561 CPU16Regs:$x, CPU16Regs:$y), 1562 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1563 CPU16Regs:$b, CPU16Regs:$a)>; 1564 1565// 1566// signed/unsigned 1567// x = (a == b)? x : y 1568// 1569// if (a != b) x = y 1570// 1571def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1572 CPU16Regs:$x, CPU16Regs:$y), 1573 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1574 CPU16Regs:$b, CPU16Regs:$a)>; 1575 1576// 1577// signed/unsigned 1578// x = (a == 0)? x : y 1579// 1580// if (a != 0) x = y 1581// 1582def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1583 CPU16Regs:$x, CPU16Regs:$y), 1584 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1585 CPU16Regs:$a)>; 1586 1587 1588// 1589// signed/unsigned 1590// x = (a == k)? x : y 1591// 1592// if (a != k) x = y 1593// 1594def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1595 CPU16Regs:$x, CPU16Regs:$y), 1596 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1597 CPU16Regs:$a, immZExt16:$k)>; 1598 1599 1600// 1601// signed/unsigned 1602// x = (a != b)? x : y 1603// 1604// if (a == b) x = y 1605// 1606// 1607def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1608 CPU16Regs:$x, CPU16Regs:$y), 1609 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1610 CPU16Regs:$b, CPU16Regs:$a)>; 1611 1612// 1613// signed/unsigned 1614// x = (a != 0)? x : y 1615// 1616// if (a == 0) x = y 1617// 1618def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1619 CPU16Regs:$x, CPU16Regs:$y), 1620 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1621 CPU16Regs:$a)>; 1622 1623// signed/unsigned 1624// x = (a)? x : y 1625// 1626// if (!a) x = y 1627// 1628def : Mips16Pat<(select CPU16Regs:$a, 1629 CPU16Regs:$x, CPU16Regs:$y), 1630 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1631 CPU16Regs:$a)>; 1632 1633 1634// 1635// signed/unsigned 1636// x = (a != k)? x : y 1637// 1638// if (a == k) x = y 1639// 1640def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1641 CPU16Regs:$x, CPU16Regs:$y), 1642 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1643 CPU16Regs:$a, immZExt16:$k)>; 1644 1645// 1646// When writing C code to test setxx these patterns, 1647// some will be transformed into 1648// other things. So we test using C code but using -O3 and -O0 1649// 1650// seteq 1651// 1652def : Mips16Pat 1653 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1654 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1655 1656def : Mips16Pat 1657 <(seteq CPU16Regs:$lhs, 0), 1658 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1659 1660 1661// 1662// setge 1663// 1664 1665def: Mips16Pat 1666 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1667 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1668 (LiRxImmX16 1))>; 1669 1670// 1671// For constants, llvm transforms this to: 1672// x > (k -1) and then reverses the operands to use setlt. So this pattern 1673// is not used now by the compiler. (Presumably checking that k-1 does not 1674// overflow). The compiler never uses this at a the current time, due to 1675// other optimizations. 1676// 1677//def: Mips16Pat 1678// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1679// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1680// (LiRxImmX16 1))>; 1681 1682// This catches the x >= -32768 case by transforming it to x > -32769 1683// 1684def: Mips16Pat 1685 <(setgt CPU16Regs:$lhs, -32769), 1686 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1687 (LiRxImmX16 1))>; 1688 1689// 1690// setgt 1691// 1692// 1693 1694def: Mips16Pat 1695 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1696 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1697 1698// 1699// setle 1700// 1701def: Mips16Pat 1702 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1703 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1704 1705// 1706// setlt 1707// 1708def: SetCC_R16<setlt, SltCCRxRy16>; 1709 1710def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1711 1712// 1713// setne 1714// 1715def : Mips16Pat 1716 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1717 (SltuCCRxRy16 (LiRxImmX16 0), 1718 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1719 1720 1721// 1722// setuge 1723// 1724def: Mips16Pat 1725 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1726 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1727 (LiRxImmX16 1))>; 1728 1729// this pattern will never be used because the compiler will transform 1730// x >= k to x > (k - 1) and then use SLT 1731// 1732//def: Mips16Pat 1733// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1734// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1735// (LiRxImmX16 1))>; 1736 1737// 1738// setugt 1739// 1740def: Mips16Pat 1741 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1742 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1743 1744// 1745// setule 1746// 1747def: Mips16Pat 1748 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1749 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1750 1751// 1752// setult 1753// 1754def: SetCC_R16<setult, SltuCCRxRy16>; 1755 1756def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1757 1758def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1759 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1760 1761// hi/lo relocs 1762 1763def : Mips16Pat<(MipsHi tglobaladdr:$in), 1764 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1765def : Mips16Pat<(MipsHi tjumptable:$in), 1766 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1767def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1768 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1769 1770// wrapper_pic 1771class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1772 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1773 (ADDiuOp RC:$gp, node:$in)>; 1774 1775 1776def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1777def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1778 1779def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1780 (LbuRxRyOffMemX16 addr16:$src)>; 1781def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1782 (LhuRxRyOffMemX16 addr16:$src)>; 1783