Mips16InstrInfo.td revision 51c9043f3bc215bb3026486e5e1ef5989a8d8d8b
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// 36// I8 instruction format 37// 38 39class FI816_ins_base<bits<3> _func, string asmstr, 40 string asmstr2, InstrItinClass itin>: 41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 42 [], itin>; 43 44 45class FI816_SP_ins<bits<3> _func, string asmstr, 46 InstrItinClass itin>: 47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 48 49// 50// RI instruction format 51// 52 53 54class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 55 InstrItinClass itin>: 56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 57 !strconcat(asmstr, asmstr2), [], itin>; 58 59class FRI16_ins<bits<5> op, string asmstr, 60 InstrItinClass itin>: 61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 62 63class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 64 InstrItinClass itin>: 65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 66 !strconcat(asmstr, asmstr2), [], itin>; 67 68class FRI16R_ins<bits<5> op, string asmstr, 69 InstrItinClass itin>: 70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 71 72class F2RI16_ins<bits<5> _op, string asmstr, 73 InstrItinClass itin>: 74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 76 let Constraints = "$rx_ = $rx"; 77} 78 79class FRI16_B_ins<bits<5> _op, string asmstr, 80 InstrItinClass itin>: 81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 83// 84// Compare a register and immediate and place result in CC 85// Implicit use of T8 86// 87// EXT-CCRR Instruction format 88// 89class FEXT_CCRXI16_ins<string asmstr>: 90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 92 let isCodeGenOnly=1; 93 let usesCustomInserter = 1; 94} 95 96// JAL and JALX instruction format 97// 98class FJAL16_ins<bits<1> _X, string asmstr, 99 InstrItinClass itin>: 100 FJAL16<_X, (outs), (ins simm20:$imm), 101 !strconcat(asmstr, "\t$imm\n\tnop"),[], 102 itin> { 103 let isCodeGenOnly=1; 104} 105// 106// EXT-I instruction format 107// 108class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 109 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 110 !strconcat(asmstr, "\t$imm16"),[], itin>; 111 112// 113// EXT-I8 instruction format 114// 115 116class FEXT_I816_ins_base<bits<3> _func, string asmstr, 117 string asmstr2, InstrItinClass itin>: 118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 119 [], itin>; 120 121class FEXT_I816_ins<bits<3> _func, string asmstr, 122 InstrItinClass itin>: 123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 124 125class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 126 InstrItinClass itin>: 127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 128 129// 130// Assembler formats in alphabetical order. 131// Natural and pseudos are mixed together. 132// 133// Compare two registers and place result in CC 134// Implicit use of T8 135// 136// CC-RR Instruction format 137// 138class FCCRR16_ins<string asmstr> : 139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 141 let isCodeGenOnly=1; 142 let usesCustomInserter = 1; 143} 144 145// 146// EXT-RI instruction format 147// 148 149class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 150 InstrItinClass itin>: 151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 152 !strconcat(asmstr, asmstr2), [], itin>; 153 154class FEXT_RI16_ins<bits<5> _op, string asmstr, 155 InstrItinClass itin>: 156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 157 158class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 159 InstrItinClass itin>: 160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 161 !strconcat(asmstr, asmstr2), [], itin>; 162 163class FEXT_RI16R_ins<bits<5> _op, string asmstr, 164 InstrItinClass itin>: 165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 166 167class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 169 170class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 171 InstrItinClass itin>: 172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 174 175class FEXT_2RI16_ins<bits<5> _op, string asmstr, 176 InstrItinClass itin>: 177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 179 let Constraints = "$rx_ = $rx"; 180} 181 182 183// this has an explicit sp argument that we ignore to work around a problem 184// in the compiler 185class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 186 InstrItinClass itin>: 187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 189 190class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr, 191 InstrItinClass itin>: 192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm), 193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 194 195// 196// EXT-RRI instruction format 197// 198 199class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 200 InstrItinClass itin>: 201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 203 204class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 205 InstrItinClass itin>: 206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 208 209// 210// 211// EXT-RRI-A instruction format 212// 213 214class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 215 InstrItinClass itin>: 216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 218 219// 220// EXT-SHIFT instruction format 221// 222class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 225 226// 227// EXT-T8I8 228// 229class FEXT_T8I816_ins<string asmstr, string asmstr2>: 230 MipsPseudo16<(outs), 231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 233 !strconcat(asmstr, "\t$imm"))),[]> { 234 let isCodeGenOnly=1; 235 let usesCustomInserter = 1; 236} 237 238// 239// EXT-T8I8I 240// 241class FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 242 MipsPseudo16<(outs), 243 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 244 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 245 !strconcat(asmstr, "\t$targ"))), []> { 246 let isCodeGenOnly=1; 247 let usesCustomInserter = 1; 248} 249// 250 251 252// 253// I8_MOVR32 instruction format (used only by the MOVR32 instructio 254// 255class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 256 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32), 257 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 258 259// 260// I8_MOV32R instruction format (used only by MOV32R instruction) 261// 262 263class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 264 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz), 265 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 266 267// 268// This are pseudo formats for multiply 269// This first one can be changed to non pseudo now. 270// 271// MULT 272// 273class FMULT16_ins<string asmstr, InstrItinClass itin> : 274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 275 !strconcat(asmstr, "\t$rx, $ry"), []>; 276 277// 278// MULT-LO 279// 280class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 283 let isCodeGenOnly=1; 284} 285 286// 287// RR-type instruction format 288// 289 290class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 293} 294 295class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> : 296 FRRBreak16<(outs), (ins), asmstr, [], itin> { 297 let Code=0; 298} 299 300class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : 301 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 302 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 303} 304 305class FRRTR16_ins<string asmstr> : 306 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 307 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 308 309// 310// maybe refactor but need a $zero as a dummy first parameter 311// 312class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 313 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 314 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 315 316class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 317 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 318 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 319 320 321class FRR16_M_ins<bits<5> f, string asmstr, 322 InstrItinClass itin> : 323 FRR16<f, (outs CPU16Regs:$rx), (ins), 324 !strconcat(asmstr, "\t$rx"), [], itin>; 325 326class FRxRxRy16_ins<bits<5> f, string asmstr, 327 InstrItinClass itin> : 328 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 329 !strconcat(asmstr, "\t$rz, $ry"), 330 [], itin> { 331 let Constraints = "$rx = $rz"; 332} 333 334let rx=0 in 335class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 336 string asmstr, InstrItinClass itin>: 337 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 338 [], itin> ; 339 340 341class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 342 string asmstr, InstrItinClass itin>: 343 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 344 !strconcat(asmstr, "\t $rx"), [], itin> ; 345 346// 347// RRR-type instruction format 348// 349 350class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 351 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 352 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 353 354// 355// These Sel patterns support the generation of conditional move 356// pseudo instructions. 357// 358// The nomenclature uses the components making up the pseudo and may 359// be a bit counter intuitive when compared with the end result we seek. 360// For example using a bqez in the example directly below results in the 361// conditional move being done if the tested register is not zero. 362// I considered in easier to check by keeping the pseudo consistent with 363// it's components but it could have been done differently. 364// 365// The simplest case is when can test and operand directly and do the 366// conditional move based on a simple mips16 conditional 367// branch instruction. 368// for example: 369// if $op == beqz or bnez: 370// 371// $op1 $rt, .+4 372// move $rd, $rs 373// 374// if $op == beqz, then if $rt != 0, then the conditional assignment 375// $rd = $rs is done. 376 377// if $op == bnez, then if $rt == 0, then the conditional assignment 378// $rd = $rs is done. 379// 380// So this pseudo class only has one operand, i.e. op 381// 382class Sel<string op>: 383 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 384 CPU16Regs:$rt), 385 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 386 //let isCodeGenOnly=1; 387 let Constraints = "$rd = $rd_"; 388 let usesCustomInserter = 1; 389} 390 391// 392// The next two instruction classes allow for an operand which tests 393// two operands and returns a value in register T8 and 394//then does a conditional branch based on the value of T8 395// 396 397// op2 can be cmpi or slti/sltiu 398// op1 can bteqz or btnez 399// the operands for op2 are a register and a signed constant 400// 401// $op2 $t, $imm ;test register t and branch conditionally 402// $op1 .+4 ;op1 is a conditional branch 403// move $rd, $rs 404// 405// 406class SeliT<string op1, string op2>: 407 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 408 CPU16Regs:$rl, simm16:$imm), 409 !strconcat(op2, 410 !strconcat("\t$rl, $imm\n\t", 411 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 412 let isCodeGenOnly=1; 413 let Constraints = "$rd = $rd_"; 414 let usesCustomInserter = 1; 415} 416 417// 418// op2 can be cmp or slt/sltu 419// op1 can be bteqz or btnez 420// the operands for op2 are two registers 421// op1 is a conditional branch 422// 423// 424// $op2 $rl, $rr ;test registers rl,rr 425// $op1 .+4 ;op2 is a conditional branch 426// move $rd, $rs 427// 428// 429class SelT<string op1, string op2>: 430 MipsPseudo16<(outs CPU16Regs:$rd_), 431 (ins CPU16Regs:$rd, CPU16Regs:$rs, 432 CPU16Regs:$rl, CPU16Regs:$rr), 433 !strconcat(op2, 434 !strconcat("\t$rl, $rr\n\t", 435 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 436 let isCodeGenOnly=1; 437 let Constraints = "$rd = $rd_"; 438 let usesCustomInserter = 1; 439} 440 441// 442// 32 bit constant 443// 444def imm32: Operand<i32>; 445 446def Constant32: 447 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 448 449def LwConstant32: 450 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm), 451 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 452 453 454// 455// Some general instruction class info 456// 457// 458 459class ArithLogic16Defs<bit isCom=0> { 460 bits<5> shamt = 0; 461 bit isCommutable = isCom; 462 bit isReMaterializable = 1; 463 bit neverHasSideEffects = 1; 464} 465 466class branch16 { 467 bit isBranch = 1; 468 bit isTerminator = 1; 469 bit isBarrier = 1; 470} 471 472class cbranch16 { 473 bit isBranch = 1; 474 bit isTerminator = 1; 475} 476 477class MayLoad { 478 bit mayLoad = 1; 479} 480 481class MayStore { 482 bit mayStore = 1; 483} 484// 485 486 487// Format: ADDIU rx, immediate MIPS16e 488// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 489// To add a constant to a 32-bit integer. 490// 491def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 492 493def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 494 ArithLogic16Defs<0> { 495 let AddedComplexity = 5; 496} 497def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 498 ArithLogic16Defs<0> { 499 let isCodeGenOnly = 1; 500} 501 502def AddiuRxRyOffMemX16: 503 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 504 505// 506 507// Format: ADDIU rx, pc, immediate MIPS16e 508// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 509// To add a constant to the program counter. 510// 511def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 512 513// 514// Format: ADDIU sp, immediate MIPS16e 515// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 516// To add a constant to the stack pointer. 517// 518def AddiuSpImm16 519 : FI816_SP_ins<0b011, "addiu", IIAlu> { 520 let Defs = [SP]; 521 let Uses = [SP]; 522 let AddedComplexity = 5; 523} 524 525def AddiuSpImmX16 526 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 527 let Defs = [SP]; 528 let Uses = [SP]; 529} 530 531// 532// Format: ADDU rz, rx, ry MIPS16e 533// Purpose: Add Unsigned Word (3-Operand) 534// To add 32-bit integers. 535// 536 537def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 538 539// 540// Format: AND rx, ry MIPS16e 541// Purpose: AND 542// To do a bitwise logical AND. 543 544def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 545 546 547// 548// Format: BEQZ rx, offset MIPS16e 549// Purpose: Branch on Equal to Zero 550// To test a GPR then do a PC-relative conditional branch. 551// 552def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 553 554 555// 556// Format: BEQZ rx, offset MIPS16e 557// Purpose: Branch on Equal to Zero (Extended) 558// To test a GPR then do a PC-relative conditional branch. 559// 560def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 561 562// Format: B offset MIPS16e 563// Purpose: Unconditional Branch 564// To do an unconditional PC-relative branch. 565// 566def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 567 568// 569// Format: BNEZ rx, offset MIPS16e 570// Purpose: Branch on Not Equal to Zero 571// To test a GPR then do a PC-relative conditional branch. 572// 573def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 574 575// 576// Format: BNEZ rx, offset MIPS16e 577// Purpose: Branch on Not Equal to Zero (Extended) 578// To test a GPR then do a PC-relative conditional branch. 579// 580def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 581 582 583// 584//Format: BREAK immediate 585// Purpose: Breakpoint 586// To cause a Breakpoint exception. 587 588def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>; 589// 590// Format: BTEQZ offset MIPS16e 591// Purpose: Branch on T Equal to Zero (Extended) 592// To test special register T then do a PC-relative conditional branch. 593// 594def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 595 let Uses = [T8]; 596} 597 598def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 599 600def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 601 cbranch16; 602 603def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 604 605def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 606 607def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 608 609def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 610 cbranch16; 611 612// 613// Format: BTNEZ offset MIPS16e 614// Purpose: Branch on T Not Equal to Zero (Extended) 615// To test special register T then do a PC-relative conditional branch. 616// 617def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 618 let Uses = [T8]; 619} 620 621def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 622 623def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 624 625def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 626 627def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 628 629def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 630 631def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 632 cbranch16; 633 634// 635// Format: CMP rx, ry MIPS16e 636// Purpose: Compare 637// To compare the contents of two GPRs. 638// 639def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> { 640 let Defs = [T8]; 641} 642 643// 644// Format: CMPI rx, immediate MIPS16e 645// Purpose: Compare Immediate 646// To compare a constant with the contents of a GPR. 647// 648def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> { 649 let Defs = [T8]; 650} 651 652// 653// Format: CMPI rx, immediate MIPS16e 654// Purpose: Compare Immediate (Extended) 655// To compare a constant with the contents of a GPR. 656// 657def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> { 658 let Defs = [T8]; 659} 660 661 662// 663// Format: DIV rx, ry MIPS16e 664// Purpose: Divide Word 665// To divide 32-bit signed integers. 666// 667def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 668 let Defs = [HI, LO]; 669} 670 671// 672// Format: DIVU rx, ry MIPS16e 673// Purpose: Divide Unsigned Word 674// To divide 32-bit unsigned integers. 675// 676def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 677 let Defs = [HI, LO]; 678} 679// 680// Format: JAL target MIPS16e 681// Purpose: Jump and Link 682// To execute a procedure call within the current 256 MB-aligned 683// region and preserve the current ISA. 684// 685 686def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 687 let isBranch = 1; 688 let hasDelaySlot = 0; // not true, but we add the nop for now 689 let isTerminator=1; 690 let isBarrier=1; 691 let isCall=1; 692} 693 694// 695// Format: JR ra MIPS16e 696// Purpose: Jump Register Through Register ra 697// To execute a branch to the instruction address in the return 698// address register. 699// 700 701def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 702 let isBranch = 1; 703 let isIndirectBranch = 1; 704 let hasDelaySlot = 1; 705 let isTerminator=1; 706 let isBarrier=1; 707} 708 709def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 710 let isBranch = 1; 711 let isIndirectBranch = 1; 712 let isTerminator=1; 713 let isBarrier=1; 714} 715 716def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 717 let isBranch = 1; 718 let isIndirectBranch = 1; 719 let isTerminator=1; 720 let isBarrier=1; 721} 722// 723// Format: LB ry, offset(rx) MIPS16e 724// Purpose: Load Byte (Extended) 725// To load a byte from memory as a signed value. 726// 727def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 728 let isCodeGenOnly = 1; 729} 730 731// 732// Format: LBU ry, offset(rx) MIPS16e 733// Purpose: Load Byte Unsigned (Extended) 734// To load a byte from memory as a unsigned value. 735// 736def LbuRxRyOffMemX16: 737 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 738 let isCodeGenOnly = 1; 739} 740 741// 742// Format: LH ry, offset(rx) MIPS16e 743// Purpose: Load Halfword signed (Extended) 744// To load a halfword from memory as a signed value. 745// 746def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 747 let isCodeGenOnly = 1; 748} 749 750// 751// Format: LHU ry, offset(rx) MIPS16e 752// Purpose: Load Halfword unsigned (Extended) 753// To load a halfword from memory as an unsigned value. 754// 755def LhuRxRyOffMemX16: 756 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 757 let isCodeGenOnly = 1; 758} 759 760// 761// Format: LI rx, immediate MIPS16e 762// Purpose: Load Immediate 763// To load a constant into a GPR. 764// 765def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 766 767// 768// Format: LI rx, immediate MIPS16e 769// Purpose: Load Immediate (Extended) 770// To load a constant into a GPR. 771// 772def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 773 774// 775// Format: LW ry, offset(rx) MIPS16e 776// Purpose: Load Word (Extended) 777// To load a word from memory as a signed value. 778// 779def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 780 let isCodeGenOnly = 1; 781} 782 783// Format: LW rx, offset(sp) MIPS16e 784// Purpose: Load Word (SP-Relative, Extended) 785// To load an SP-relative word from memory as a signed value. 786// 787def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{ 788 let Uses = [SP]; 789} 790 791// 792// Format: MOVE r32, rz MIPS16e 793// Purpose: Move 794// To move the contents of a GPR to a GPR. 795// 796def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 797 798// 799// Format: MOVE ry, r32 MIPS16e 800//Purpose: Move 801// To move the contents of a GPR to a GPR. 802// 803def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 804 805// 806// Format: MFHI rx MIPS16e 807// Purpose: Move From HI Register 808// To copy the special purpose HI register to a GPR. 809// 810def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 811 let Uses = [HI]; 812 let neverHasSideEffects = 1; 813} 814 815// 816// Format: MFLO rx MIPS16e 817// Purpose: Move From LO Register 818// To copy the special purpose LO register to a GPR. 819// 820def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 821 let Uses = [LO]; 822 let neverHasSideEffects = 1; 823} 824 825// 826// Pseudo Instruction for mult 827// 828def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 829 let isCommutable = 1; 830 let neverHasSideEffects = 1; 831 let Defs = [HI, LO]; 832} 833 834def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 835 let isCommutable = 1; 836 let neverHasSideEffects = 1; 837 let Defs = [HI, LO]; 838} 839 840// 841// Format: MULT rx, ry MIPS16e 842// Purpose: Multiply Word 843// To multiply 32-bit signed integers. 844// 845def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 846 let isCommutable = 1; 847 let neverHasSideEffects = 1; 848 let Defs = [HI, LO]; 849} 850 851// 852// Format: MULTU rx, ry MIPS16e 853// Purpose: Multiply Unsigned Word 854// To multiply 32-bit unsigned integers. 855// 856def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 857 let isCommutable = 1; 858 let neverHasSideEffects = 1; 859 let Defs = [HI, LO]; 860} 861 862// 863// Format: NEG rx, ry MIPS16e 864// Purpose: Negate 865// To negate an integer value. 866// 867def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 868 869// 870// Format: NOT rx, ry MIPS16e 871// Purpose: Not 872// To complement an integer value 873// 874def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 875 876// 877// Format: OR rx, ry MIPS16e 878// Purpose: Or 879// To do a bitwise logical OR. 880// 881def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 882 883// 884// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 885// (All args are optional) MIPS16e 886// Purpose: Restore Registers and Deallocate Stack Frame 887// To deallocate a stack frame before exit from a subroutine, 888// restoring return address and static registers, and adjusting 889// stack 890// 891 892// fixed form for restoring RA and the frame 893// for direct object emitter, encoding needs to be adjusted for the 894// frame size 895// 896let ra=1, s=0,s0=1,s1=1 in 897def RestoreRaF16: 898 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 899 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad { 900 let isCodeGenOnly = 1; 901 let Defs = [S0, S1, S2, RA, SP]; 902 let Uses = [SP]; 903} 904 905// Use Restore to increment SP since SP is not a Mip 16 register, this 906// is an easy way to do that which does not require a register. 907// 908let ra=0, s=0,s0=0,s1=0 in 909def RestoreIncSpF16: 910 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 911 "restore\t$frame_size", [], IILoad >, MayLoad { 912 let isCodeGenOnly = 1; 913 let Defs = [SP]; 914 let Uses = [SP]; 915} 916 917// 918// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 919// MIPS16e 920// Purpose: Save Registers and Set Up Stack Frame 921// To set up a stack frame on entry to a subroutine, 922// saving return address and static registers, and adjusting stack 923// 924let ra=1, s=1,s0=1,s1=1 in 925def SaveRaF16: 926 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 927 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore { 928 let isCodeGenOnly = 1; 929 let Uses = [RA, SP, S0, S1, S2]; 930 let Defs = [SP]; 931} 932 933// 934// Use Save to decrement the SP by a constant since SP is not 935// a Mips16 register. 936// 937let ra=0, s=0,s0=0,s1=0 in 938def SaveDecSpF16: 939 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 940 "save\t$frame_size", [], IIStore >, MayStore { 941 let isCodeGenOnly = 1; 942 let Uses = [SP]; 943 let Defs = [SP]; 944} 945// 946// Format: SB ry, offset(rx) MIPS16e 947// Purpose: Store Byte (Extended) 948// To store a byte to memory. 949// 950def SbRxRyOffMemX16: 951 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 952 953// 954// The Sel(T) instructions are pseudos 955// T means that they use T8 implicitly. 956// 957// 958// Format: SelBeqZ rd, rs, rt 959// Purpose: if rt==0, do nothing 960// else rs = rt 961// 962def SelBeqZ: Sel<"beqz">; 963 964// 965// Format: SelTBteqZCmp rd, rs, rl, rr 966// Purpose: b = Cmp rl, rr. 967// If b==0 then do nothing. 968// if b!=0 then rd = rs 969// 970def SelTBteqZCmp: SelT<"bteqz", "cmp">; 971 972// 973// Format: SelTBteqZCmpi rd, rs, rl, rr 974// Purpose: b = Cmpi rl, imm. 975// If b==0 then do nothing. 976// if b!=0 then rd = rs 977// 978def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 979 980// 981// Format: SelTBteqZSlt rd, rs, rl, rr 982// Purpose: b = Slt rl, rr. 983// If b==0 then do nothing. 984// if b!=0 then rd = rs 985// 986def SelTBteqZSlt: SelT<"bteqz", "slt">; 987 988// 989// Format: SelTBteqZSlti rd, rs, rl, rr 990// Purpose: b = Slti rl, imm. 991// If b==0 then do nothing. 992// if b!=0 then rd = rs 993// 994def SelTBteqZSlti: SeliT<"bteqz", "slti">; 995 996// 997// Format: SelTBteqZSltu rd, rs, rl, rr 998// Purpose: b = Sltu rl, rr. 999// If b==0 then do nothing. 1000// if b!=0 then rd = rs 1001// 1002def SelTBteqZSltu: SelT<"bteqz", "sltu">; 1003 1004// 1005// Format: SelTBteqZSltiu rd, rs, rl, rr 1006// Purpose: b = Sltiu rl, imm. 1007// If b==0 then do nothing. 1008// if b!=0 then rd = rs 1009// 1010def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 1011 1012// 1013// Format: SelBnez rd, rs, rt 1014// Purpose: if rt!=0, do nothing 1015// else rs = rt 1016// 1017def SelBneZ: Sel<"bnez">; 1018 1019// 1020// Format: SelTBtneZCmp rd, rs, rl, rr 1021// Purpose: b = Cmp rl, rr. 1022// If b!=0 then do nothing. 1023// if b0=0 then rd = rs 1024// 1025def SelTBtneZCmp: SelT<"btnez", "cmp">; 1026 1027// 1028// Format: SelTBtnezCmpi rd, rs, rl, rr 1029// Purpose: b = Cmpi rl, imm. 1030// If b!=0 then do nothing. 1031// if b==0 then rd = rs 1032// 1033def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1034 1035// 1036// Format: SelTBtneZSlt rd, rs, rl, rr 1037// Purpose: b = Slt rl, rr. 1038// If b!=0 then do nothing. 1039// if b==0 then rd = rs 1040// 1041def SelTBtneZSlt: SelT<"btnez", "slt">; 1042 1043// 1044// Format: SelTBtneZSlti rd, rs, rl, rr 1045// Purpose: b = Slti rl, imm. 1046// If b!=0 then do nothing. 1047// if b==0 then rd = rs 1048// 1049def SelTBtneZSlti: SeliT<"btnez", "slti">; 1050 1051// 1052// Format: SelTBtneZSltu rd, rs, rl, rr 1053// Purpose: b = Sltu rl, rr. 1054// If b!=0 then do nothing. 1055// if b==0 then rd = rs 1056// 1057def SelTBtneZSltu: SelT<"btnez", "sltu">; 1058 1059// 1060// Format: SelTBtneZSltiu rd, rs, rl, rr 1061// Purpose: b = Slti rl, imm. 1062// If b!=0 then do nothing. 1063// if b==0 then rd = rs 1064// 1065def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1066// 1067// 1068// Format: SH ry, offset(rx) MIPS16e 1069// Purpose: Store Halfword (Extended) 1070// To store a halfword to memory. 1071// 1072def ShRxRyOffMemX16: 1073 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1074 1075// 1076// Format: SLL rx, ry, sa MIPS16e 1077// Purpose: Shift Word Left Logical (Extended) 1078// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 1079// 1080def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1081 1082// 1083// Format: SLLV ry, rx MIPS16e 1084// Purpose: Shift Word Left Logical Variable 1085// To execute a left-shift of a word by a variable number of bits. 1086// 1087def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1088 1089// Format: SLTI rx, immediate MIPS16e 1090// Purpose: Set on Less Than Immediate 1091// To record the result of a less-than comparison with a constant. 1092// 1093// 1094def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1095 let Defs = [T8]; 1096} 1097 1098// 1099// Format: SLTI rx, immediate MIPS16e 1100// Purpose: Set on Less Than Immediate (Extended) 1101// To record the result of a less-than comparison with a constant. 1102// 1103// 1104def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1105 let Defs = [T8]; 1106} 1107 1108def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1109 1110// Format: SLTIU rx, immediate MIPS16e 1111// Purpose: Set on Less Than Immediate Unsigned 1112// To record the result of a less-than comparison with a constant. 1113// 1114// 1115def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1116 let Defs = [T8]; 1117} 1118 1119// 1120// Format: SLTI rx, immediate MIPS16e 1121// Purpose: Set on Less Than Immediate Unsigned (Extended) 1122// To record the result of a less-than comparison with a constant. 1123// 1124// 1125def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1126 let Defs = [T8]; 1127} 1128// 1129// Format: SLTIU rx, immediate MIPS16e 1130// Purpose: Set on Less Than Immediate Unsigned (Extended) 1131// To record the result of a less-than comparison with a constant. 1132// 1133def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1134 1135// 1136// Format: SLT rx, ry MIPS16e 1137// Purpose: Set on Less Than 1138// To record the result of a less-than comparison. 1139// 1140def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{ 1141 let Defs = [T8]; 1142} 1143 1144def SltCCRxRy16: FCCRR16_ins<"slt">; 1145 1146// Format: SLTU rx, ry MIPS16e 1147// Purpose: Set on Less Than Unsigned 1148// To record the result of an unsigned less-than comparison. 1149// 1150def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{ 1151 let Defs = [T8]; 1152} 1153 1154def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1155 let isCodeGenOnly=1; 1156 let Defs = [T8]; 1157} 1158 1159 1160def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1161// 1162// Format: SRAV ry, rx MIPS16e 1163// Purpose: Shift Word Right Arithmetic Variable 1164// To execute an arithmetic right-shift of a word by a variable 1165// number of bits. 1166// 1167def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1168 1169 1170// 1171// Format: SRA rx, ry, sa MIPS16e 1172// Purpose: Shift Word Right Arithmetic (Extended) 1173// To execute an arithmetic right-shift of a word by a fixed 1174// number of bits—1 to 8 bits. 1175// 1176def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1177 1178 1179// 1180// Format: SRLV ry, rx MIPS16e 1181// Purpose: Shift Word Right Logical Variable 1182// To execute a logical right-shift of a word by a variable 1183// number of bits. 1184// 1185def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1186 1187 1188// 1189// Format: SRL rx, ry, sa MIPS16e 1190// Purpose: Shift Word Right Logical (Extended) 1191// To execute a logical right-shift of a word by a fixed 1192// number of bits—1 to 31 bits. 1193// 1194def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1195 1196// 1197// Format: SUBU rz, rx, ry MIPS16e 1198// Purpose: Subtract Unsigned Word 1199// To subtract 32-bit integers 1200// 1201def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1202 1203// 1204// Format: SW ry, offset(rx) MIPS16e 1205// Purpose: Store Word (Extended) 1206// To store a word to memory. 1207// 1208def SwRxRyOffMemX16: 1209 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1210 1211// 1212// Format: SW rx, offset(sp) MIPS16e 1213// Purpose: Store Word rx (SP-Relative) 1214// To store an SP-relative word to memory. 1215// 1216def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins 1217 <0b11010, "sw", IIStore>, MayStore; 1218 1219// 1220// 1221// Format: XOR rx, ry MIPS16e 1222// Purpose: Xor 1223// To do a bitwise logical XOR. 1224// 1225def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1226 1227class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1228 let Predicates = [InMips16Mode]; 1229} 1230 1231// Unary Arith/Logic 1232// 1233class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1234 Mips16Pat<(OpNode CPU16Regs:$r), 1235 (I CPU16Regs:$r)>; 1236 1237def: ArithLogicU_pat<not, NotRxRy16>; 1238def: ArithLogicU_pat<ineg, NegRxRy16>; 1239 1240class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1241 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1242 (I CPU16Regs:$l, CPU16Regs:$r)>; 1243 1244def: ArithLogic16_pat<add, AdduRxRyRz16>; 1245def: ArithLogic16_pat<and, AndRxRxRy16>; 1246def: ArithLogic16_pat<mul, MultRxRyRz16>; 1247def: ArithLogic16_pat<or, OrRxRxRy16>; 1248def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1249def: ArithLogic16_pat<xor, XorRxRxRy16>; 1250 1251// Arithmetic and logical instructions with 2 register operands. 1252 1253class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1254 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1255 (I CPU16Regs:$in, imm_type:$imm)>; 1256 1257def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1258def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1259def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1260def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1261def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1262 1263class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1264 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1265 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1266 1267def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1268def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1269def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1270 1271class LoadM16_pat<PatFrag OpNode, Instruction I> : 1272 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1273 1274def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1275def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1276def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1277def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1278def: LoadM16_pat<load, LwRxRyOffMemX16>; 1279 1280class StoreM16_pat<PatFrag OpNode, Instruction I> : 1281 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1282 (I CPU16Regs:$r, addr16:$addr)>; 1283 1284def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1285def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1286def: StoreM16_pat<store, SwRxRyOffMemX16>; 1287 1288// Unconditional branch 1289class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1290 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1291 let Predicates = [InMips16Mode]; 1292 } 1293 1294def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1295 (Jal16 tglobaladdr:$dst)>; 1296 1297def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1298 (Jal16 texternalsym:$dst)>; 1299 1300// Indirect branch 1301def: Mips16Pat< 1302 (brind CPU16Regs:$rs), 1303 (JrcRx16 CPU16Regs:$rs)>; 1304 1305// Jump and Link (Call) 1306let isCall=1, hasDelaySlot=0 in 1307def JumpLinkReg16: 1308 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1309 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1310 1311// Mips16 pseudos 1312let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1313 hasExtraSrcRegAllocReq = 1 in 1314def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1315 1316 1317// setcc patterns 1318 1319class SetCC_R16<PatFrag cond_op, Instruction I>: 1320 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1321 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1322 1323class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1324 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1325 (I CPU16Regs:$rx, imm_type:$imm16)>; 1326 1327 1328def: Mips16Pat<(i32 addr16:$addr), 1329 (AddiuRxRyOffMemX16 addr16:$addr)>; 1330 1331 1332// Large (>16 bit) immediate loads 1333def : Mips16Pat<(i32 imm:$imm), 1334 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1335 (LiRxImmX16 (LO16 imm:$imm)))>; 1336 1337// Carry MipsPatterns 1338def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1339 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1340def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1341 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1342def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1343 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1344 1345// 1346// Some branch conditional patterns are not generated by llvm at this time. 1347// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1348// comparison they are used and for unsigned a different pattern is used. 1349// I am pushing upstream from the full mips16 port and it seemed that I needed 1350// these earlier and the mips32 port has these but now I cannot create test 1351// cases that use these patterns. While I sort this all out I will leave these 1352// extra patterns commented out and if I can be sure they are really not used, 1353// I will delete the code. I don't want to check the code in uncommented without 1354// a valid test case. In some cases, the compiler is generating patterns with 1355// setcc instead and earlier I had implemented setcc first so may have masked 1356// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1357// figure out how to enable the brcond patterns or else possibly new 1358// combinations of of brcond and setcc. 1359// 1360// 1361// bcond-seteq 1362// 1363def: Mips16Pat 1364 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1365 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1366 >; 1367 1368 1369def: Mips16Pat 1370 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1371 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1372 >; 1373 1374def: Mips16Pat 1375 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1376 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1377 >; 1378 1379// 1380// bcond-setgt (do we need to have this pair of setlt, setgt??) 1381// 1382def: Mips16Pat 1383 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1384 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1385 >; 1386 1387// 1388// bcond-setge 1389// 1390def: Mips16Pat 1391 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1392 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1393 >; 1394 1395// 1396// never called because compiler transforms a >= k to a > (k-1) 1397def: Mips16Pat 1398 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1399 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1400 >; 1401 1402// 1403// bcond-setlt 1404// 1405def: Mips16Pat 1406 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1407 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1408 >; 1409 1410def: Mips16Pat 1411 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1412 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1413 >; 1414 1415// 1416// bcond-setle 1417// 1418def: Mips16Pat 1419 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1420 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1421 >; 1422 1423// 1424// bcond-setne 1425// 1426def: Mips16Pat 1427 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1428 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1429 >; 1430 1431def: Mips16Pat 1432 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1433 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1434 >; 1435 1436def: Mips16Pat 1437 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1438 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1439 >; 1440 1441// 1442// This needs to be there but I forget which code will generate it 1443// 1444def: Mips16Pat 1445 <(brcond CPU16Regs:$rx, bb:$targ16), 1446 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1447 >; 1448 1449// 1450 1451// 1452// bcond-setugt 1453// 1454//def: Mips16Pat 1455// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1456// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1457// >; 1458 1459// 1460// bcond-setuge 1461// 1462//def: Mips16Pat 1463// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1464// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1465// >; 1466 1467 1468// 1469// bcond-setult 1470// 1471//def: Mips16Pat 1472// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1473// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1474// >; 1475 1476def: UncondBranch16_pat<br, BimmX16>; 1477 1478// Small immediates 1479def: Mips16Pat<(i32 immSExt16:$in), 1480 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1481 1482def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1483 1484// 1485// MipsDivRem 1486// 1487def: Mips16Pat 1488 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), 1489 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1490 1491// 1492// MipsDivRemU 1493// 1494def: Mips16Pat 1495 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry), 1496 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1497 1498// signed a,b 1499// x = (a>=b)?x:y 1500// 1501// if !(a < b) x = y 1502// 1503def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1504 CPU16Regs:$x, CPU16Regs:$y), 1505 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1506 CPU16Regs:$a, CPU16Regs:$b)>; 1507 1508// signed a,b 1509// x = (a>b)?x:y 1510// 1511// if (b < a) x = y 1512// 1513def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1514 CPU16Regs:$x, CPU16Regs:$y), 1515 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1516 CPU16Regs:$b, CPU16Regs:$a)>; 1517 1518// unsigned a,b 1519// x = (a>=b)?x:y 1520// 1521// if !(a < b) x = y; 1522// 1523def : Mips16Pat< 1524 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1525 CPU16Regs:$x, CPU16Regs:$y), 1526 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1527 CPU16Regs:$a, CPU16Regs:$b)>; 1528 1529// unsigned a,b 1530// x = (a>b)?x:y 1531// 1532// if (b < a) x = y 1533// 1534def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1535 CPU16Regs:$x, CPU16Regs:$y), 1536 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1537 CPU16Regs:$b, CPU16Regs:$a)>; 1538 1539// signed 1540// x = (a >= k)?x:y 1541// due to an llvm optimization, i don't think that this will ever 1542// be used. This is transformed into x = (a > k-1)?x:y 1543// 1544// 1545 1546//def : Mips16Pat< 1547// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1548// CPU16Regs:$T, CPU16Regs:$F), 1549// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1550// CPU16Regs:$lhs, immSExt16:$rhs)>; 1551 1552//def : Mips16Pat< 1553// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1554// CPU16Regs:$T, CPU16Regs:$F), 1555// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1556// CPU16Regs:$lhs, immSExt16:$rhs)>; 1557 1558// signed 1559// x = (a < k)?x:y 1560// 1561// if !(a < k) x = y; 1562// 1563def : Mips16Pat< 1564 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1565 CPU16Regs:$x, CPU16Regs:$y), 1566 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1567 CPU16Regs:$a, immSExt16:$b)>; 1568 1569 1570// 1571// 1572// signed 1573// x = (a <= b)? x : y 1574// 1575// if (b < a) x = y 1576// 1577def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1578 CPU16Regs:$x, CPU16Regs:$y), 1579 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1580 CPU16Regs:$b, CPU16Regs:$a)>; 1581 1582// 1583// unnsigned 1584// x = (a <= b)? x : y 1585// 1586// if (b < a) x = y 1587// 1588def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1589 CPU16Regs:$x, CPU16Regs:$y), 1590 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1591 CPU16Regs:$b, CPU16Regs:$a)>; 1592 1593// 1594// signed/unsigned 1595// x = (a == b)? x : y 1596// 1597// if (a != b) x = y 1598// 1599def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1600 CPU16Regs:$x, CPU16Regs:$y), 1601 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1602 CPU16Regs:$b, CPU16Regs:$a)>; 1603 1604// 1605// signed/unsigned 1606// x = (a == 0)? x : y 1607// 1608// if (a != 0) x = y 1609// 1610def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1611 CPU16Regs:$x, CPU16Regs:$y), 1612 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1613 CPU16Regs:$a)>; 1614 1615 1616// 1617// signed/unsigned 1618// x = (a == k)? x : y 1619// 1620// if (a != k) x = y 1621// 1622def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1623 CPU16Regs:$x, CPU16Regs:$y), 1624 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1625 CPU16Regs:$a, immZExt16:$k)>; 1626 1627 1628// 1629// signed/unsigned 1630// x = (a != b)? x : y 1631// 1632// if (a == b) x = y 1633// 1634// 1635def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1636 CPU16Regs:$x, CPU16Regs:$y), 1637 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1638 CPU16Regs:$b, CPU16Regs:$a)>; 1639 1640// 1641// signed/unsigned 1642// x = (a != 0)? x : y 1643// 1644// if (a == 0) x = y 1645// 1646def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1647 CPU16Regs:$x, CPU16Regs:$y), 1648 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1649 CPU16Regs:$a)>; 1650 1651// signed/unsigned 1652// x = (a)? x : y 1653// 1654// if (!a) x = y 1655// 1656def : Mips16Pat<(select CPU16Regs:$a, 1657 CPU16Regs:$x, CPU16Regs:$y), 1658 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1659 CPU16Regs:$a)>; 1660 1661 1662// 1663// signed/unsigned 1664// x = (a != k)? x : y 1665// 1666// if (a == k) x = y 1667// 1668def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1669 CPU16Regs:$x, CPU16Regs:$y), 1670 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1671 CPU16Regs:$a, immZExt16:$k)>; 1672 1673// 1674// When writing C code to test setxx these patterns, 1675// some will be transformed into 1676// other things. So we test using C code but using -O3 and -O0 1677// 1678// seteq 1679// 1680def : Mips16Pat 1681 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1682 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1683 1684def : Mips16Pat 1685 <(seteq CPU16Regs:$lhs, 0), 1686 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1687 1688 1689// 1690// setge 1691// 1692 1693def: Mips16Pat 1694 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1695 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1696 (LiRxImmX16 1))>; 1697 1698// 1699// For constants, llvm transforms this to: 1700// x > (k -1) and then reverses the operands to use setlt. So this pattern 1701// is not used now by the compiler. (Presumably checking that k-1 does not 1702// overflow). The compiler never uses this at a the current time, due to 1703// other optimizations. 1704// 1705//def: Mips16Pat 1706// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1707// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1708// (LiRxImmX16 1))>; 1709 1710// This catches the x >= -32768 case by transforming it to x > -32769 1711// 1712def: Mips16Pat 1713 <(setgt CPU16Regs:$lhs, -32769), 1714 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1715 (LiRxImmX16 1))>; 1716 1717// 1718// setgt 1719// 1720// 1721 1722def: Mips16Pat 1723 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1724 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1725 1726// 1727// setle 1728// 1729def: Mips16Pat 1730 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1731 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1732 1733// 1734// setlt 1735// 1736def: SetCC_R16<setlt, SltCCRxRy16>; 1737 1738def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1739 1740// 1741// setne 1742// 1743def : Mips16Pat 1744 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1745 (SltuCCRxRy16 (LiRxImmX16 0), 1746 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1747 1748 1749// 1750// setuge 1751// 1752def: Mips16Pat 1753 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1754 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1755 (LiRxImmX16 1))>; 1756 1757// this pattern will never be used because the compiler will transform 1758// x >= k to x > (k - 1) and then use SLT 1759// 1760//def: Mips16Pat 1761// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1762// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1763// (LiRxImmX16 1))>; 1764 1765// 1766// setugt 1767// 1768def: Mips16Pat 1769 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1770 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1771 1772// 1773// setule 1774// 1775def: Mips16Pat 1776 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1777 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1778 1779// 1780// setult 1781// 1782def: SetCC_R16<setult, SltuCCRxRy16>; 1783 1784def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1785 1786def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1787 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1788 1789// hi/lo relocs 1790 1791def : Mips16Pat<(MipsHi tglobaladdr:$in), 1792 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1793def : Mips16Pat<(MipsHi tjumptable:$in), 1794 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1795def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1796 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1797 1798// wrapper_pic 1799class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1800 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1801 (ADDiuOp RC:$gp, node:$in)>; 1802 1803 1804def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1805def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1806 1807def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1808 (LbuRxRyOffMemX16 addr16:$src)>; 1809def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1810 (LhuRxRyOffMemX16 addr16:$src)>; 1811 1812def: Mips16Pat<(trap), (Break16)>; 1813 1814