Mips16InstrInfo.td revision 5404ed811de113a21c99366c43b1209f3ba40c62
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// 36// I8 instruction format 37// 38 39class FI816_ins_base<bits<3> _func, string asmstr, 40 string asmstr2, InstrItinClass itin>: 41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 42 [], itin>; 43 44 45class FI816_SP_ins<bits<3> _func, string asmstr, 46 InstrItinClass itin>: 47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 48 49// 50// RI instruction format 51// 52 53 54class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 55 InstrItinClass itin>: 56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 57 !strconcat(asmstr, asmstr2), [], itin>; 58 59class FRI16_ins<bits<5> op, string asmstr, 60 InstrItinClass itin>: 61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 62 63class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 64 InstrItinClass itin>: 65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 66 !strconcat(asmstr, asmstr2), [], itin>; 67 68class FRI16R_ins<bits<5> op, string asmstr, 69 InstrItinClass itin>: 70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 71 72class F2RI16_ins<bits<5> _op, string asmstr, 73 InstrItinClass itin>: 74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 76 let Constraints = "$rx_ = $rx"; 77} 78 79class FRI16_B_ins<bits<5> _op, string asmstr, 80 InstrItinClass itin>: 81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 83// 84// Compare a register and immediate and place result in CC 85// Implicit use of T8 86// 87// EXT-CCRR Instruction format 88// 89class FEXT_CCRXI16_ins<string asmstr>: 90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 92 let isCodeGenOnly=1; 93 let usesCustomInserter = 1; 94} 95 96// JAL and JALX instruction format 97// 98class FJAL16_ins<bits<1> _X, string asmstr, 99 InstrItinClass itin>: 100 FJAL16<_X, (outs), (ins simm20:$imm), 101 !strconcat(asmstr, "\t$imm\n\tnop"),[], 102 itin> { 103 let isCodeGenOnly=1; 104} 105// 106// EXT-I instruction format 107// 108class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 109 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 110 !strconcat(asmstr, "\t$imm16"),[], itin>; 111 112// 113// EXT-I8 instruction format 114// 115 116class FEXT_I816_ins_base<bits<3> _func, string asmstr, 117 string asmstr2, InstrItinClass itin>: 118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 119 [], itin>; 120 121class FEXT_I816_ins<bits<3> _func, string asmstr, 122 InstrItinClass itin>: 123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 124 125class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 126 InstrItinClass itin>: 127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 128 129// 130// Assembler formats in alphabetical order. 131// Natural and pseudos are mixed together. 132// 133// Compare two registers and place result in CC 134// Implicit use of T8 135// 136// CC-RR Instruction format 137// 138class FCCRR16_ins<string asmstr> : 139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 141 let isCodeGenOnly=1; 142 let usesCustomInserter = 1; 143} 144 145// 146// EXT-RI instruction format 147// 148 149class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 150 InstrItinClass itin>: 151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 152 !strconcat(asmstr, asmstr2), [], itin>; 153 154class FEXT_RI16_ins<bits<5> _op, string asmstr, 155 InstrItinClass itin>: 156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 157 158class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 159 InstrItinClass itin>: 160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 161 !strconcat(asmstr, asmstr2), [], itin>; 162 163class FEXT_RI16R_ins<bits<5> _op, string asmstr, 164 InstrItinClass itin>: 165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 166 167class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 169 170class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 171 InstrItinClass itin>: 172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 174 175class FEXT_2RI16_ins<bits<5> _op, string asmstr, 176 InstrItinClass itin>: 177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 179 let Constraints = "$rx_ = $rx"; 180} 181 182 183// this has an explicit sp argument that we ignore to work around a problem 184// in the compiler 185class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 186 InstrItinClass itin>: 187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 189 190class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr, 191 InstrItinClass itin>: 192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm), 193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 194 195// 196// EXT-RRI instruction format 197// 198 199class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 200 InstrItinClass itin>: 201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 203 204class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 205 InstrItinClass itin>: 206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 208 209// 210// 211// EXT-RRI-A instruction format 212// 213 214class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 215 InstrItinClass itin>: 216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 218 219// 220// EXT-SHIFT instruction format 221// 222class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa), 224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 225 226// 227// EXT-T8I8 228// 229class FEXT_T8I816_ins<string asmstr, string asmstr2>: 230 MipsPseudo16<(outs), 231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 233 !strconcat(asmstr, "\t$imm"))),[]> { 234 let isCodeGenOnly=1; 235 let usesCustomInserter = 1; 236} 237 238// 239// EXT-T8I8I 240// 241class FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 242 MipsPseudo16<(outs), 243 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 244 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 245 !strconcat(asmstr, "\t$targ"))), []> { 246 let isCodeGenOnly=1; 247 let usesCustomInserter = 1; 248} 249// 250 251 252// 253// I8_MOVR32 instruction format (used only by the MOVR32 instructio 254// 255class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 256 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32), 257 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 258 259// 260// I8_MOV32R instruction format (used only by MOV32R instruction) 261// 262 263class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 264 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz), 265 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 266 267// 268// This are pseudo formats for multiply 269// This first one can be changed to non pseudo now. 270// 271// MULT 272// 273class FMULT16_ins<string asmstr, InstrItinClass itin> : 274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 275 !strconcat(asmstr, "\t$rx, $ry"), []>; 276 277// 278// MULT-LO 279// 280class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 283 let isCodeGenOnly=1; 284} 285 286// 287// RR-type instruction format 288// 289 290class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 293} 294 295class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> : 296 FRRBreak16<(outs), (ins), asmstr, [], itin> { 297 let Code=0; 298} 299 300class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : 301 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 302 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 303} 304 305class FRRTR16_ins<string asmstr> : 306 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 307 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 308 309// 310// maybe refactor but need a $zero as a dummy first parameter 311// 312class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 313 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 314 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 315 316class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 317 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 318 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 319 320 321class FRR16_M_ins<bits<5> f, string asmstr, 322 InstrItinClass itin> : 323 FRR16<f, (outs CPU16Regs:$rx), (ins), 324 !strconcat(asmstr, "\t$rx"), [], itin>; 325 326class FRxRxRy16_ins<bits<5> f, string asmstr, 327 InstrItinClass itin> : 328 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 329 !strconcat(asmstr, "\t$rz, $ry"), 330 [], itin> { 331 let Constraints = "$rx = $rz"; 332} 333 334let rx=0 in 335class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 336 string asmstr, InstrItinClass itin>: 337 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 338 [], itin> ; 339 340 341class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 342 string asmstr, InstrItinClass itin>: 343 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 344 !strconcat(asmstr, "\t $rx"), [], itin> ; 345 346// 347// RRR-type instruction format 348// 349 350class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 351 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 352 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 353 354// 355// These Sel patterns support the generation of conditional move 356// pseudo instructions. 357// 358// The nomenclature uses the components making up the pseudo and may 359// be a bit counter intuitive when compared with the end result we seek. 360// For example using a bqez in the example directly below results in the 361// conditional move being done if the tested register is not zero. 362// I considered in easier to check by keeping the pseudo consistent with 363// it's components but it could have been done differently. 364// 365// The simplest case is when can test and operand directly and do the 366// conditional move based on a simple mips16 conditional 367// branch instruction. 368// for example: 369// if $op == beqz or bnez: 370// 371// $op1 $rt, .+4 372// move $rd, $rs 373// 374// if $op == beqz, then if $rt != 0, then the conditional assignment 375// $rd = $rs is done. 376 377// if $op == bnez, then if $rt == 0, then the conditional assignment 378// $rd = $rs is done. 379// 380// So this pseudo class only has one operand, i.e. op 381// 382class Sel<string op>: 383 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 384 CPU16Regs:$rt), 385 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 386 //let isCodeGenOnly=1; 387 let Constraints = "$rd = $rd_"; 388 let usesCustomInserter = 1; 389} 390 391// 392// The next two instruction classes allow for an operand which tests 393// two operands and returns a value in register T8 and 394//then does a conditional branch based on the value of T8 395// 396 397// op2 can be cmpi or slti/sltiu 398// op1 can bteqz or btnez 399// the operands for op2 are a register and a signed constant 400// 401// $op2 $t, $imm ;test register t and branch conditionally 402// $op1 .+4 ;op1 is a conditional branch 403// move $rd, $rs 404// 405// 406class SeliT<string op1, string op2>: 407 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 408 CPU16Regs:$rl, simm16:$imm), 409 !strconcat(op2, 410 !strconcat("\t$rl, $imm\n\t", 411 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 412 let isCodeGenOnly=1; 413 let Constraints = "$rd = $rd_"; 414 let usesCustomInserter = 1; 415} 416 417// 418// op2 can be cmp or slt/sltu 419// op1 can be bteqz or btnez 420// the operands for op2 are two registers 421// op1 is a conditional branch 422// 423// 424// $op2 $rl, $rr ;test registers rl,rr 425// $op1 .+4 ;op2 is a conditional branch 426// move $rd, $rs 427// 428// 429class SelT<string op1, string op2>: 430 MipsPseudo16<(outs CPU16Regs:$rd_), 431 (ins CPU16Regs:$rd, CPU16Regs:$rs, 432 CPU16Regs:$rl, CPU16Regs:$rr), 433 !strconcat(op2, 434 !strconcat("\t$rl, $rr\n\t", 435 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 436 let isCodeGenOnly=1; 437 let Constraints = "$rd = $rd_"; 438 let usesCustomInserter = 1; 439} 440 441// 442// 32 bit constant 443// 444def imm32: Operand<i32>; 445 446def Constant32: 447 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 448 449def LwConstant32: 450 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm), 451 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 452 453 454// 455// Some general instruction class info 456// 457// 458 459class ArithLogic16Defs<bit isCom=0> { 460 bits<5> shamt = 0; 461 bit isCommutable = isCom; 462 bit isReMaterializable = 1; 463 bit neverHasSideEffects = 1; 464} 465 466class branch16 { 467 bit isBranch = 1; 468 bit isTerminator = 1; 469 bit isBarrier = 1; 470} 471 472class cbranch16 { 473 bit isBranch = 1; 474 bit isTerminator = 1; 475} 476 477class MayLoad { 478 bit mayLoad = 1; 479} 480 481class MayStore { 482 bit mayStore = 1; 483} 484// 485 486 487// Format: ADDIU rx, immediate MIPS16e 488// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 489// To add a constant to a 32-bit integer. 490// 491def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 492 493def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 494 ArithLogic16Defs<0> { 495 let AddedComplexity = 5; 496} 497def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 498 ArithLogic16Defs<0> { 499 let isCodeGenOnly = 1; 500} 501 502def AddiuRxRyOffMemX16: 503 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 504 505// 506 507// Format: ADDIU rx, pc, immediate MIPS16e 508// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 509// To add a constant to the program counter. 510// 511def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 512 513// 514// Format: ADDIU sp, immediate MIPS16e 515// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 516// To add a constant to the stack pointer. 517// 518def AddiuSpImm16 519 : FI816_SP_ins<0b011, "addiu", IIAlu> { 520 let Defs = [SP]; 521 let Uses = [SP]; 522 let AddedComplexity = 5; 523} 524 525def AddiuSpImmX16 526 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 527 let Defs = [SP]; 528 let Uses = [SP]; 529} 530 531// 532// Format: ADDU rz, rx, ry MIPS16e 533// Purpose: Add Unsigned Word (3-Operand) 534// To add 32-bit integers. 535// 536 537def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 538 539// 540// Format: AND rx, ry MIPS16e 541// Purpose: AND 542// To do a bitwise logical AND. 543 544def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 545 546 547// 548// Format: BEQZ rx, offset MIPS16e 549// Purpose: Branch on Equal to Zero 550// To test a GPR then do a PC-relative conditional branch. 551// 552def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 553 554 555// 556// Format: BEQZ rx, offset MIPS16e 557// Purpose: Branch on Equal to Zero (Extended) 558// To test a GPR then do a PC-relative conditional branch. 559// 560def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 561 562// Format: B offset MIPS16e 563// Purpose: Unconditional Branch 564// To do an unconditional PC-relative branch. 565// 566def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 567 568// 569// Format: BNEZ rx, offset MIPS16e 570// Purpose: Branch on Not Equal to Zero 571// To test a GPR then do a PC-relative conditional branch. 572// 573def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 574 575// 576// Format: BNEZ rx, offset MIPS16e 577// Purpose: Branch on Not Equal to Zero (Extended) 578// To test a GPR then do a PC-relative conditional branch. 579// 580def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 581 582 583// 584//Format: BREAK immediate 585// Purpose: Breakpoint 586// To cause a Breakpoint exception. 587 588def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>; 589// 590// Format: BTEQZ offset MIPS16e 591// Purpose: Branch on T Equal to Zero (Extended) 592// To test special register T then do a PC-relative conditional branch. 593// 594def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 595 let Uses = [T8]; 596} 597 598def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 599 600def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 601 cbranch16; 602 603def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 604 605def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 606 607def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 608 609def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 610 cbranch16; 611 612// 613// Format: BTNEZ offset MIPS16e 614// Purpose: Branch on T Not Equal to Zero (Extended) 615// To test special register T then do a PC-relative conditional branch. 616// 617def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 618 let Uses = [T8]; 619} 620 621def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 622 623def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 624 625def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 626 627def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 628 629def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 630 631def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 632 cbranch16; 633 634// 635// Format: CMP rx, ry MIPS16e 636// Purpose: Compare 637// To compare the contents of two GPRs. 638// 639def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> { 640 let Defs = [T8]; 641} 642 643// 644// Format: CMPI rx, immediate MIPS16e 645// Purpose: Compare Immediate 646// To compare a constant with the contents of a GPR. 647// 648def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> { 649 let Defs = [T8]; 650} 651 652// 653// Format: CMPI rx, immediate MIPS16e 654// Purpose: Compare Immediate (Extended) 655// To compare a constant with the contents of a GPR. 656// 657def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> { 658 let Defs = [T8]; 659} 660 661 662// 663// Format: DIV rx, ry MIPS16e 664// Purpose: Divide Word 665// To divide 32-bit signed integers. 666// 667def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 668 let Defs = [HI0, LO0]; 669} 670 671// 672// Format: DIVU rx, ry MIPS16e 673// Purpose: Divide Unsigned Word 674// To divide 32-bit unsigned integers. 675// 676def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 677 let Defs = [HI0, LO0]; 678} 679// 680// Format: JAL target MIPS16e 681// Purpose: Jump and Link 682// To execute a procedure call within the current 256 MB-aligned 683// region and preserve the current ISA. 684// 685 686def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 687 let hasDelaySlot = 0; // not true, but we add the nop for now 688 let isCall=1; 689} 690 691// 692// Format: JR ra MIPS16e 693// Purpose: Jump Register Through Register ra 694// To execute a branch to the instruction address in the return 695// address register. 696// 697 698def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 699 let isBranch = 1; 700 let isIndirectBranch = 1; 701 let hasDelaySlot = 1; 702 let isTerminator=1; 703 let isBarrier=1; 704} 705 706def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 707 let isBranch = 1; 708 let isIndirectBranch = 1; 709 let isTerminator=1; 710 let isBarrier=1; 711} 712 713def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 714 let isBranch = 1; 715 let isIndirectBranch = 1; 716 let isTerminator=1; 717 let isBarrier=1; 718} 719// 720// Format: LB ry, offset(rx) MIPS16e 721// Purpose: Load Byte (Extended) 722// To load a byte from memory as a signed value. 723// 724def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 725 let isCodeGenOnly = 1; 726} 727 728// 729// Format: LBU ry, offset(rx) MIPS16e 730// Purpose: Load Byte Unsigned (Extended) 731// To load a byte from memory as a unsigned value. 732// 733def LbuRxRyOffMemX16: 734 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 735 let isCodeGenOnly = 1; 736} 737 738// 739// Format: LH ry, offset(rx) MIPS16e 740// Purpose: Load Halfword signed (Extended) 741// To load a halfword from memory as a signed value. 742// 743def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 744 let isCodeGenOnly = 1; 745} 746 747// 748// Format: LHU ry, offset(rx) MIPS16e 749// Purpose: Load Halfword unsigned (Extended) 750// To load a halfword from memory as an unsigned value. 751// 752def LhuRxRyOffMemX16: 753 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 754 let isCodeGenOnly = 1; 755} 756 757// 758// Format: LI rx, immediate MIPS16e 759// Purpose: Load Immediate 760// To load a constant into a GPR. 761// 762def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 763 764// 765// Format: LI rx, immediate MIPS16e 766// Purpose: Load Immediate (Extended) 767// To load a constant into a GPR. 768// 769def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 770 771def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> { 772 let isCodeGenOnly = 1; 773} 774 775// 776// Format: LW ry, offset(rx) MIPS16e 777// Purpose: Load Word (Extended) 778// To load a word from memory as a signed value. 779// 780def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 781 let isCodeGenOnly = 1; 782} 783 784// Format: LW rx, offset(sp) MIPS16e 785// Purpose: Load Word (SP-Relative, Extended) 786// To load an SP-relative word from memory as a signed value. 787// 788def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{ 789 let Uses = [SP]; 790} 791 792// 793// Format: MOVE r32, rz MIPS16e 794// Purpose: Move 795// To move the contents of a GPR to a GPR. 796// 797def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 798 799// 800// Format: MOVE ry, r32 MIPS16e 801//Purpose: Move 802// To move the contents of a GPR to a GPR. 803// 804def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 805 806// 807// Format: MFHI rx MIPS16e 808// Purpose: Move From HI Register 809// To copy the special purpose HI register to a GPR. 810// 811def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 812 let Uses = [HI0]; 813 let neverHasSideEffects = 1; 814} 815 816// 817// Format: MFLO rx MIPS16e 818// Purpose: Move From LO Register 819// To copy the special purpose LO register to a GPR. 820// 821def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 822 let Uses = [LO0]; 823 let neverHasSideEffects = 1; 824} 825 826// 827// Pseudo Instruction for mult 828// 829def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 830 let isCommutable = 1; 831 let neverHasSideEffects = 1; 832 let Defs = [HI0, LO0]; 833} 834 835def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 836 let isCommutable = 1; 837 let neverHasSideEffects = 1; 838 let Defs = [HI0, LO0]; 839} 840 841// 842// Format: MULT rx, ry MIPS16e 843// Purpose: Multiply Word 844// To multiply 32-bit signed integers. 845// 846def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 847 let isCommutable = 1; 848 let neverHasSideEffects = 1; 849 let Defs = [HI0, LO0]; 850} 851 852// 853// Format: MULTU rx, ry MIPS16e 854// Purpose: Multiply Unsigned Word 855// To multiply 32-bit unsigned integers. 856// 857def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 858 let isCommutable = 1; 859 let neverHasSideEffects = 1; 860 let Defs = [HI0, LO0]; 861} 862 863// 864// Format: NEG rx, ry MIPS16e 865// Purpose: Negate 866// To negate an integer value. 867// 868def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 869 870// 871// Format: NOT rx, ry MIPS16e 872// Purpose: Not 873// To complement an integer value 874// 875def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 876 877// 878// Format: OR rx, ry MIPS16e 879// Purpose: Or 880// To do a bitwise logical OR. 881// 882def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 883 884// 885// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 886// (All args are optional) MIPS16e 887// Purpose: Restore Registers and Deallocate Stack Frame 888// To deallocate a stack frame before exit from a subroutine, 889// restoring return address and static registers, and adjusting 890// stack 891// 892 893// fixed form for restoring RA and the frame 894// for direct object emitter, encoding needs to be adjusted for the 895// frame size 896// 897let ra=1, s=0,s0=1,s1=1 in 898def RestoreRaF16: 899 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 900 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad { 901 let isCodeGenOnly = 1; 902 let Defs = [S0, S1, S2, RA, SP]; 903 let Uses = [SP]; 904} 905 906// Use Restore to increment SP since SP is not a Mip 16 register, this 907// is an easy way to do that which does not require a register. 908// 909let ra=0, s=0,s0=0,s1=0 in 910def RestoreIncSpF16: 911 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 912 "restore\t$frame_size", [], IILoad >, MayLoad { 913 let isCodeGenOnly = 1; 914 let Defs = [SP]; 915 let Uses = [SP]; 916} 917 918// 919// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 920// MIPS16e 921// Purpose: Save Registers and Set Up Stack Frame 922// To set up a stack frame on entry to a subroutine, 923// saving return address and static registers, and adjusting stack 924// 925let ra=1, s=1,s0=1,s1=1 in 926def SaveRaF16: 927 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 928 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore { 929 let isCodeGenOnly = 1; 930 let Uses = [RA, SP, S0, S1, S2]; 931 let Defs = [SP]; 932} 933 934// 935// Use Save to decrement the SP by a constant since SP is not 936// a Mips16 register. 937// 938let ra=0, s=0,s0=0,s1=0 in 939def SaveDecSpF16: 940 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 941 "save\t$frame_size", [], IIStore >, MayStore { 942 let isCodeGenOnly = 1; 943 let Uses = [SP]; 944 let Defs = [SP]; 945} 946// 947// Format: SB ry, offset(rx) MIPS16e 948// Purpose: Store Byte (Extended) 949// To store a byte to memory. 950// 951def SbRxRyOffMemX16: 952 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 953 954// 955// The Sel(T) instructions are pseudos 956// T means that they use T8 implicitly. 957// 958// 959// Format: SelBeqZ rd, rs, rt 960// Purpose: if rt==0, do nothing 961// else rs = rt 962// 963def SelBeqZ: Sel<"beqz">; 964 965// 966// Format: SelTBteqZCmp rd, rs, rl, rr 967// Purpose: b = Cmp rl, rr. 968// If b==0 then do nothing. 969// if b!=0 then rd = rs 970// 971def SelTBteqZCmp: SelT<"bteqz", "cmp">; 972 973// 974// Format: SelTBteqZCmpi rd, rs, rl, rr 975// Purpose: b = Cmpi rl, imm. 976// If b==0 then do nothing. 977// if b!=0 then rd = rs 978// 979def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 980 981// 982// Format: SelTBteqZSlt rd, rs, rl, rr 983// Purpose: b = Slt rl, rr. 984// If b==0 then do nothing. 985// if b!=0 then rd = rs 986// 987def SelTBteqZSlt: SelT<"bteqz", "slt">; 988 989// 990// Format: SelTBteqZSlti rd, rs, rl, rr 991// Purpose: b = Slti rl, imm. 992// If b==0 then do nothing. 993// if b!=0 then rd = rs 994// 995def SelTBteqZSlti: SeliT<"bteqz", "slti">; 996 997// 998// Format: SelTBteqZSltu rd, rs, rl, rr 999// Purpose: b = Sltu rl, rr. 1000// If b==0 then do nothing. 1001// if b!=0 then rd = rs 1002// 1003def SelTBteqZSltu: SelT<"bteqz", "sltu">; 1004 1005// 1006// Format: SelTBteqZSltiu rd, rs, rl, rr 1007// Purpose: b = Sltiu rl, imm. 1008// If b==0 then do nothing. 1009// if b!=0 then rd = rs 1010// 1011def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 1012 1013// 1014// Format: SelBnez rd, rs, rt 1015// Purpose: if rt!=0, do nothing 1016// else rs = rt 1017// 1018def SelBneZ: Sel<"bnez">; 1019 1020// 1021// Format: SelTBtneZCmp rd, rs, rl, rr 1022// Purpose: b = Cmp rl, rr. 1023// If b!=0 then do nothing. 1024// if b0=0 then rd = rs 1025// 1026def SelTBtneZCmp: SelT<"btnez", "cmp">; 1027 1028// 1029// Format: SelTBtnezCmpi rd, rs, rl, rr 1030// Purpose: b = Cmpi rl, imm. 1031// If b!=0 then do nothing. 1032// if b==0 then rd = rs 1033// 1034def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1035 1036// 1037// Format: SelTBtneZSlt rd, rs, rl, rr 1038// Purpose: b = Slt rl, rr. 1039// If b!=0 then do nothing. 1040// if b==0 then rd = rs 1041// 1042def SelTBtneZSlt: SelT<"btnez", "slt">; 1043 1044// 1045// Format: SelTBtneZSlti rd, rs, rl, rr 1046// Purpose: b = Slti rl, imm. 1047// If b!=0 then do nothing. 1048// if b==0 then rd = rs 1049// 1050def SelTBtneZSlti: SeliT<"btnez", "slti">; 1051 1052// 1053// Format: SelTBtneZSltu rd, rs, rl, rr 1054// Purpose: b = Sltu rl, rr. 1055// If b!=0 then do nothing. 1056// if b==0 then rd = rs 1057// 1058def SelTBtneZSltu: SelT<"btnez", "sltu">; 1059 1060// 1061// Format: SelTBtneZSltiu rd, rs, rl, rr 1062// Purpose: b = Slti rl, imm. 1063// If b!=0 then do nothing. 1064// if b==0 then rd = rs 1065// 1066def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1067// 1068// 1069// Format: SH ry, offset(rx) MIPS16e 1070// Purpose: Store Halfword (Extended) 1071// To store a halfword to memory. 1072// 1073def ShRxRyOffMemX16: 1074 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1075 1076// 1077// Format: SLL rx, ry, sa MIPS16e 1078// Purpose: Shift Word Left Logical (Extended) 1079// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 1080// 1081def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1082 1083// 1084// Format: SLLV ry, rx MIPS16e 1085// Purpose: Shift Word Left Logical Variable 1086// To execute a left-shift of a word by a variable number of bits. 1087// 1088def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1089 1090// Format: SLTI rx, immediate MIPS16e 1091// Purpose: Set on Less Than Immediate 1092// To record the result of a less-than comparison with a constant. 1093// 1094// 1095def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1096 let Defs = [T8]; 1097} 1098 1099// 1100// Format: SLTI rx, immediate MIPS16e 1101// Purpose: Set on Less Than Immediate (Extended) 1102// To record the result of a less-than comparison with a constant. 1103// 1104// 1105def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1106 let Defs = [T8]; 1107} 1108 1109def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1110 1111// Format: SLTIU rx, immediate MIPS16e 1112// Purpose: Set on Less Than Immediate Unsigned 1113// To record the result of a less-than comparison with a constant. 1114// 1115// 1116def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1117 let Defs = [T8]; 1118} 1119 1120// 1121// Format: SLTI rx, immediate MIPS16e 1122// Purpose: Set on Less Than Immediate Unsigned (Extended) 1123// To record the result of a less-than comparison with a constant. 1124// 1125// 1126def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1127 let Defs = [T8]; 1128} 1129// 1130// Format: SLTIU rx, immediate MIPS16e 1131// Purpose: Set on Less Than Immediate Unsigned (Extended) 1132// To record the result of a less-than comparison with a constant. 1133// 1134def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1135 1136// 1137// Format: SLT rx, ry MIPS16e 1138// Purpose: Set on Less Than 1139// To record the result of a less-than comparison. 1140// 1141def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{ 1142 let Defs = [T8]; 1143} 1144 1145def SltCCRxRy16: FCCRR16_ins<"slt">; 1146 1147// Format: SLTU rx, ry MIPS16e 1148// Purpose: Set on Less Than Unsigned 1149// To record the result of an unsigned less-than comparison. 1150// 1151def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{ 1152 let Defs = [T8]; 1153} 1154 1155def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1156 let isCodeGenOnly=1; 1157 let Defs = [T8]; 1158} 1159 1160 1161def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1162// 1163// Format: SRAV ry, rx MIPS16e 1164// Purpose: Shift Word Right Arithmetic Variable 1165// To execute an arithmetic right-shift of a word by a variable 1166// number of bits. 1167// 1168def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1169 1170 1171// 1172// Format: SRA rx, ry, sa MIPS16e 1173// Purpose: Shift Word Right Arithmetic (Extended) 1174// To execute an arithmetic right-shift of a word by a fixed 1175// number of bits—1 to 8 bits. 1176// 1177def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1178 1179 1180// 1181// Format: SRLV ry, rx MIPS16e 1182// Purpose: Shift Word Right Logical Variable 1183// To execute a logical right-shift of a word by a variable 1184// number of bits. 1185// 1186def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1187 1188 1189// 1190// Format: SRL rx, ry, sa MIPS16e 1191// Purpose: Shift Word Right Logical (Extended) 1192// To execute a logical right-shift of a word by a fixed 1193// number of bits—1 to 31 bits. 1194// 1195def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1196 1197// 1198// Format: SUBU rz, rx, ry MIPS16e 1199// Purpose: Subtract Unsigned Word 1200// To subtract 32-bit integers 1201// 1202def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1203 1204// 1205// Format: SW ry, offset(rx) MIPS16e 1206// Purpose: Store Word (Extended) 1207// To store a word to memory. 1208// 1209def SwRxRyOffMemX16: 1210 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1211 1212// 1213// Format: SW rx, offset(sp) MIPS16e 1214// Purpose: Store Word rx (SP-Relative) 1215// To store an SP-relative word to memory. 1216// 1217def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins 1218 <0b11010, "sw", IIStore>, MayStore; 1219 1220// 1221// 1222// Format: XOR rx, ry MIPS16e 1223// Purpose: Xor 1224// To do a bitwise logical XOR. 1225// 1226def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1227 1228class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1229 let Predicates = [InMips16Mode]; 1230} 1231 1232// Unary Arith/Logic 1233// 1234class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1235 Mips16Pat<(OpNode CPU16Regs:$r), 1236 (I CPU16Regs:$r)>; 1237 1238def: ArithLogicU_pat<not, NotRxRy16>; 1239def: ArithLogicU_pat<ineg, NegRxRy16>; 1240 1241class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1242 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1243 (I CPU16Regs:$l, CPU16Regs:$r)>; 1244 1245def: ArithLogic16_pat<add, AdduRxRyRz16>; 1246def: ArithLogic16_pat<and, AndRxRxRy16>; 1247def: ArithLogic16_pat<mul, MultRxRyRz16>; 1248def: ArithLogic16_pat<or, OrRxRxRy16>; 1249def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1250def: ArithLogic16_pat<xor, XorRxRxRy16>; 1251 1252// Arithmetic and logical instructions with 2 register operands. 1253 1254class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1255 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1256 (I CPU16Regs:$in, imm_type:$imm)>; 1257 1258def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1259def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1260def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1261def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1262def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1263 1264class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1265 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1266 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1267 1268def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1269def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1270def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1271 1272class LoadM16_pat<PatFrag OpNode, Instruction I> : 1273 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1274 1275def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1276def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1277def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1278def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1279def: LoadM16_pat<load, LwRxRyOffMemX16>; 1280 1281class StoreM16_pat<PatFrag OpNode, Instruction I> : 1282 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1283 (I CPU16Regs:$r, addr16:$addr)>; 1284 1285def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1286def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1287def: StoreM16_pat<store, SwRxRyOffMemX16>; 1288 1289// Unconditional branch 1290class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1291 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1292 let Predicates = [InMips16Mode]; 1293 } 1294 1295def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1296 (Jal16 tglobaladdr:$dst)>; 1297 1298def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1299 (Jal16 texternalsym:$dst)>; 1300 1301// Indirect branch 1302def: Mips16Pat< 1303 (brind CPU16Regs:$rs), 1304 (JrcRx16 CPU16Regs:$rs)>; 1305 1306// Jump and Link (Call) 1307let isCall=1, hasDelaySlot=0 in 1308def JumpLinkReg16: 1309 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1310 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1311 1312// Mips16 pseudos 1313let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1314 hasExtraSrcRegAllocReq = 1 in 1315def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1316 1317 1318// setcc patterns 1319 1320class SetCC_R16<PatFrag cond_op, Instruction I>: 1321 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1322 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1323 1324class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1325 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1326 (I CPU16Regs:$rx, imm_type:$imm16)>; 1327 1328 1329def: Mips16Pat<(i32 addr16:$addr), 1330 (AddiuRxRyOffMemX16 addr16:$addr)>; 1331 1332 1333// Large (>16 bit) immediate loads 1334def : Mips16Pat<(i32 imm:$imm), 1335 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1336 (LiRxImmX16 (LO16 imm:$imm)))>; 1337 1338// Carry MipsPatterns 1339def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1340 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1341def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1342 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1343def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1344 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1345 1346// 1347// Some branch conditional patterns are not generated by llvm at this time. 1348// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1349// comparison they are used and for unsigned a different pattern is used. 1350// I am pushing upstream from the full mips16 port and it seemed that I needed 1351// these earlier and the mips32 port has these but now I cannot create test 1352// cases that use these patterns. While I sort this all out I will leave these 1353// extra patterns commented out and if I can be sure they are really not used, 1354// I will delete the code. I don't want to check the code in uncommented without 1355// a valid test case. In some cases, the compiler is generating patterns with 1356// setcc instead and earlier I had implemented setcc first so may have masked 1357// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1358// figure out how to enable the brcond patterns or else possibly new 1359// combinations of of brcond and setcc. 1360// 1361// 1362// bcond-seteq 1363// 1364def: Mips16Pat 1365 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1366 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1367 >; 1368 1369 1370def: Mips16Pat 1371 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1372 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1373 >; 1374 1375def: Mips16Pat 1376 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1377 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1378 >; 1379 1380// 1381// bcond-setgt (do we need to have this pair of setlt, setgt??) 1382// 1383def: Mips16Pat 1384 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1385 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1386 >; 1387 1388// 1389// bcond-setge 1390// 1391def: Mips16Pat 1392 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1393 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1394 >; 1395 1396// 1397// never called because compiler transforms a >= k to a > (k-1) 1398def: Mips16Pat 1399 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1400 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1401 >; 1402 1403// 1404// bcond-setlt 1405// 1406def: Mips16Pat 1407 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1408 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1409 >; 1410 1411def: Mips16Pat 1412 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1413 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1414 >; 1415 1416// 1417// bcond-setle 1418// 1419def: Mips16Pat 1420 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1421 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1422 >; 1423 1424// 1425// bcond-setne 1426// 1427def: Mips16Pat 1428 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1429 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1430 >; 1431 1432def: Mips16Pat 1433 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1434 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1435 >; 1436 1437def: Mips16Pat 1438 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1439 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1440 >; 1441 1442// 1443// This needs to be there but I forget which code will generate it 1444// 1445def: Mips16Pat 1446 <(brcond CPU16Regs:$rx, bb:$targ16), 1447 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1448 >; 1449 1450// 1451 1452// 1453// bcond-setugt 1454// 1455//def: Mips16Pat 1456// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1457// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1458// >; 1459 1460// 1461// bcond-setuge 1462// 1463//def: Mips16Pat 1464// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1465// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1466// >; 1467 1468 1469// 1470// bcond-setult 1471// 1472//def: Mips16Pat 1473// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1474// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1475// >; 1476 1477def: UncondBranch16_pat<br, BimmX16>; 1478 1479// Small immediates 1480def: Mips16Pat<(i32 immSExt16:$in), 1481 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1482 1483def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1484 1485// 1486// MipsDivRem 1487// 1488def: Mips16Pat 1489 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), 1490 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1491 1492// 1493// MipsDivRemU 1494// 1495def: Mips16Pat 1496 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry), 1497 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1498 1499// signed a,b 1500// x = (a>=b)?x:y 1501// 1502// if !(a < b) x = y 1503// 1504def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1505 CPU16Regs:$x, CPU16Regs:$y), 1506 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1507 CPU16Regs:$a, CPU16Regs:$b)>; 1508 1509// signed a,b 1510// x = (a>b)?x:y 1511// 1512// if (b < a) x = y 1513// 1514def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1515 CPU16Regs:$x, CPU16Regs:$y), 1516 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1517 CPU16Regs:$b, CPU16Regs:$a)>; 1518 1519// unsigned a,b 1520// x = (a>=b)?x:y 1521// 1522// if !(a < b) x = y; 1523// 1524def : Mips16Pat< 1525 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1526 CPU16Regs:$x, CPU16Regs:$y), 1527 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1528 CPU16Regs:$a, CPU16Regs:$b)>; 1529 1530// unsigned a,b 1531// x = (a>b)?x:y 1532// 1533// if (b < a) x = y 1534// 1535def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1536 CPU16Regs:$x, CPU16Regs:$y), 1537 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1538 CPU16Regs:$b, CPU16Regs:$a)>; 1539 1540// signed 1541// x = (a >= k)?x:y 1542// due to an llvm optimization, i don't think that this will ever 1543// be used. This is transformed into x = (a > k-1)?x:y 1544// 1545// 1546 1547//def : Mips16Pat< 1548// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1549// CPU16Regs:$T, CPU16Regs:$F), 1550// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1551// CPU16Regs:$lhs, immSExt16:$rhs)>; 1552 1553//def : Mips16Pat< 1554// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1555// CPU16Regs:$T, CPU16Regs:$F), 1556// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1557// CPU16Regs:$lhs, immSExt16:$rhs)>; 1558 1559// signed 1560// x = (a < k)?x:y 1561// 1562// if !(a < k) x = y; 1563// 1564def : Mips16Pat< 1565 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1566 CPU16Regs:$x, CPU16Regs:$y), 1567 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1568 CPU16Regs:$a, immSExt16:$b)>; 1569 1570 1571// 1572// 1573// signed 1574// x = (a <= b)? x : y 1575// 1576// if (b < a) x = y 1577// 1578def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1579 CPU16Regs:$x, CPU16Regs:$y), 1580 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1581 CPU16Regs:$b, CPU16Regs:$a)>; 1582 1583// 1584// unnsigned 1585// x = (a <= b)? x : y 1586// 1587// if (b < a) x = y 1588// 1589def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1590 CPU16Regs:$x, CPU16Regs:$y), 1591 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1592 CPU16Regs:$b, CPU16Regs:$a)>; 1593 1594// 1595// signed/unsigned 1596// x = (a == b)? x : y 1597// 1598// if (a != b) x = y 1599// 1600def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1601 CPU16Regs:$x, CPU16Regs:$y), 1602 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1603 CPU16Regs:$b, CPU16Regs:$a)>; 1604 1605// 1606// signed/unsigned 1607// x = (a == 0)? x : y 1608// 1609// if (a != 0) x = y 1610// 1611def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1612 CPU16Regs:$x, CPU16Regs:$y), 1613 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1614 CPU16Regs:$a)>; 1615 1616 1617// 1618// signed/unsigned 1619// x = (a == k)? x : y 1620// 1621// if (a != k) x = y 1622// 1623def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1624 CPU16Regs:$x, CPU16Regs:$y), 1625 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1626 CPU16Regs:$a, immZExt16:$k)>; 1627 1628 1629// 1630// signed/unsigned 1631// x = (a != b)? x : y 1632// 1633// if (a == b) x = y 1634// 1635// 1636def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1637 CPU16Regs:$x, CPU16Regs:$y), 1638 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1639 CPU16Regs:$b, CPU16Regs:$a)>; 1640 1641// 1642// signed/unsigned 1643// x = (a != 0)? x : y 1644// 1645// if (a == 0) x = y 1646// 1647def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1648 CPU16Regs:$x, CPU16Regs:$y), 1649 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1650 CPU16Regs:$a)>; 1651 1652// signed/unsigned 1653// x = (a)? x : y 1654// 1655// if (!a) x = y 1656// 1657def : Mips16Pat<(select CPU16Regs:$a, 1658 CPU16Regs:$x, CPU16Regs:$y), 1659 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1660 CPU16Regs:$a)>; 1661 1662 1663// 1664// signed/unsigned 1665// x = (a != k)? x : y 1666// 1667// if (a == k) x = y 1668// 1669def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1670 CPU16Regs:$x, CPU16Regs:$y), 1671 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1672 CPU16Regs:$a, immZExt16:$k)>; 1673 1674// 1675// When writing C code to test setxx these patterns, 1676// some will be transformed into 1677// other things. So we test using C code but using -O3 and -O0 1678// 1679// seteq 1680// 1681def : Mips16Pat 1682 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1683 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1684 1685def : Mips16Pat 1686 <(seteq CPU16Regs:$lhs, 0), 1687 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1688 1689 1690// 1691// setge 1692// 1693 1694def: Mips16Pat 1695 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1696 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1697 (LiRxImmX16 1))>; 1698 1699// 1700// For constants, llvm transforms this to: 1701// x > (k -1) and then reverses the operands to use setlt. So this pattern 1702// is not used now by the compiler. (Presumably checking that k-1 does not 1703// overflow). The compiler never uses this at a the current time, due to 1704// other optimizations. 1705// 1706//def: Mips16Pat 1707// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1708// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1709// (LiRxImmX16 1))>; 1710 1711// This catches the x >= -32768 case by transforming it to x > -32769 1712// 1713def: Mips16Pat 1714 <(setgt CPU16Regs:$lhs, -32769), 1715 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1716 (LiRxImmX16 1))>; 1717 1718// 1719// setgt 1720// 1721// 1722 1723def: Mips16Pat 1724 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1725 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1726 1727// 1728// setle 1729// 1730def: Mips16Pat 1731 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1732 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1733 1734// 1735// setlt 1736// 1737def: SetCC_R16<setlt, SltCCRxRy16>; 1738 1739def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1740 1741// 1742// setne 1743// 1744def : Mips16Pat 1745 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1746 (SltuCCRxRy16 (LiRxImmX16 0), 1747 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1748 1749 1750// 1751// setuge 1752// 1753def: Mips16Pat 1754 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1755 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1756 (LiRxImmX16 1))>; 1757 1758// this pattern will never be used because the compiler will transform 1759// x >= k to x > (k - 1) and then use SLT 1760// 1761//def: Mips16Pat 1762// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1763// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1764// (LiRxImmX16 1))>; 1765 1766// 1767// setugt 1768// 1769def: Mips16Pat 1770 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1771 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1772 1773// 1774// setule 1775// 1776def: Mips16Pat 1777 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1778 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1779 1780// 1781// setult 1782// 1783def: SetCC_R16<setult, SltuCCRxRy16>; 1784 1785def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1786 1787def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1788 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1789 1790// hi/lo relocs 1791def : Mips16Pat<(MipsHi tblockaddress:$in), 1792 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>; 1793def : Mips16Pat<(MipsHi tglobaladdr:$in), 1794 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1795def : Mips16Pat<(MipsHi tjumptable:$in), 1796 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1797def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1798 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1799 1800def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>; 1801 1802// wrapper_pic 1803class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1804 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1805 (ADDiuOp RC:$gp, node:$in)>; 1806 1807 1808def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1809def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1810 1811def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1812 (LbuRxRyOffMemX16 addr16:$src)>; 1813def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1814 (LhuRxRyOffMemX16 addr16:$src)>; 1815 1816def: Mips16Pat<(trap), (Break16)>; 1817 1818def GotPrologue16: 1819 MipsPseudo16< 1820 (outs CPU16Regs:$rh, CPU16Regs:$rl), 1821 (ins simm16:$immHi, simm16:$immLo), 1822 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ; 1823