Mips16InstrInfo.td revision 603f69dc2c69ac3f4040e125febd3925dec2bcb2
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14def uimm5 : Operand<i8> { 15 let DecoderMethod= "DecodeSimm16"; 16} 17 18// 19// RRR-type instruction format 20// 21 22class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 23 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 24 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 25 26// 27// I8_MOV32R instruction format (used only by MOV32R instruction) 28// 29class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 30 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 31 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 32 33// 34// EXT-RI instruction format 35// 36 37class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 38 InstrItinClass itin>: 39 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 40 !strconcat(asmstr, asmstr2), [], itin>; 41 42class FEXT_RI16_ins<bits<5> _op, string asmstr, 43 InstrItinClass itin>: 44 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 45 46class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 47 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 48 49 50class FEXT_2RI16_ins<bits<5> _op, string asmstr, 51 InstrItinClass itin>: 52 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 53 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 54 let Constraints = "$rx_ = $rx"; 55} 56 57 58// 59// RR-type instruction format 60// 61let rx=0 in 62class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 63 string asmstr, InstrItinClass itin>: 64 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 65 [], itin> ; 66 67// 68// EXT-RRI instruction format 69// 70 71class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 72 InstrItinClass itin>: 73 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 74 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 75 76// 77// EXT-SHIFT instruction format 78// 79class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 80 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa), 81 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 82 83// 84// Address operand 85def mem16 : Operand<i32> { 86 let PrintMethod = "printMemOperand"; 87 let MIOperandInfo = (ops CPU16Regs, simm16); 88 let EncoderMethod = "getMemEncoding"; 89} 90 91// 92 93// Format: ADDIU rx, immediate MIPS16e 94// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 95// To add a constant to a 32-bit integer. 96// 97class AddiuRxImmX16_base: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 98def AddiuRxImmX16: AddiuRxImmX16_base; 99 100 101class AddiuRxRxImmX16_base: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>; 102def AddiuRxRxImmX16: AddiuRxRxImmX16_base; 103 104// 105 106// Format: ADDIU rx, pc, immediate MIPS16e 107// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 108// To add a constant to the program counter. 109// 110class AddiuRxPcImmX16_base : FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 111def AddiuRxPcImmX16 : AddiuRxPcImmX16_base; 112// 113// Format: ADDU rz, rx, ry MIPS16e 114// Purpose: Add Unsigned Word (3-Operand) 115// To add 32-bit integers. 116// 117 118class AdduRxRyRz16_base: FRRR16_ins<01, "addu", IIAlu>; 119def AdduRxRyRz16: AdduRxRyRz16_base; 120 121// 122// Format: JR ra MIPS16e 123// Purpose: Jump Register Through Register ra 124// To execute a branch to the instruction address in the return 125// address register. 126// 127 128def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>; 129 130// 131// Format: LI rx, immediate MIPS16e 132// Purpose: Load Immediate (Extended) 133// To load a constant into a GPR. 134// 135def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 136 137// 138// Format: LW ry, offset(rx) MIPS16e 139// Purpose: Load Word (Extended) 140// To load a word from memory as a signed value. 141// 142class LwRxRyOffMemX16_base: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>; 143def LwRxRyOffMemX16: LwRxRyOffMemX16_base; 144 145// 146// Format: MOVE r32, rz MIPS16e 147// Purpose: Move 148// To move the contents of a GPR to a GPR. 149// 150def Mov32R16: FI8_MOV32R16_ins<"move", IIAlu>; 151// 152// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 153// (All args are optional) MIPS16e 154// Purpose: Restore Registers and Deallocate Stack Frame 155// To deallocate a stack frame before exit from a subroutine, 156// restoring return address and static registers, and adjusting 157// stack 158// 159 160// fixed form for restoring RA and the frame 161// for direct object emitter, encoding needs to be adjusted for the 162// frame size 163// 164let ra=1, s=0,s0=0,s1=0 in 165def RestoreRaF16: 166 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 167 "restore \t$$ra, $frame_size", [], IILoad >; 168 169// 170// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 171// MIPS16e 172// Purpose: Save Registers and Set Up Stack Frame 173// To set up a stack frame on entry to a subroutine, 174// saving return address and static registers, and adjusting stack 175// 176let ra=1, s=1,s0=0,s1=0 in 177def SaveRaF16: 178 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 179 "save \t$$ra, $frame_size", [], IILoad >; 180 181// 182// Format: SLL rx, ry, sa MIPS16e 183// Purpose: Shift Word Left Logical (Extended) 184// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 185// 186def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 187 188// 189// Format: SW ry, offset(rx) MIPS16e 190// Purpose: Store Word (Extended) 191// To store a word to memory. 192// 193class SwRxRyOffMemX16_base: FEXT_RRI16_mem_ins<0b11011, "sw", mem16, IIAlu>; 194def SwRxRyOffMemX16: SwRxRyOffMemX16_base; 195 196class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 197 let Predicates = [InMips16Mode]; 198} 199 200class ArithLogicR16Defs<SDNode OpNode, bit isComm = 0> { 201 dag OutOperandList = (outs CPU16Regs:$rz); 202 dag InOperandList = (ins CPU16Regs:$rx, CPU16Regs:$ry); 203 list<dag> Pattern = [(set CPU16Regs:$rz, 204 (OpNode CPU16Regs:$rx, CPU16Regs:$ry))]; 205} 206 207multiclass ArithLogicR16_base { 208 def _add: AdduRxRyRz16_base, ArithLogicR16Defs<add, 1>; 209} 210 211defm ArithLogicR16_patt : ArithLogicR16_base; 212 213class LoadM16Defs<PatFrag OpNode, Operand _MemOpnd, bit Pseudo=0> { 214 bit isPseudo = Pseudo; 215 Operand MemOpnd = _MemOpnd; 216 dag OutOperandList = (outs CPU16Regs:$ry); 217 dag InOperandList = (ins MemOpnd:$addr); 218 list<dag> Pattern = [(set CPU16Regs:$ry, (OpNode addr:$addr))]; 219} 220 221multiclass LoadM16_base { 222 def _LwRxRyOffMemX16: LwRxRyOffMemX16_base, LoadM16Defs<load_a, mem16>; 223} 224 225defm LoadM16: LoadM16_base; 226 227class StoreM16Defs<PatFrag OpNode, Operand _MemOpnd, bit Pseudo=0> { 228 bit isPseudo = Pseudo; 229 Operand MemOpnd = _MemOpnd; 230 dag OutOperandList = (outs ); 231 dag InOperandList = (ins CPU16Regs:$ry, MemOpnd:$addr); 232 list<dag> Pattern = [(OpNode CPU16Regs:$ry, addr:$addr)]; 233} 234 235multiclass StoreM16_base { 236 def _SwRxRyOffMemX16: SwRxRyOffMemX16_base, StoreM16Defs<store_a, mem16>; 237} 238 239defm StoreM16: StoreM16_base; 240 241// Jump and Link (Call) 242let isCall=1, hasDelaySlot=1 in 243def JumpLinkReg16: 244 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 245 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 246 247// Mips16 pseudos 248let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 249 hasExtraSrcRegAllocReq = 1 in 250def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 251 252// Small immediates 253def : Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 254 255 256def : Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 257 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 258