Mips16InstrInfo.td revision 6e3443eed44a463bdbc9d2e01f01b85f07d5ca40
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16Regs, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// Compare a register and immediate and place result in CC 36// Implicit use of T8 37// 38// EXT-CCRR Instruction format 39// 40class FEXT_CCRXI16_ins<bits<5> _op, string asmstr, 41 InstrItinClass itin>: 42 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 43 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> { 44 let isCodeGenOnly=1; 45} 46 47// JAL and JALX instruction format 48// 49class FJAL16_ins<bits<1> _X, string asmstr, 50 InstrItinClass itin>: 51 FJAL16<_X, (outs), (ins simm20:$imm), 52 !strconcat(asmstr, "\t$imm\n\tnop"),[], 53 itin> { 54 let isCodeGenOnly=1; 55} 56// 57// EXT-I instruction format 58// 59class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 60 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 61 !strconcat(asmstr, "\t$imm16"),[], itin>; 62 63// 64// EXT-I8 instruction format 65// 66 67class FEXT_I816_ins_base<bits<3> _func, string asmstr, 68 string asmstr2, InstrItinClass itin>: 69 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 70 [], itin>; 71 72class FEXT_I816_ins<bits<3> _func, string asmstr, 73 InstrItinClass itin>: 74 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 75 76class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 77 InstrItinClass itin>: 78 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 79 80// 81// Assembler formats in alphabetical order. 82// Natural and pseudos are mixed together. 83// 84// Compare two registers and place result in CC 85// Implicit use of T8 86// 87// CC-RR Instruction format 88// 89class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 90 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 91 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> { 92 let isCodeGenOnly=1; 93} 94 95// 96// EXT-RI instruction format 97// 98 99class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 100 InstrItinClass itin>: 101 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 102 !strconcat(asmstr, asmstr2), [], itin>; 103 104class FEXT_RI16_ins<bits<5> _op, string asmstr, 105 InstrItinClass itin>: 106 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 107 108class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 109 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 110 111class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 112 InstrItinClass itin>: 113 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 114 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 115 116class FEXT_2RI16_ins<bits<5> _op, string asmstr, 117 InstrItinClass itin>: 118 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 119 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 120 let Constraints = "$rx_ = $rx"; 121} 122 123 124// this has an explicit sp argument that we ignore to work around a problem 125// in the compiler 126class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 127 InstrItinClass itin>: 128 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 129 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 130 131// 132// EXT-RRI instruction format 133// 134 135class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 136 InstrItinClass itin>: 137 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 138 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 139 140class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 141 InstrItinClass itin>: 142 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 143 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 144 145// 146// 147// EXT-RRI-A instruction format 148// 149 150class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 151 InstrItinClass itin>: 152 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 153 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 154 155// 156// EXT-SHIFT instruction format 157// 158class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 159 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 160 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 161 162// 163// EXT-T8I8 164// 165class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2, 166 InstrItinClass itin>: 167 FEXT_I816<_func, (outs), 168 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 169 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 170 !strconcat(asmstr, "\t$imm"))),[], itin> { 171 let isCodeGenOnly=1; 172} 173 174// 175// EXT-T8I8I 176// 177class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2, 178 InstrItinClass itin>: 179 FEXT_I816<_func, (outs), 180 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 181 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 182 !strconcat(asmstr, "\t$targ"))), [], itin> { 183 let isCodeGenOnly=1; 184} 185// 186 187 188// 189// I8_MOVR32 instruction format (used only by the MOVR32 instructio 190// 191class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 192 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 193 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 194 195// 196// I8_MOV32R instruction format (used only by MOV32R instruction) 197// 198 199class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 200 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 201 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 202 203// 204// This are pseudo formats for multiply 205// This first one can be changed to non pseudo now. 206// 207// MULT 208// 209class FMULT16_ins<string asmstr, InstrItinClass itin> : 210 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 211 !strconcat(asmstr, "\t$rx, $ry"), []>; 212 213// 214// MULT-LO 215// 216class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 217 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 218 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 219 let isCodeGenOnly=1; 220} 221 222// 223// RR-type instruction format 224// 225 226class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 227 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 228 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 229} 230 231class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 232 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 233 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ; 234 235// 236// maybe refactor but need a $zero as a dummy first parameter 237// 238class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 239 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 240 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 241 242class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 243 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 244 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 245 246 247class FRR16_M_ins<bits<5> f, string asmstr, 248 InstrItinClass itin> : 249 FRR16<f, (outs CPU16Regs:$rx), (ins), 250 !strconcat(asmstr, "\t$rx"), [], itin>; 251 252class FRxRxRy16_ins<bits<5> f, string asmstr, 253 InstrItinClass itin> : 254 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 255 !strconcat(asmstr, "\t$rz, $ry"), 256 [], itin> { 257 let Constraints = "$rx = $rz"; 258} 259 260let rx=0 in 261class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 262 string asmstr, InstrItinClass itin>: 263 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 264 [], itin> ; 265 266 267class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 268 string asmstr, InstrItinClass itin>: 269 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 270 !strconcat(asmstr, "\t $rx"), [], itin> ; 271 272// 273// RRR-type instruction format 274// 275 276class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 277 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 278 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 279 280// 281// These Sel patterns support the generation of conditional move 282// pseudo instructions. 283// 284// The nomenclature uses the components making up the pseudo and may 285// be a bit counter intuitive when compared with the end result we seek. 286// For example using a bqez in the example directly below results in the 287// conditional move being done if the tested register is not zero. 288// I considered in easier to check by keeping the pseudo consistent with 289// it's components but it could have been done differently. 290// 291// The simplest case is when can test and operand directly and do the 292// conditional move based on a simple mips16 conditional 293// branch instruction. 294// for example: 295// if $op == beqz or bnez: 296// 297// $op1 $rt, .+4 298// move $rd, $rs 299// 300// if $op == beqz, then if $rt != 0, then the conditional assignment 301// $rd = $rs is done. 302 303// if $op == bnez, then if $rt == 0, then the conditional assignment 304// $rd = $rs is done. 305// 306// So this pseudo class only has one operand, i.e. op 307// 308class Sel<bits<5> f1, string op, InstrItinClass itin>: 309 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 310 CPU16Regs:$rt), 311 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin, 312 Pseudo16> { 313 let isCodeGenOnly=1; 314 let Constraints = "$rd = $rd_"; 315} 316 317// 318// The next two instruction classes allow for an operand which tests 319// two operands and returns a value in register T8 and 320//then does a conditional branch based on the value of T8 321// 322 323// op2 can be cmpi or slti/sltiu 324// op1 can bteqz or btnez 325// the operands for op2 are a register and a signed constant 326// 327// $op2 $t, $imm ;test register t and branch conditionally 328// $op1 .+4 ;op1 is a conditional branch 329// move $rd, $rs 330// 331// 332class SeliT<bits<5> f1, string op1, bits<5> f2, string op2, 333 InstrItinClass itin>: 334 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 335 CPU16Regs:$rl, simm16:$imm), 336 !strconcat(op2, 337 !strconcat("\t$rl, $imm\n\t", 338 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 339 Pseudo16> { 340 let isCodeGenOnly=1; 341 let Constraints = "$rd = $rd_"; 342} 343 344// 345// op2 can be cmp or slt/sltu 346// op1 can be bteqz or btnez 347// the operands for op2 are two registers 348// op1 is a conditional branch 349// 350// 351// $op2 $rl, $rr ;test registers rl,rr 352// $op1 .+4 ;op2 is a conditional branch 353// move $rd, $rs 354// 355// 356class SelT<bits<5> f1, string op1, bits<5> f2, string op2, 357 InstrItinClass itin>: 358 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 359 CPU16Regs:$rl, CPU16Regs:$rr), 360 !strconcat(op2, 361 !strconcat("\t$rl, $rr\n\t", 362 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 363 Pseudo16> { 364 let isCodeGenOnly=1; 365 let Constraints = "$rd = $rd_"; 366} 367 368// 369// 32 bit constant 370// 371def imm32: Operand<i32>; 372 373def Constant32: 374 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 375 376def LwConstant32: 377 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm), 378 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 379 380 381// 382// Some general instruction class info 383// 384// 385 386class ArithLogic16Defs<bit isCom=0> { 387 bits<5> shamt = 0; 388 bit isCommutable = isCom; 389 bit isReMaterializable = 1; 390 bit neverHasSideEffects = 1; 391} 392 393class branch16 { 394 bit isBranch = 1; 395 bit isTerminator = 1; 396 bit isBarrier = 1; 397} 398 399class cbranch16 { 400 bit isBranch = 1; 401 bit isTerminator = 1; 402} 403 404class MayLoad { 405 bit mayLoad = 1; 406} 407 408class MayStore { 409 bit mayStore = 1; 410} 411// 412 413// Format: ADDIU rx, immediate MIPS16e 414// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 415// To add a constant to a 32-bit integer. 416// 417def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 418 419def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 420 ArithLogic16Defs<0>; 421 422def AddiuRxRyOffMemX16: 423 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 424 425// 426 427// Format: ADDIU rx, pc, immediate MIPS16e 428// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 429// To add a constant to the program counter. 430// 431def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 432 433// 434// Format: ADDIU sp, immediate MIPS16e 435// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 436// To add a constant to the stack pointer. 437// 438def AddiuSpImmX16 439 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 440 let Defs = [SP]; 441 let Uses = [SP]; 442} 443 444// 445// Format: ADDU rz, rx, ry MIPS16e 446// Purpose: Add Unsigned Word (3-Operand) 447// To add 32-bit integers. 448// 449 450def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 451 452// 453// Format: AND rx, ry MIPS16e 454// Purpose: AND 455// To do a bitwise logical AND. 456 457def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 458 459 460// 461// Format: BEQZ rx, offset MIPS16e 462// Purpose: Branch on Equal to Zero (Extended) 463// To test a GPR then do a PC-relative conditional branch. 464// 465def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 466 467// Format: B offset MIPS16e 468// Purpose: Unconditional Branch 469// To do an unconditional PC-relative branch. 470// 471def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 472 473// 474// Format: BNEZ rx, offset MIPS16e 475// Purpose: Branch on Not Equal to Zero (Extended) 476// To test a GPR then do a PC-relative conditional branch. 477// 478def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 479 480// 481// Format: BTEQZ offset MIPS16e 482// Purpose: Branch on T Equal to Zero (Extended) 483// To test special register T then do a PC-relative conditional branch. 484// 485def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; 486 487def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16; 488 489def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>, 490 cbranch16; 491 492def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16; 493 494def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16; 495 496def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16; 497 498def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>, 499 cbranch16; 500 501// 502// Format: BTNEZ offset MIPS16e 503// Purpose: Branch on T Not Equal to Zero (Extended) 504// To test special register T then do a PC-relative conditional branch. 505// 506def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; 507 508def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16; 509 510def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16; 511 512def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16; 513 514def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16; 515 516def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16; 517 518def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>, 519 cbranch16; 520 521// 522// Format: DIV rx, ry MIPS16e 523// Purpose: Divide Word 524// To divide 32-bit signed integers. 525// 526def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 527 let Defs = [HI, LO]; 528} 529 530// 531// Format: DIVU rx, ry MIPS16e 532// Purpose: Divide Unsigned Word 533// To divide 32-bit unsigned integers. 534// 535def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 536 let Defs = [HI, LO]; 537} 538// 539// Format: JAL target MIPS16e 540// Purpose: Jump and Link 541// To execute a procedure call within the current 256 MB-aligned 542// region and preserve the current ISA. 543// 544 545def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 546 let isBranch = 1; 547 let hasDelaySlot = 0; // not true, but we add the nop for now 548 let isTerminator=1; 549 let isBarrier=1; 550} 551 552// 553// Format: JR ra MIPS16e 554// Purpose: Jump Register Through Register ra 555// To execute a branch to the instruction address in the return 556// address register. 557// 558 559def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 560 let isBranch = 1; 561 let isIndirectBranch = 1; 562 let hasDelaySlot = 1; 563 let isTerminator=1; 564 let isBarrier=1; 565} 566 567def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> { 568 let isBranch = 1; 569 let isIndirectBranch = 1; 570 let isTerminator=1; 571 let isBarrier=1; 572} 573 574def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 575 let isBranch = 1; 576 let isIndirectBranch = 1; 577 let isTerminator=1; 578 let isBarrier=1; 579} 580// 581// Format: LB ry, offset(rx) MIPS16e 582// Purpose: Load Byte (Extended) 583// To load a byte from memory as a signed value. 584// 585def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; 586 587// 588// Format: LBU ry, offset(rx) MIPS16e 589// Purpose: Load Byte Unsigned (Extended) 590// To load a byte from memory as a unsigned value. 591// 592def LbuRxRyOffMemX16: 593 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad; 594 595// 596// Format: LH ry, offset(rx) MIPS16e 597// Purpose: Load Halfword signed (Extended) 598// To load a halfword from memory as a signed value. 599// 600def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; 601 602// 603// Format: LHU ry, offset(rx) MIPS16e 604// Purpose: Load Halfword unsigned (Extended) 605// To load a halfword from memory as an unsigned value. 606// 607def LhuRxRyOffMemX16: 608 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad; 609 610// 611// Format: LI rx, immediate MIPS16e 612// Purpose: Load Immediate (Extended) 613// To load a constant into a GPR. 614// 615def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 616 617// 618// Format: LW ry, offset(rx) MIPS16e 619// Purpose: Load Word (Extended) 620// To load a word from memory as a signed value. 621// 622def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad; 623 624// Format: LW rx, offset(sp) MIPS16e 625// Purpose: Load Word (SP-Relative, Extended) 626// To load an SP-relative word from memory as a signed value. 627// 628def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{ 629 let Uses = [SP]; 630} 631 632// 633// Format: MOVE r32, rz MIPS16e 634// Purpose: Move 635// To move the contents of a GPR to a GPR. 636// 637def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 638 639// 640// Format: MOVE ry, r32 MIPS16e 641//Purpose: Move 642// To move the contents of a GPR to a GPR. 643// 644def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 645 646// 647// Format: MFHI rx MIPS16e 648// Purpose: Move From HI Register 649// To copy the special purpose HI register to a GPR. 650// 651def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 652 let Uses = [HI]; 653 let neverHasSideEffects = 1; 654} 655 656// 657// Format: MFLO rx MIPS16e 658// Purpose: Move From LO Register 659// To copy the special purpose LO register to a GPR. 660// 661def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 662 let Uses = [LO]; 663 let neverHasSideEffects = 1; 664} 665 666// 667// Pseudo Instruction for mult 668// 669def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 670 let isCommutable = 1; 671 let neverHasSideEffects = 1; 672 let Defs = [HI, LO]; 673} 674 675def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 676 let isCommutable = 1; 677 let neverHasSideEffects = 1; 678 let Defs = [HI, LO]; 679} 680 681// 682// Format: MULT rx, ry MIPS16e 683// Purpose: Multiply Word 684// To multiply 32-bit signed integers. 685// 686def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 687 let isCommutable = 1; 688 let neverHasSideEffects = 1; 689 let Defs = [HI, LO]; 690} 691 692// 693// Format: MULTU rx, ry MIPS16e 694// Purpose: Multiply Unsigned Word 695// To multiply 32-bit unsigned integers. 696// 697def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 698 let isCommutable = 1; 699 let neverHasSideEffects = 1; 700 let Defs = [HI, LO]; 701} 702 703// 704// Format: NEG rx, ry MIPS16e 705// Purpose: Negate 706// To negate an integer value. 707// 708def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 709 710// 711// Format: NOT rx, ry MIPS16e 712// Purpose: Not 713// To complement an integer value 714// 715def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 716 717// 718// Format: OR rx, ry MIPS16e 719// Purpose: Or 720// To do a bitwise logical OR. 721// 722def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 723 724// 725// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 726// (All args are optional) MIPS16e 727// Purpose: Restore Registers and Deallocate Stack Frame 728// To deallocate a stack frame before exit from a subroutine, 729// restoring return address and static registers, and adjusting 730// stack 731// 732 733// fixed form for restoring RA and the frame 734// for direct object emitter, encoding needs to be adjusted for the 735// frame size 736// 737let ra=1, s=0,s0=1,s1=1 in 738def RestoreRaF16: 739 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 740 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 741 let isCodeGenOnly = 1; 742 let Defs = [S0, S1, RA, SP]; 743 let Uses = [SP]; 744} 745 746// Use Restore to increment SP since SP is not a Mip 16 register, this 747// is an easy way to do that which does not require a register. 748// 749let ra=0, s=0,s0=0,s1=0 in 750def RestoreIncSpF16: 751 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 752 "restore\t$frame_size", [], IILoad >, MayLoad { 753 let isCodeGenOnly = 1; 754 let Defs = [SP]; 755 let Uses = [SP]; 756} 757 758// 759// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 760// MIPS16e 761// Purpose: Save Registers and Set Up Stack Frame 762// To set up a stack frame on entry to a subroutine, 763// saving return address and static registers, and adjusting stack 764// 765let ra=1, s=1,s0=1,s1=1 in 766def SaveRaF16: 767 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 768 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 769 let isCodeGenOnly = 1; 770 let Uses = [RA, SP, S0, S1]; 771 let Defs = [SP]; 772} 773 774// 775// Use Save to decrement the SP by a constant since SP is not 776// a Mips16 register. 777// 778let ra=0, s=0,s0=0,s1=0 in 779def SaveDecSpF16: 780 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 781 "save\t$frame_size", [], IIStore >, MayStore { 782 let isCodeGenOnly = 1; 783 let Uses = [SP]; 784 let Defs = [SP]; 785} 786// 787// Format: SB ry, offset(rx) MIPS16e 788// Purpose: Store Byte (Extended) 789// To store a byte to memory. 790// 791def SbRxRyOffMemX16: 792 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 793 794// 795// The Sel(T) instructions are pseudos 796// T means that they use T8 implicitly. 797// 798// 799// Format: SelBeqZ rd, rs, rt 800// Purpose: if rt==0, do nothing 801// else rs = rt 802// 803def SelBeqZ: Sel<0b00100, "beqz", IIAlu>; 804 805// 806// Format: SelTBteqZCmp rd, rs, rl, rr 807// Purpose: b = Cmp rl, rr. 808// If b==0 then do nothing. 809// if b!=0 then rd = rs 810// 811def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>; 812 813// 814// Format: SelTBteqZCmpi rd, rs, rl, rr 815// Purpose: b = Cmpi rl, imm. 816// If b==0 then do nothing. 817// if b!=0 then rd = rs 818// 819def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>; 820 821// 822// Format: SelTBteqZSlt rd, rs, rl, rr 823// Purpose: b = Slt rl, rr. 824// If b==0 then do nothing. 825// if b!=0 then rd = rs 826// 827def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>; 828 829// 830// Format: SelTBteqZSlti rd, rs, rl, rr 831// Purpose: b = Slti rl, imm. 832// If b==0 then do nothing. 833// if b!=0 then rd = rs 834// 835def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>; 836 837// 838// Format: SelTBteqZSltu rd, rs, rl, rr 839// Purpose: b = Sltu rl, rr. 840// If b==0 then do nothing. 841// if b!=0 then rd = rs 842// 843def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>; 844 845// 846// Format: SelTBteqZSltiu rd, rs, rl, rr 847// Purpose: b = Sltiu rl, imm. 848// If b==0 then do nothing. 849// if b!=0 then rd = rs 850// 851def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>; 852 853// 854// Format: SelBnez rd, rs, rt 855// Purpose: if rt!=0, do nothing 856// else rs = rt 857// 858def SelBneZ: Sel<0b00101, "bnez", IIAlu>; 859 860// 861// Format: SelTBtneZCmp rd, rs, rl, rr 862// Purpose: b = Cmp rl, rr. 863// If b!=0 then do nothing. 864// if b0=0 then rd = rs 865// 866def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>; 867 868// 869// Format: SelTBtnezCmpi rd, rs, rl, rr 870// Purpose: b = Cmpi rl, imm. 871// If b!=0 then do nothing. 872// if b==0 then rd = rs 873// 874def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>; 875 876// 877// Format: SelTBtneZSlt rd, rs, rl, rr 878// Purpose: b = Slt rl, rr. 879// If b!=0 then do nothing. 880// if b==0 then rd = rs 881// 882def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>; 883 884// 885// Format: SelTBtneZSlti rd, rs, rl, rr 886// Purpose: b = Slti rl, imm. 887// If b!=0 then do nothing. 888// if b==0 then rd = rs 889// 890def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>; 891 892// 893// Format: SelTBtneZSltu rd, rs, rl, rr 894// Purpose: b = Sltu rl, rr. 895// If b!=0 then do nothing. 896// if b==0 then rd = rs 897// 898def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>; 899 900// 901// Format: SelTBtneZSltiu rd, rs, rl, rr 902// Purpose: b = Slti rl, imm. 903// If b!=0 then do nothing. 904// if b==0 then rd = rs 905// 906def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>; 907// 908// 909// Format: SH ry, offset(rx) MIPS16e 910// Purpose: Store Halfword (Extended) 911// To store a halfword to memory. 912// 913def ShRxRyOffMemX16: 914 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 915 916// 917// Format: SLL rx, ry, sa MIPS16e 918// Purpose: Shift Word Left Logical (Extended) 919// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 920// 921def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 922 923// 924// Format: SLLV ry, rx MIPS16e 925// Purpose: Shift Word Left Logical Variable 926// To execute a left-shift of a word by a variable number of bits. 927// 928def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 929 930// 931// Format: SLTI rx, immediate MIPS16e 932// Purpose: Set on Less Than Immediate (Extended) 933// To record the result of a less-than comparison with a constant. 934// 935def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>; 936 937// 938// Format: SLTIU rx, immediate MIPS16e 939// Purpose: Set on Less Than Immediate Unsigned (Extended) 940// To record the result of a less-than comparison with a constant. 941// 942def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>; 943 944// 945// Format: SLT rx, ry MIPS16e 946// Purpose: Set on Less Than 947// To record the result of a less-than comparison. 948// 949def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; 950 951def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>; 952 953// Format: SLTU rx, ry MIPS16e 954// Purpose: Set on Less Than Unsigned 955// To record the result of an unsigned less-than comparison. 956// 957def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> { 958 let isCodeGenOnly=1; 959} 960 961 962def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>; 963// 964// Format: SRAV ry, rx MIPS16e 965// Purpose: Shift Word Right Arithmetic Variable 966// To execute an arithmetic right-shift of a word by a variable 967// number of bits. 968// 969def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 970 971 972// 973// Format: SRA rx, ry, sa MIPS16e 974// Purpose: Shift Word Right Arithmetic (Extended) 975// To execute an arithmetic right-shift of a word by a fixed 976// number of bits—1 to 8 bits. 977// 978def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 979 980 981// 982// Format: SRLV ry, rx MIPS16e 983// Purpose: Shift Word Right Logical Variable 984// To execute a logical right-shift of a word by a variable 985// number of bits. 986// 987def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 988 989 990// 991// Format: SRL rx, ry, sa MIPS16e 992// Purpose: Shift Word Right Logical (Extended) 993// To execute a logical right-shift of a word by a fixed 994// number of bits—1 to 31 bits. 995// 996def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 997 998// 999// Format: SUBU rz, rx, ry MIPS16e 1000// Purpose: Subtract Unsigned Word 1001// To subtract 32-bit integers 1002// 1003def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1004 1005// 1006// Format: SW ry, offset(rx) MIPS16e 1007// Purpose: Store Word (Extended) 1008// To store a word to memory. 1009// 1010def SwRxRyOffMemX16: 1011 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1012 1013// 1014// Format: SW rx, offset(sp) MIPS16e 1015// Purpose: Store Word rx (SP-Relative) 1016// To store an SP-relative word to memory. 1017// 1018def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 1019 1020// 1021// 1022// Format: XOR rx, ry MIPS16e 1023// Purpose: Xor 1024// To do a bitwise logical XOR. 1025// 1026def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1027 1028class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1029 let Predicates = [InMips16Mode]; 1030} 1031 1032// Unary Arith/Logic 1033// 1034class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1035 Mips16Pat<(OpNode CPU16Regs:$r), 1036 (I CPU16Regs:$r)>; 1037 1038def: ArithLogicU_pat<not, NotRxRy16>; 1039def: ArithLogicU_pat<ineg, NegRxRy16>; 1040 1041class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1042 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1043 (I CPU16Regs:$l, CPU16Regs:$r)>; 1044 1045def: ArithLogic16_pat<add, AdduRxRyRz16>; 1046def: ArithLogic16_pat<and, AndRxRxRy16>; 1047def: ArithLogic16_pat<mul, MultRxRyRz16>; 1048def: ArithLogic16_pat<or, OrRxRxRy16>; 1049def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1050def: ArithLogic16_pat<xor, XorRxRxRy16>; 1051 1052// Arithmetic and logical instructions with 2 register operands. 1053 1054class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1055 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1056 (I CPU16Regs:$in, imm_type:$imm)>; 1057 1058def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1059def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1060def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1061def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1062 1063class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1064 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1065 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1066 1067def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1068def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1069def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1070 1071class LoadM16_pat<PatFrag OpNode, Instruction I> : 1072 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1073 1074def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1075def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1076def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1077def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1078def: LoadM16_pat<load, LwRxRyOffMemX16>; 1079 1080class StoreM16_pat<PatFrag OpNode, Instruction I> : 1081 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1082 (I CPU16Regs:$r, addr16:$addr)>; 1083 1084def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1085def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1086def: StoreM16_pat<store, SwRxRyOffMemX16>; 1087 1088// Unconditional branch 1089class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1090 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1091 let Predicates = [InMips16Mode]; 1092 } 1093 1094def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1095 (Jal16 tglobaladdr:$dst)>; 1096 1097// Indirect branch 1098def: Mips16Pat< 1099 (brind CPU16Regs:$rs), 1100 (JrcRx16 CPU16Regs:$rs)>; 1101 1102// Jump and Link (Call) 1103let isCall=1, hasDelaySlot=0 in 1104def JumpLinkReg16: 1105 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1106 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1107 1108// Mips16 pseudos 1109let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1110 hasExtraSrcRegAllocReq = 1 in 1111def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1112 1113 1114// setcc patterns 1115 1116class SetCC_R16<PatFrag cond_op, Instruction I>: 1117 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1118 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1119 1120class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1121 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1122 (I CPU16Regs:$rx, imm_type:$imm16)>; 1123 1124 1125def: Mips16Pat<(i32 addr16:$addr), 1126 (AddiuRxRyOffMemX16 addr16:$addr)>; 1127 1128 1129// Large (>16 bit) immediate loads 1130def : Mips16Pat<(i32 imm:$imm), 1131 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1132 (LiRxImmX16 (LO16 imm:$imm)))>; 1133 1134// Carry MipsPatterns 1135def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1136 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1137def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1138 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1139def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1140 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1141 1142// 1143// Some branch conditional patterns are not generated by llvm at this time. 1144// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1145// comparison they are used and for unsigned a different pattern is used. 1146// I am pushing upstream from the full mips16 port and it seemed that I needed 1147// these earlier and the mips32 port has these but now I cannot create test 1148// cases that use these patterns. While I sort this all out I will leave these 1149// extra patterns commented out and if I can be sure they are really not used, 1150// I will delete the code. I don't want to check the code in uncommented without 1151// a valid test case. In some cases, the compiler is generating patterns with 1152// setcc instead and earlier I had implemented setcc first so may have masked 1153// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1154// figure out how to enable the brcond patterns or else possibly new 1155// combinations of of brcond and setcc. 1156// 1157// 1158// bcond-seteq 1159// 1160def: Mips16Pat 1161 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1162 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1163 >; 1164 1165 1166def: Mips16Pat 1167 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1168 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1169 >; 1170 1171def: Mips16Pat 1172 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1173 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1174 >; 1175 1176// 1177// bcond-setgt (do we need to have this pair of setlt, setgt??) 1178// 1179def: Mips16Pat 1180 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1181 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1182 >; 1183 1184// 1185// bcond-setge 1186// 1187def: Mips16Pat 1188 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1189 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1190 >; 1191 1192// 1193// never called because compiler transforms a >= k to a > (k-1) 1194def: Mips16Pat 1195 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1196 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1197 >; 1198 1199// 1200// bcond-setlt 1201// 1202def: Mips16Pat 1203 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1204 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1205 >; 1206 1207def: Mips16Pat 1208 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1209 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1210 >; 1211 1212// 1213// bcond-setle 1214// 1215def: Mips16Pat 1216 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1217 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1218 >; 1219 1220// 1221// bcond-setne 1222// 1223def: Mips16Pat 1224 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1225 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1226 >; 1227 1228def: Mips16Pat 1229 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1230 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1231 >; 1232 1233def: Mips16Pat 1234 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1235 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1236 >; 1237 1238// 1239// This needs to be there but I forget which code will generate it 1240// 1241def: Mips16Pat 1242 <(brcond CPU16Regs:$rx, bb:$targ16), 1243 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1244 >; 1245 1246// 1247 1248// 1249// bcond-setugt 1250// 1251//def: Mips16Pat 1252// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1253// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1254// >; 1255 1256// 1257// bcond-setuge 1258// 1259//def: Mips16Pat 1260// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1261// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1262// >; 1263 1264 1265// 1266// bcond-setult 1267// 1268//def: Mips16Pat 1269// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1270// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1271// >; 1272 1273def: UncondBranch16_pat<br, BimmX16>; 1274 1275// Small immediates 1276def: Mips16Pat<(i32 immSExt16:$in), 1277 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1278 1279def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1280 1281// 1282// MipsDivRem 1283// 1284def: Mips16Pat 1285 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry), 1286 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1287 1288// 1289// MipsDivRemU 1290// 1291def: Mips16Pat 1292 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry), 1293 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1294 1295// signed a,b 1296// x = (a>=b)?x:y 1297// 1298// if !(a < b) x = y 1299// 1300def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1301 CPU16Regs:$x, CPU16Regs:$y), 1302 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1303 CPU16Regs:$a, CPU16Regs:$b)>; 1304 1305// signed a,b 1306// x = (a>b)?x:y 1307// 1308// if (b < a) x = y 1309// 1310def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1311 CPU16Regs:$x, CPU16Regs:$y), 1312 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1313 CPU16Regs:$b, CPU16Regs:$a)>; 1314 1315// unsigned a,b 1316// x = (a>=b)?x:y 1317// 1318// if !(a < b) x = y; 1319// 1320def : Mips16Pat< 1321 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1322 CPU16Regs:$x, CPU16Regs:$y), 1323 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1324 CPU16Regs:$a, CPU16Regs:$b)>; 1325 1326// unsigned a,b 1327// x = (a>b)?x:y 1328// 1329// if (b < a) x = y 1330// 1331def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1332 CPU16Regs:$x, CPU16Regs:$y), 1333 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1334 CPU16Regs:$b, CPU16Regs:$a)>; 1335 1336// signed 1337// x = (a >= k)?x:y 1338// due to an llvm optimization, i don't think that this will ever 1339// be used. This is transformed into x = (a > k-1)?x:y 1340// 1341// 1342 1343//def : Mips16Pat< 1344// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1345// CPU16Regs:$T, CPU16Regs:$F), 1346// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1347// CPU16Regs:$lhs, immSExt16:$rhs)>; 1348 1349//def : Mips16Pat< 1350// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1351// CPU16Regs:$T, CPU16Regs:$F), 1352// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1353// CPU16Regs:$lhs, immSExt16:$rhs)>; 1354 1355// signed 1356// x = (a < k)?x:y 1357// 1358// if !(a < k) x = y; 1359// 1360def : Mips16Pat< 1361 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1362 CPU16Regs:$x, CPU16Regs:$y), 1363 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1364 CPU16Regs:$a, immSExt16:$b)>; 1365 1366 1367// 1368// 1369// signed 1370// x = (a <= b)? x : y 1371// 1372// if (b < a) x = y 1373// 1374def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1375 CPU16Regs:$x, CPU16Regs:$y), 1376 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1377 CPU16Regs:$b, CPU16Regs:$a)>; 1378 1379// 1380// unnsigned 1381// x = (a <= b)? x : y 1382// 1383// if (b < a) x = y 1384// 1385def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1386 CPU16Regs:$x, CPU16Regs:$y), 1387 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1388 CPU16Regs:$b, CPU16Regs:$a)>; 1389 1390// 1391// signed/unsigned 1392// x = (a == b)? x : y 1393// 1394// if (a != b) x = y 1395// 1396def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1397 CPU16Regs:$x, CPU16Regs:$y), 1398 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1399 CPU16Regs:$b, CPU16Regs:$a)>; 1400 1401// 1402// signed/unsigned 1403// x = (a == 0)? x : y 1404// 1405// if (a != 0) x = y 1406// 1407def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1408 CPU16Regs:$x, CPU16Regs:$y), 1409 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1410 CPU16Regs:$a)>; 1411 1412 1413// 1414// signed/unsigned 1415// x = (a == k)? x : y 1416// 1417// if (a != k) x = y 1418// 1419def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1420 CPU16Regs:$x, CPU16Regs:$y), 1421 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1422 CPU16Regs:$a, immZExt16:$k)>; 1423 1424 1425// 1426// signed/unsigned 1427// x = (a != b)? x : y 1428// 1429// if (a == b) x = y 1430// 1431// 1432def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1433 CPU16Regs:$x, CPU16Regs:$y), 1434 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1435 CPU16Regs:$b, CPU16Regs:$a)>; 1436 1437// 1438// signed/unsigned 1439// x = (a != 0)? x : y 1440// 1441// if (a == 0) x = y 1442// 1443def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1444 CPU16Regs:$x, CPU16Regs:$y), 1445 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1446 CPU16Regs:$a)>; 1447 1448// signed/unsigned 1449// x = (a)? x : y 1450// 1451// if (!a) x = y 1452// 1453def : Mips16Pat<(select CPU16Regs:$a, 1454 CPU16Regs:$x, CPU16Regs:$y), 1455 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1456 CPU16Regs:$a)>; 1457 1458 1459// 1460// signed/unsigned 1461// x = (a != k)? x : y 1462// 1463// if (a == k) x = y 1464// 1465def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1466 CPU16Regs:$x, CPU16Regs:$y), 1467 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1468 CPU16Regs:$a, immZExt16:$k)>; 1469 1470// 1471// When writing C code to test setxx these patterns, 1472// some will be transformed into 1473// other things. So we test using C code but using -O3 and -O0 1474// 1475// seteq 1476// 1477def : Mips16Pat 1478 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1479 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1480 1481def : Mips16Pat 1482 <(seteq CPU16Regs:$lhs, 0), 1483 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1484 1485 1486// 1487// setge 1488// 1489 1490def: Mips16Pat 1491 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1492 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1493 (LiRxImmX16 1))>; 1494 1495// 1496// For constants, llvm transforms this to: 1497// x > (k -1) and then reverses the operands to use setlt. So this pattern 1498// is not used now by the compiler. (Presumably checking that k-1 does not 1499// overflow). The compiler never uses this at a the current time, due to 1500// other optimizations. 1501// 1502//def: Mips16Pat 1503// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1504// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1505// (LiRxImmX16 1))>; 1506 1507// This catches the x >= -32768 case by transforming it to x > -32769 1508// 1509def: Mips16Pat 1510 <(setgt CPU16Regs:$lhs, -32769), 1511 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1512 (LiRxImmX16 1))>; 1513 1514// 1515// setgt 1516// 1517// 1518 1519def: Mips16Pat 1520 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1521 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1522 1523// 1524// setle 1525// 1526def: Mips16Pat 1527 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1528 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1529 1530// 1531// setlt 1532// 1533def: SetCC_R16<setlt, SltCCRxRy16>; 1534 1535def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1536 1537// 1538// setne 1539// 1540def : Mips16Pat 1541 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1542 (SltuCCRxRy16 (LiRxImmX16 0), 1543 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1544 1545 1546// 1547// setuge 1548// 1549def: Mips16Pat 1550 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1551 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1552 (LiRxImmX16 1))>; 1553 1554// this pattern will never be used because the compiler will transform 1555// x >= k to x > (k - 1) and then use SLT 1556// 1557//def: Mips16Pat 1558// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1559// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1560// (LiRxImmX16 1))>; 1561 1562// 1563// setugt 1564// 1565def: Mips16Pat 1566 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1567 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1568 1569// 1570// setule 1571// 1572def: Mips16Pat 1573 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1574 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1575 1576// 1577// setult 1578// 1579def: SetCC_R16<setult, SltuCCRxRy16>; 1580 1581def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1582 1583def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1584 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1585 1586// hi/lo relocs 1587 1588def : Mips16Pat<(MipsHi tglobaladdr:$in), 1589 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1590def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1591 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1592 1593// wrapper_pic 1594class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1595 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1596 (ADDiuOp RC:$gp, node:$in)>; 1597 1598 1599def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1600def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1601 1602def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1603 (LbuRxRyOffMemX16 addr16:$src)>; 1604def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1605 (LhuRxRyOffMemX16 addr16:$src)>; 1606