Mips16InstrInfo.td revision a81be80b0eabfc8b5e590a10471c66dadf6ded6f
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14 15// 16// Address operand 17def mem16 : Operand<i32> { 18 let PrintMethod = "printMemOperand"; 19 let MIOperandInfo = (ops CPU16Regs, simm16); 20 let EncoderMethod = "getMemEncoding"; 21} 22 23// 24// Compare a register and immediate and place result in CC 25// Implicit use of T8 26// 27// EXT-CCRR Instruction format 28// 29class FEXT_CCRXI16_ins<bits<5> _op, string asmstr, 30 InstrItinClass itin>: 31 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 32 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> { 33 let isCodeGenOnly=1; 34} 35 36// 37// EXT-I instruction format 38// 39class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 40 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 41 !strconcat(asmstr, "\t$imm16"),[], itin>; 42 43// 44// EXT-I8 instruction format 45// 46 47class FEXT_I816_ins_base<bits<3> _func, string asmstr, 48 string asmstr2, InstrItinClass itin>: 49 FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2), 50 [], itin>; 51 52class FEXT_I816_ins<bits<3> _func, string asmstr, 53 InstrItinClass itin>: 54 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 55 56// 57// Assembler formats in alphabetical order. 58// Natural and pseudos are mixed together. 59// 60// Compare two registers and place result in CC 61// Implicit use of T8 62// 63// CC-RR Instruction format 64// 65class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 66 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 67 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> { 68 let isCodeGenOnly=1; 69} 70 71// 72// EXT-RI instruction format 73// 74 75class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 76 InstrItinClass itin>: 77 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 78 !strconcat(asmstr, asmstr2), [], itin>; 79 80class FEXT_RI16_ins<bits<5> _op, string asmstr, 81 InstrItinClass itin>: 82 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 83 84class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 85 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 86 87class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 88 InstrItinClass itin>: 89 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 90 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 91 92class FEXT_2RI16_ins<bits<5> _op, string asmstr, 93 InstrItinClass itin>: 94 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 95 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 96 let Constraints = "$rx_ = $rx"; 97} 98 99 100// this has an explicit sp argument that we ignore to work around a problem 101// in the compiler 102class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 103 InstrItinClass itin>: 104 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 105 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 106 107// 108// EXT-RRI instruction format 109// 110 111class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 112 InstrItinClass itin>: 113 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 114 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 115 116class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 117 InstrItinClass itin>: 118 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 119 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 120 121// 122// EXT-SHIFT instruction format 123// 124class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 125 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 126 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 127 128// 129// EXT-T8I8 130// 131class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2, 132 InstrItinClass itin>: 133 FEXT_I816<_func, (outs), 134 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 135 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 136 !strconcat(asmstr, "\t$imm"))),[], itin> { 137 let isCodeGenOnly=1; 138} 139 140// 141// EXT-T8I8I 142// 143class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2, 144 InstrItinClass itin>: 145 FEXT_I816<_func, (outs), 146 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 147 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 148 !strconcat(asmstr, "\t$targ"))), [], itin> { 149 let isCodeGenOnly=1; 150} 151// 152 153 154// 155// I8_MOVR32 instruction format (used only by the MOVR32 instructio 156// 157class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 158 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 159 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 160 161// 162// I8_MOV32R instruction format (used only by MOV32R instruction) 163// 164 165class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 166 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 167 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 168 169// 170// This are pseudo formats for multiply 171// This first one can be changed to non pseudo now. 172// 173// MULT 174// 175class FMULT16_ins<string asmstr, InstrItinClass itin> : 176 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 177 !strconcat(asmstr, "\t$rx, $ry"), []>; 178 179// 180// MULT-LO 181// 182class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 183 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 184 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 185 let isCodeGenOnly=1; 186} 187 188// 189// RR-type instruction format 190// 191 192class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 193 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 194 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 195} 196 197class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 198 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 199 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ; 200 201// 202// maybe refactor but need a $zero as a dummy first parameter 203// 204class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 205 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 206 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 207 208class FRR16_M_ins<bits<5> f, string asmstr, 209 InstrItinClass itin> : 210 FRR16<f, (outs CPU16Regs:$rx), (ins), 211 !strconcat(asmstr, "\t$rx"), [], itin>; 212 213class FRxRxRy16_ins<bits<5> f, string asmstr, 214 InstrItinClass itin> : 215 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 216 !strconcat(asmstr, "\t$rz, $ry"), 217 [], itin> { 218 let Constraints = "$rx = $rz"; 219} 220 221let rx=0 in 222class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 223 string asmstr, InstrItinClass itin>: 224 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 225 [], itin> ; 226 227// 228// RRR-type instruction format 229// 230 231class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 232 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 233 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 234 235// 236// These Sel patterns support the generation of conditional move 237// pseudo instructions. 238// 239// The nomenclature uses the components making up the pseudo and may 240// be a bit counter intuitive when compared with the end result we seek. 241// For example using a bqez in the example directly below results in the 242// conditional move being done if the tested register is not zero. 243// I considered in easier to check by keeping the pseudo consistent with 244// it's components but it could have been done differently. 245// 246// The simplest case is when can test and operand directly and do the 247// conditional move based on a simple mips16 conditional 248// branch instruction. 249// for example: 250// if $op == beqz or bnez: 251// 252// $op1 $rt, .+4 253// move $rd, $rs 254// 255// if $op == beqz, then if $rt != 0, then the conditional assignment 256// $rd = $rs is done. 257 258// if $op == bnez, then if $rt == 0, then the conditional assignment 259// $rd = $rs is done. 260// 261// So this pseudo class only has one operand, i.e. op 262// 263class Sel<bits<5> f1, string op, InstrItinClass itin>: 264 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 265 CPU16Regs:$rt), 266 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin, 267 Pseudo16> { 268 let isCodeGenOnly=1; 269 let Constraints = "$rd = $rd_"; 270} 271 272// 273// The next two instruction classes allow for an operand which tests 274// two operands and returns a value in register T8 and 275//then does a conditional branch based on the value of T8 276// 277 278// op2 can be cmpi or slti/sltiu 279// op1 can bteqz or btnez 280// the operands for op2 are a register and a signed constant 281// 282// $op2 $t, $imm ;test register t and branch conditionally 283// $op1 .+4 ;op1 is a conditional branch 284// move $rd, $rs 285// 286// 287class SeliT<bits<5> f1, string op1, bits<5> f2, string op2, 288 InstrItinClass itin>: 289 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 290 CPU16Regs:$rl, simm16:$imm), 291 !strconcat(op2, 292 !strconcat("\t$rl, $imm\n\t", 293 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 294 Pseudo16> { 295 let isCodeGenOnly=1; 296 let Constraints = "$rd = $rd_"; 297} 298 299// 300// op2 can be cmp or slt/sltu 301// op1 can be bteqz or btnez 302// the operands for op2 are two registers 303// op1 is a conditional branch 304// 305// 306// $op2 $rl, $rr ;test registers rl,rr 307// $op1 .+4 ;op2 is a conditional branch 308// move $rd, $rs 309// 310// 311class SelT<bits<5> f1, string op1, bits<5> f2, string op2, 312 InstrItinClass itin>: 313 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 314 CPU16Regs:$rl, CPU16Regs:$rr), 315 !strconcat(op2, 316 !strconcat("\t$rl, $rr\n\t", 317 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 318 Pseudo16> { 319 let isCodeGenOnly=1; 320 let Constraints = "$rd = $rd_"; 321} 322 323 324// 325// Some general instruction class info 326// 327// 328 329class ArithLogic16Defs<bit isCom=0> { 330 bits<5> shamt = 0; 331 bit isCommutable = isCom; 332 bit isReMaterializable = 1; 333 bit neverHasSideEffects = 1; 334} 335 336class branch16 { 337 bit isBranch = 1; 338 bit isTerminator = 1; 339 bit isBarrier = 1; 340} 341 342class cbranch16 { 343 bit isBranch = 1; 344 bit isTerminator = 1; 345} 346 347class MayLoad { 348 bit mayLoad = 1; 349} 350 351class MayStore { 352 bit mayStore = 1; 353} 354// 355 356// Format: ADDIU rx, immediate MIPS16e 357// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 358// To add a constant to a 32-bit integer. 359// 360def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 361 362def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 363 ArithLogic16Defs<0>; 364 365// 366 367// Format: ADDIU rx, pc, immediate MIPS16e 368// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 369// To add a constant to the program counter. 370// 371def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 372// 373// Format: ADDU rz, rx, ry MIPS16e 374// Purpose: Add Unsigned Word (3-Operand) 375// To add 32-bit integers. 376// 377 378def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 379 380// 381// Format: AND rx, ry MIPS16e 382// Purpose: AND 383// To do a bitwise logical AND. 384 385def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 386 387 388// 389// Format: BEQZ rx, offset MIPS16e 390// Purpose: Branch on Equal to Zero (Extended) 391// To test a GPR then do a PC-relative conditional branch. 392// 393def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 394 395// Format: B offset MIPS16e 396// Purpose: Unconditional Branch 397// To do an unconditional PC-relative branch. 398// 399def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 400 401// 402// Format: BNEZ rx, offset MIPS16e 403// Purpose: Branch on Not Equal to Zero (Extended) 404// To test a GPR then do a PC-relative conditional branch. 405// 406def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 407 408// 409// Format: BTEQZ offset MIPS16e 410// Purpose: Branch on T Equal to Zero (Extended) 411// To test special register T then do a PC-relative conditional branch. 412// 413def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; 414 415def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16; 416 417def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>, 418 cbranch16; 419 420def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16; 421 422def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16; 423 424def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16; 425 426def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>, 427 cbranch16; 428 429// 430// Format: BTNEZ offset MIPS16e 431// Purpose: Branch on T Not Equal to Zero (Extended) 432// To test special register T then do a PC-relative conditional branch. 433// 434def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; 435 436def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16; 437 438def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16; 439 440def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16; 441 442def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16; 443 444def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16; 445 446def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>, 447 cbranch16; 448 449// 450// Format: DIV rx, ry MIPS16e 451// Purpose: Divide Word 452// To divide 32-bit signed integers. 453// 454def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 455 let Defs = [HI, LO]; 456} 457 458// 459// Format: DIVU rx, ry MIPS16e 460// Purpose: Divide Unsigned Word 461// To divide 32-bit unsigned integers. 462// 463def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 464 let Defs = [HI, LO]; 465} 466 467 468// 469// Format: JR ra MIPS16e 470// Purpose: Jump Register Through Register ra 471// To execute a branch to the instruction address in the return 472// address register. 473// 474 475def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>; 476 477// 478// Format: LB ry, offset(rx) MIPS16e 479// Purpose: Load Byte (Extended) 480// To load a byte from memory as a signed value. 481// 482def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; 483 484// 485// Format: LBU ry, offset(rx) MIPS16e 486// Purpose: Load Byte Unsigned (Extended) 487// To load a byte from memory as a unsigned value. 488// 489def LbuRxRyOffMemX16: 490 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad; 491 492// 493// Format: LH ry, offset(rx) MIPS16e 494// Purpose: Load Halfword signed (Extended) 495// To load a halfword from memory as a signed value. 496// 497def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; 498 499// 500// Format: LHU ry, offset(rx) MIPS16e 501// Purpose: Load Halfword unsigned (Extended) 502// To load a halfword from memory as an unsigned value. 503// 504def LhuRxRyOffMemX16: 505 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad; 506 507// 508// Format: LI rx, immediate MIPS16e 509// Purpose: Load Immediate (Extended) 510// To load a constant into a GPR. 511// 512def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 513 514// 515// Format: LW ry, offset(rx) MIPS16e 516// Purpose: Load Word (Extended) 517// To load a word from memory as a signed value. 518// 519def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad; 520 521// Format: LW rx, offset(sp) MIPS16e 522// Purpose: Load Word (SP-Relative, Extended) 523// To load an SP-relative word from memory as a signed value. 524// 525def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad; 526 527// 528// Format: MOVE r32, rz MIPS16e 529// Purpose: Move 530// To move the contents of a GPR to a GPR. 531// 532def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 533 534// 535// Format: MOVE ry, r32 MIPS16e 536//Purpose: Move 537// To move the contents of a GPR to a GPR. 538// 539def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 540 541// 542// Format: MFHI rx MIPS16e 543// Purpose: Move From HI Register 544// To copy the special purpose HI register to a GPR. 545// 546def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 547 let Uses = [HI]; 548 let neverHasSideEffects = 1; 549} 550 551// 552// Format: MFLO rx MIPS16e 553// Purpose: Move From LO Register 554// To copy the special purpose LO register to a GPR. 555// 556def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 557 let Uses = [LO]; 558 let neverHasSideEffects = 1; 559} 560 561// 562// Pseudo Instruction for mult 563// 564def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 565 let isCommutable = 1; 566 let neverHasSideEffects = 1; 567 let Defs = [HI, LO]; 568} 569 570def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 571 let isCommutable = 1; 572 let neverHasSideEffects = 1; 573 let Defs = [HI, LO]; 574} 575 576// 577// Format: MULT rx, ry MIPS16e 578// Purpose: Multiply Word 579// To multiply 32-bit signed integers. 580// 581def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 582 let isCommutable = 1; 583 let neverHasSideEffects = 1; 584 let Defs = [HI, LO]; 585} 586 587// 588// Format: MULTU rx, ry MIPS16e 589// Purpose: Multiply Unsigned Word 590// To multiply 32-bit unsigned integers. 591// 592def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 593 let isCommutable = 1; 594 let neverHasSideEffects = 1; 595 let Defs = [HI, LO]; 596} 597 598// 599// Format: NEG rx, ry MIPS16e 600// Purpose: Negate 601// To negate an integer value. 602// 603def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>; 604 605// 606// Format: NOT rx, ry MIPS16e 607// Purpose: Not 608// To complement an integer value 609// 610def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>; 611 612// 613// Format: OR rx, ry MIPS16e 614// Purpose: Or 615// To do a bitwise logical OR. 616// 617def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 618 619// 620// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 621// (All args are optional) MIPS16e 622// Purpose: Restore Registers and Deallocate Stack Frame 623// To deallocate a stack frame before exit from a subroutine, 624// restoring return address and static registers, and adjusting 625// stack 626// 627 628// fixed form for restoring RA and the frame 629// for direct object emitter, encoding needs to be adjusted for the 630// frame size 631// 632let ra=1, s=0,s0=1,s1=1 in 633def RestoreRaF16: 634 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 635 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 636 let isCodeGenOnly = 1; 637} 638 639// 640// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 641// MIPS16e 642// Purpose: Save Registers and Set Up Stack Frame 643// To set up a stack frame on entry to a subroutine, 644// saving return address and static registers, and adjusting stack 645// 646let ra=1, s=1,s0=1,s1=1 in 647def SaveRaF16: 648 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 649 "save \t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 650 let isCodeGenOnly = 1; 651} 652// 653// Format: SB ry, offset(rx) MIPS16e 654// Purpose: Store Byte (Extended) 655// To store a byte to memory. 656// 657def SbRxRyOffMemX16: 658 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 659 660// 661// The Sel(T) instructions are pseudos 662// T means that they use T8 implicitly. 663// 664// 665// Format: SelBeqZ rd, rs, rt 666// Purpose: if rt==0, do nothing 667// else rs = rt 668// 669def SelBeqZ: Sel<0b00100, "beqz", IIAlu>; 670 671// 672// Format: SelTBteqZCmp rd, rs, rl, rr 673// Purpose: b = Cmp rl, rr. 674// If b==0 then do nothing. 675// if b!=0 then rd = rs 676// 677def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>; 678 679// 680// Format: SelTBteqZCmpi rd, rs, rl, rr 681// Purpose: b = Cmpi rl, imm. 682// If b==0 then do nothing. 683// if b!=0 then rd = rs 684// 685def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>; 686 687// 688// Format: SelTBteqZSlt rd, rs, rl, rr 689// Purpose: b = Slt rl, rr. 690// If b==0 then do nothing. 691// if b!=0 then rd = rs 692// 693def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>; 694 695// 696// Format: SelTBteqZSlti rd, rs, rl, rr 697// Purpose: b = Slti rl, imm. 698// If b==0 then do nothing. 699// if b!=0 then rd = rs 700// 701def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>; 702 703// 704// Format: SelTBteqZSltu rd, rs, rl, rr 705// Purpose: b = Sltu rl, rr. 706// If b==0 then do nothing. 707// if b!=0 then rd = rs 708// 709def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>; 710 711// 712// Format: SelTBteqZSltiu rd, rs, rl, rr 713// Purpose: b = Sltiu rl, imm. 714// If b==0 then do nothing. 715// if b!=0 then rd = rs 716// 717def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>; 718 719// 720// Format: SelBnez rd, rs, rt 721// Purpose: if rt!=0, do nothing 722// else rs = rt 723// 724def SelBneZ: Sel<0b00101, "bnez", IIAlu>; 725 726// 727// Format: SelTBtneZCmp rd, rs, rl, rr 728// Purpose: b = Cmp rl, rr. 729// If b!=0 then do nothing. 730// if b0=0 then rd = rs 731// 732def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>; 733 734// 735// Format: SelTBtnezCmpi rd, rs, rl, rr 736// Purpose: b = Cmpi rl, imm. 737// If b!=0 then do nothing. 738// if b==0 then rd = rs 739// 740def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>; 741 742// 743// Format: SelTBtneZSlt rd, rs, rl, rr 744// Purpose: b = Slt rl, rr. 745// If b!=0 then do nothing. 746// if b==0 then rd = rs 747// 748def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>; 749 750// 751// Format: SelTBtneZSlti rd, rs, rl, rr 752// Purpose: b = Slti rl, imm. 753// If b!=0 then do nothing. 754// if b==0 then rd = rs 755// 756def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>; 757 758// 759// Format: SelTBtneZSltu rd, rs, rl, rr 760// Purpose: b = Sltu rl, rr. 761// If b!=0 then do nothing. 762// if b==0 then rd = rs 763// 764def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>; 765 766// 767// Format: SelTBtneZSltiu rd, rs, rl, rr 768// Purpose: b = Slti rl, imm. 769// If b!=0 then do nothing. 770// if b==0 then rd = rs 771// 772def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>; 773// 774// 775// Format: SH ry, offset(rx) MIPS16e 776// Purpose: Store Halfword (Extended) 777// To store a halfword to memory. 778// 779def ShRxRyOffMemX16: 780 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 781 782// 783// Format: SLL rx, ry, sa MIPS16e 784// Purpose: Shift Word Left Logical (Extended) 785// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 786// 787def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 788 789// 790// Format: SLLV ry, rx MIPS16e 791// Purpose: Shift Word Left Logical Variable 792// To execute a left-shift of a word by a variable number of bits. 793// 794def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 795 796// 797// Format: SLTI rx, immediate MIPS16e 798// Purpose: Set on Less Than Immediate (Extended) 799// To record the result of a less-than comparison with a constant. 800// 801def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>; 802 803// 804// Format: SLTIU rx, immediate MIPS16e 805// Purpose: Set on Less Than Immediate Unsigned (Extended) 806// To record the result of a less-than comparison with a constant. 807// 808def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>; 809 810// 811// Format: SLT rx, ry MIPS16e 812// Purpose: Set on Less Than 813// To record the result of a less-than comparison. 814// 815def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; 816 817def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>; 818 819// Format: SLTU rx, ry MIPS16e 820// Purpose: Set on Less Than Unsigned 821// To record the result of an unsigned less-than comparison. 822// 823def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> { 824 let isCodeGenOnly=1; 825} 826 827 828def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>; 829// 830// Format: SRAV ry, rx MIPS16e 831// Purpose: Shift Word Right Arithmetic Variable 832// To execute an arithmetic right-shift of a word by a variable 833// number of bits. 834// 835def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 836 837 838// 839// Format: SRA rx, ry, sa MIPS16e 840// Purpose: Shift Word Right Arithmetic (Extended) 841// To execute an arithmetic right-shift of a word by a fixed 842// number of bits—1 to 8 bits. 843// 844def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 845 846 847// 848// Format: SRLV ry, rx MIPS16e 849// Purpose: Shift Word Right Logical Variable 850// To execute a logical right-shift of a word by a variable 851// number of bits. 852// 853def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 854 855 856// 857// Format: SRL rx, ry, sa MIPS16e 858// Purpose: Shift Word Right Logical (Extended) 859// To execute a logical right-shift of a word by a fixed 860// number of bits—1 to 31 bits. 861// 862def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 863 864// 865// Format: SUBU rz, rx, ry MIPS16e 866// Purpose: Subtract Unsigned Word 867// To subtract 32-bit integers 868// 869def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 870 871// 872// Format: SW ry, offset(rx) MIPS16e 873// Purpose: Store Word (Extended) 874// To store a word to memory. 875// 876def SwRxRyOffMemX16: 877 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 878 879// 880// Format: SW rx, offset(sp) MIPS16e 881// Purpose: Store Word rx (SP-Relative) 882// To store an SP-relative word to memory. 883// 884def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 885 886// 887// 888// Format: XOR rx, ry MIPS16e 889// Purpose: Xor 890// To do a bitwise logical XOR. 891// 892def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 893 894class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 895 let Predicates = [InMips16Mode]; 896} 897 898// Unary Arith/Logic 899// 900class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 901 Mips16Pat<(OpNode CPU16Regs:$r), 902 (I CPU16Regs:$r)>; 903 904def: ArithLogicU_pat<not, NotRxRy16>; 905def: ArithLogicU_pat<ineg, NegRxRy16>; 906 907class ArithLogic16_pat<SDNode OpNode, Instruction I> : 908 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 909 (I CPU16Regs:$l, CPU16Regs:$r)>; 910 911def: ArithLogic16_pat<add, AdduRxRyRz16>; 912def: ArithLogic16_pat<and, AndRxRxRy16>; 913def: ArithLogic16_pat<mul, MultRxRyRz16>; 914def: ArithLogic16_pat<or, OrRxRxRy16>; 915def: ArithLogic16_pat<sub, SubuRxRyRz16>; 916def: ArithLogic16_pat<xor, XorRxRxRy16>; 917 918// Arithmetic and logical instructions with 2 register operands. 919 920class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 921 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 922 (I CPU16Regs:$in, imm_type:$imm)>; 923 924def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 925def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 926def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 927def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 928 929class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 930 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 931 (I CPU16Regs:$r, CPU16Regs:$ra)>; 932 933def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 934def: shift_rotate_reg16_pat<sra, SravRxRy16>; 935def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 936 937class LoadM16_pat<PatFrag OpNode, Instruction I> : 938 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>; 939 940def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 941def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 942def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 943def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 944def: LoadM16_pat<load, LwRxRyOffMemX16>; 945 946class StoreM16_pat<PatFrag OpNode, Instruction I> : 947 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>; 948 949def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 950def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 951def: StoreM16_pat<store, SwRxRyOffMemX16>; 952 953// Unconditional branch 954class UncondBranch16_pat<SDNode OpNode, Instruction I>: 955 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 956 let Predicates = [RelocPIC, InMips16Mode]; 957 } 958 959// Jump and Link (Call) 960let isCall=1, hasDelaySlot=1 in 961def JumpLinkReg16: 962 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 963 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 964 965// Mips16 pseudos 966let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 967 hasExtraSrcRegAllocReq = 1 in 968def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 969 970 971// setcc patterns 972 973class SetCC_R16<PatFrag cond_op, Instruction I>: 974 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 975 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 976 977class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 978 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 979 (I CPU16Regs:$rx, imm_type:$imm16)>; 980 981// Large (>16 bit) immediate loads 982def : Mips16Pat<(i32 imm:$imm), 983 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 984 (LiRxImmX16 (LO16 imm:$imm)))>; 985 986// Carry MipsPatterns 987def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 988 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 989def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 990 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 991def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 992 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 993 994// 995// Some branch conditional patterns are not generated by llvm at this time. 996// Some are for seemingly arbitrary reasons not used: i.e. with signed number 997// comparison they are used and for unsigned a different pattern is used. 998// I am pushing upstream from the full mips16 port and it seemed that I needed 999// these earlier and the mips32 port has these but now I cannot create test 1000// cases that use these patterns. While I sort this all out I will leave these 1001// extra patterns commented out and if I can be sure they are really not used, 1002// I will delete the code. I don't want to check the code in uncommented without 1003// a valid test case. In some cases, the compiler is generating patterns with 1004// setcc instead and earlier I had implemented setcc first so may have masked 1005// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1006// figure out how to enable the brcond patterns or else possibly new 1007// combinations of of brcond and setcc. 1008// 1009// 1010// bcond-seteq 1011// 1012def: Mips16Pat 1013 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1014 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1015 >; 1016 1017 1018def: Mips16Pat 1019 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1020 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1021 >; 1022 1023def: Mips16Pat 1024 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1025 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1026 >; 1027 1028// 1029// bcond-setgt (do we need to have this pair of setlt, setgt??) 1030// 1031def: Mips16Pat 1032 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1033 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1034 >; 1035 1036// 1037// bcond-setge 1038// 1039def: Mips16Pat 1040 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1041 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1042 >; 1043 1044// 1045// never called because compiler transforms a >= k to a > (k-1) 1046def: Mips16Pat 1047 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1048 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1049 >; 1050 1051// 1052// bcond-setlt 1053// 1054def: Mips16Pat 1055 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1056 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1057 >; 1058 1059def: Mips16Pat 1060 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1061 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1062 >; 1063 1064// 1065// bcond-setle 1066// 1067def: Mips16Pat 1068 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1069 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1070 >; 1071 1072// 1073// bcond-setne 1074// 1075def: Mips16Pat 1076 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1077 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1078 >; 1079 1080def: Mips16Pat 1081 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1082 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1083 >; 1084 1085def: Mips16Pat 1086 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1087 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1088 >; 1089 1090// 1091// This needs to be there but I forget which code will generate it 1092// 1093def: Mips16Pat 1094 <(brcond CPU16Regs:$rx, bb:$targ16), 1095 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1096 >; 1097 1098// 1099 1100// 1101// bcond-setugt 1102// 1103//def: Mips16Pat 1104// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1105// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1106// >; 1107 1108// 1109// bcond-setuge 1110// 1111//def: Mips16Pat 1112// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1113// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1114// >; 1115 1116 1117// 1118// bcond-setult 1119// 1120//def: Mips16Pat 1121// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1122// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1123// >; 1124 1125def: UncondBranch16_pat<br, BimmX16>; 1126 1127// Small immediates 1128def: Mips16Pat<(i32 immSExt16:$in), 1129 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1130 1131def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1132 1133// 1134// MipsDivRem 1135// 1136def: Mips16Pat 1137 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry), 1138 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1139 1140// 1141// MipsDivRemU 1142// 1143def: Mips16Pat 1144 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry), 1145 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1146 1147// signed a,b 1148// x = (a>=b)?x:y 1149// 1150// if !(a < b) x = y 1151// 1152def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1153 CPU16Regs:$x, CPU16Regs:$y), 1154 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1155 CPU16Regs:$a, CPU16Regs:$b)>; 1156 1157// signed a,b 1158// x = (a>b)?x:y 1159// 1160// if (b < a) x = y 1161// 1162def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1163 CPU16Regs:$x, CPU16Regs:$y), 1164 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1165 CPU16Regs:$b, CPU16Regs:$a)>; 1166 1167// unsigned a,b 1168// x = (a>=b)?x:y 1169// 1170// if !(a < b) x = y; 1171// 1172def : Mips16Pat< 1173 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1174 CPU16Regs:$x, CPU16Regs:$y), 1175 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1176 CPU16Regs:$a, CPU16Regs:$b)>; 1177 1178// unsigned a,b 1179// x = (a>b)?x:y 1180// 1181// if (b < a) x = y 1182// 1183def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1184 CPU16Regs:$x, CPU16Regs:$y), 1185 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1186 CPU16Regs:$b, CPU16Regs:$a)>; 1187 1188// signed 1189// x = (a >= k)?x:y 1190// due to an llvm optimization, i don't think that this will ever 1191// be used. This is transformed into x = (a > k-1)?x:y 1192// 1193// 1194 1195//def : Mips16Pat< 1196// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1197// CPU16Regs:$T, CPU16Regs:$F), 1198// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1199// CPU16Regs:$lhs, immSExt16:$rhs)>; 1200 1201//def : Mips16Pat< 1202// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1203// CPU16Regs:$T, CPU16Regs:$F), 1204// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1205// CPU16Regs:$lhs, immSExt16:$rhs)>; 1206 1207// signed 1208// x = (a < k)?x:y 1209// 1210// if !(a < k) x = y; 1211// 1212def : Mips16Pat< 1213 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1214 CPU16Regs:$x, CPU16Regs:$y), 1215 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1216 CPU16Regs:$a, immSExt16:$b)>; 1217 1218 1219// 1220// 1221// signed 1222// x = (a <= b)? x : y 1223// 1224// if (b < a) x = y 1225// 1226def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1227 CPU16Regs:$x, CPU16Regs:$y), 1228 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1229 CPU16Regs:$b, CPU16Regs:$a)>; 1230 1231// 1232// unnsigned 1233// x = (a <= b)? x : y 1234// 1235// if (b < a) x = y 1236// 1237def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1238 CPU16Regs:$x, CPU16Regs:$y), 1239 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1240 CPU16Regs:$b, CPU16Regs:$a)>; 1241 1242// 1243// signed/unsigned 1244// x = (a == b)? x : y 1245// 1246// if (a != b) x = y 1247// 1248def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1249 CPU16Regs:$x, CPU16Regs:$y), 1250 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1251 CPU16Regs:$b, CPU16Regs:$a)>; 1252 1253// 1254// signed/unsigned 1255// x = (a == 0)? x : y 1256// 1257// if (a != 0) x = y 1258// 1259def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1260 CPU16Regs:$x, CPU16Regs:$y), 1261 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1262 CPU16Regs:$a)>; 1263 1264 1265// 1266// signed/unsigned 1267// x = (a == k)? x : y 1268// 1269// if (a != k) x = y 1270// 1271def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1272 CPU16Regs:$x, CPU16Regs:$y), 1273 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1274 CPU16Regs:$a, immZExt16:$k)>; 1275 1276 1277// 1278// signed/unsigned 1279// x = (a != b)? x : y 1280// 1281// if (a == b) x = y 1282// 1283// 1284def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1285 CPU16Regs:$x, CPU16Regs:$y), 1286 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1287 CPU16Regs:$b, CPU16Regs:$a)>; 1288 1289// 1290// signed/unsigned 1291// x = (a != 0)? x : y 1292// 1293// if (a == 0) x = y 1294// 1295def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1296 CPU16Regs:$x, CPU16Regs:$y), 1297 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1298 CPU16Regs:$a)>; 1299 1300// signed/unsigned 1301// x = (a)? x : y 1302// 1303// if (!a) x = y 1304// 1305def : Mips16Pat<(select CPU16Regs:$a, 1306 CPU16Regs:$x, CPU16Regs:$y), 1307 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1308 CPU16Regs:$a)>; 1309 1310 1311// 1312// signed/unsigned 1313// x = (a != k)? x : y 1314// 1315// if (a == k) x = y 1316// 1317def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1318 CPU16Regs:$x, CPU16Regs:$y), 1319 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1320 CPU16Regs:$a, immZExt16:$k)>; 1321 1322// 1323// When writing C code to test setxx these patterns, 1324// some will be transformed into 1325// other things. So we test using C code but using -O3 and -O0 1326// 1327// seteq 1328// 1329def : Mips16Pat 1330 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1331 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1332 1333def : Mips16Pat 1334 <(seteq CPU16Regs:$lhs, 0), 1335 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1336 1337 1338// 1339// setge 1340// 1341 1342def: Mips16Pat 1343 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1344 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1345 (LiRxImmX16 1))>; 1346 1347// 1348// For constants, llvm transforms this to: 1349// x > (k -1) and then reverses the operands to use setlt. So this pattern 1350// is not used now by the compiler. (Presumably checking that k-1 does not 1351// overflow). The compiler never uses this at a the current time, due to 1352// other optimizations. 1353// 1354//def: Mips16Pat 1355// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1356// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1357// (LiRxImmX16 1))>; 1358 1359// This catches the x >= -32768 case by transforming it to x > -32769 1360// 1361def: Mips16Pat 1362 <(setgt CPU16Regs:$lhs, -32769), 1363 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1364 (LiRxImmX16 1))>; 1365 1366// 1367// setgt 1368// 1369// 1370 1371def: Mips16Pat 1372 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1373 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1374 1375// 1376// setle 1377// 1378def: Mips16Pat 1379 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1380 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1381 1382// 1383// setlt 1384// 1385def: SetCC_R16<setlt, SltCCRxRy16>; 1386 1387def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1388 1389// 1390// setne 1391// 1392def : Mips16Pat 1393 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1394 (SltuCCRxRy16 (LiRxImmX16 0), 1395 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1396 1397 1398// 1399// setuge 1400// 1401def: Mips16Pat 1402 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1403 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1404 (LiRxImmX16 1))>; 1405 1406// this pattern will never be used because the compiler will transform 1407// x >= k to x > (k - 1) and then use SLT 1408// 1409//def: Mips16Pat 1410// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1411// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1412// (LiRxImmX16 1))>; 1413 1414// 1415// setugt 1416// 1417def: Mips16Pat 1418 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1419 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1420 1421// 1422// setule 1423// 1424def: Mips16Pat 1425 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1426 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1427 1428// 1429// setult 1430// 1431def: SetCC_R16<setult, SltuCCRxRy16>; 1432 1433def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1434 1435def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1436 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1437