Mips16InstrInfo.td revision c09856b5357af621fcb84a7b2b6bfbf630c244ef
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16Regs, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// Compare a register and immediate and place result in CC 36// Implicit use of T8 37// 38// EXT-CCRR Instruction format 39// 40class FEXT_CCRXI16_ins<bits<5> _op, string asmstr, 41 InstrItinClass itin>: 42 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 43 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> { 44 let isCodeGenOnly=1; 45} 46 47// 48// EXT-I instruction format 49// 50class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 51 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 52 !strconcat(asmstr, "\t$imm16"),[], itin>; 53 54// 55// EXT-I8 instruction format 56// 57 58class FEXT_I816_ins_base<bits<3> _func, string asmstr, 59 string asmstr2, InstrItinClass itin>: 60 FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2), 61 [], itin>; 62 63class FEXT_I816_ins<bits<3> _func, string asmstr, 64 InstrItinClass itin>: 65 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 66 67// 68// Assembler formats in alphabetical order. 69// Natural and pseudos are mixed together. 70// 71// Compare two registers and place result in CC 72// Implicit use of T8 73// 74// CC-RR Instruction format 75// 76class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 77 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 78 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> { 79 let isCodeGenOnly=1; 80} 81 82// 83// EXT-RI instruction format 84// 85 86class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 87 InstrItinClass itin>: 88 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 89 !strconcat(asmstr, asmstr2), [], itin>; 90 91class FEXT_RI16_ins<bits<5> _op, string asmstr, 92 InstrItinClass itin>: 93 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 94 95class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 96 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 97 98class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 99 InstrItinClass itin>: 100 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 101 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 102 103class FEXT_2RI16_ins<bits<5> _op, string asmstr, 104 InstrItinClass itin>: 105 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 106 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 107 let Constraints = "$rx_ = $rx"; 108} 109 110 111// this has an explicit sp argument that we ignore to work around a problem 112// in the compiler 113class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 114 InstrItinClass itin>: 115 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 116 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 117 118// 119// EXT-RRI instruction format 120// 121 122class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 123 InstrItinClass itin>: 124 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 125 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 126 127class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 128 InstrItinClass itin>: 129 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 130 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 131 132// 133// 134// EXT-RRI-A instruction format 135// 136 137class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 138 InstrItinClass itin>: 139 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 140 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 141 142// 143// EXT-SHIFT instruction format 144// 145class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 146 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 147 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 148 149// 150// EXT-T8I8 151// 152class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2, 153 InstrItinClass itin>: 154 FEXT_I816<_func, (outs), 155 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 156 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 157 !strconcat(asmstr, "\t$imm"))),[], itin> { 158 let isCodeGenOnly=1; 159} 160 161// 162// EXT-T8I8I 163// 164class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2, 165 InstrItinClass itin>: 166 FEXT_I816<_func, (outs), 167 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 168 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 169 !strconcat(asmstr, "\t$targ"))), [], itin> { 170 let isCodeGenOnly=1; 171} 172// 173 174 175// 176// I8_MOVR32 instruction format (used only by the MOVR32 instructio 177// 178class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 179 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 180 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 181 182// 183// I8_MOV32R instruction format (used only by MOV32R instruction) 184// 185 186class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 187 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 188 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 189 190// 191// This are pseudo formats for multiply 192// This first one can be changed to non pseudo now. 193// 194// MULT 195// 196class FMULT16_ins<string asmstr, InstrItinClass itin> : 197 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 198 !strconcat(asmstr, "\t$rx, $ry"), []>; 199 200// 201// MULT-LO 202// 203class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 204 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 205 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 206 let isCodeGenOnly=1; 207} 208 209// 210// RR-type instruction format 211// 212 213class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 214 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 215 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 216} 217 218class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 219 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 220 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ; 221 222// 223// maybe refactor but need a $zero as a dummy first parameter 224// 225class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 226 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 227 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 228 229class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 230 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 231 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 232 233 234class FRR16_M_ins<bits<5> f, string asmstr, 235 InstrItinClass itin> : 236 FRR16<f, (outs CPU16Regs:$rx), (ins), 237 !strconcat(asmstr, "\t$rx"), [], itin>; 238 239class FRxRxRy16_ins<bits<5> f, string asmstr, 240 InstrItinClass itin> : 241 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 242 !strconcat(asmstr, "\t$rz, $ry"), 243 [], itin> { 244 let Constraints = "$rx = $rz"; 245} 246 247let rx=0 in 248class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 249 string asmstr, InstrItinClass itin>: 250 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 251 [], itin> ; 252 253 254class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 255 string asmstr, InstrItinClass itin>: 256 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 257 !strconcat(asmstr, "\t $rx"), [], itin> ; 258 259// 260// RRR-type instruction format 261// 262 263class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 264 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 265 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 266 267// 268// These Sel patterns support the generation of conditional move 269// pseudo instructions. 270// 271// The nomenclature uses the components making up the pseudo and may 272// be a bit counter intuitive when compared with the end result we seek. 273// For example using a bqez in the example directly below results in the 274// conditional move being done if the tested register is not zero. 275// I considered in easier to check by keeping the pseudo consistent with 276// it's components but it could have been done differently. 277// 278// The simplest case is when can test and operand directly and do the 279// conditional move based on a simple mips16 conditional 280// branch instruction. 281// for example: 282// if $op == beqz or bnez: 283// 284// $op1 $rt, .+4 285// move $rd, $rs 286// 287// if $op == beqz, then if $rt != 0, then the conditional assignment 288// $rd = $rs is done. 289 290// if $op == bnez, then if $rt == 0, then the conditional assignment 291// $rd = $rs is done. 292// 293// So this pseudo class only has one operand, i.e. op 294// 295class Sel<bits<5> f1, string op, InstrItinClass itin>: 296 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 297 CPU16Regs:$rt), 298 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin, 299 Pseudo16> { 300 let isCodeGenOnly=1; 301 let Constraints = "$rd = $rd_"; 302} 303 304// 305// The next two instruction classes allow for an operand which tests 306// two operands and returns a value in register T8 and 307//then does a conditional branch based on the value of T8 308// 309 310// op2 can be cmpi or slti/sltiu 311// op1 can bteqz or btnez 312// the operands for op2 are a register and a signed constant 313// 314// $op2 $t, $imm ;test register t and branch conditionally 315// $op1 .+4 ;op1 is a conditional branch 316// move $rd, $rs 317// 318// 319class SeliT<bits<5> f1, string op1, bits<5> f2, string op2, 320 InstrItinClass itin>: 321 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 322 CPU16Regs:$rl, simm16:$imm), 323 !strconcat(op2, 324 !strconcat("\t$rl, $imm\n\t", 325 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 326 Pseudo16> { 327 let isCodeGenOnly=1; 328 let Constraints = "$rd = $rd_"; 329} 330 331// 332// op2 can be cmp or slt/sltu 333// op1 can be bteqz or btnez 334// the operands for op2 are two registers 335// op1 is a conditional branch 336// 337// 338// $op2 $rl, $rr ;test registers rl,rr 339// $op1 .+4 ;op2 is a conditional branch 340// move $rd, $rs 341// 342// 343class SelT<bits<5> f1, string op1, bits<5> f2, string op2, 344 InstrItinClass itin>: 345 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 346 CPU16Regs:$rl, CPU16Regs:$rr), 347 !strconcat(op2, 348 !strconcat("\t$rl, $rr\n\t", 349 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin, 350 Pseudo16> { 351 let isCodeGenOnly=1; 352 let Constraints = "$rd = $rd_"; 353} 354 355 356// 357// Some general instruction class info 358// 359// 360 361class ArithLogic16Defs<bit isCom=0> { 362 bits<5> shamt = 0; 363 bit isCommutable = isCom; 364 bit isReMaterializable = 1; 365 bit neverHasSideEffects = 1; 366} 367 368class branch16 { 369 bit isBranch = 1; 370 bit isTerminator = 1; 371 bit isBarrier = 1; 372} 373 374class cbranch16 { 375 bit isBranch = 1; 376 bit isTerminator = 1; 377} 378 379class MayLoad { 380 bit mayLoad = 1; 381} 382 383class MayStore { 384 bit mayStore = 1; 385} 386// 387 388// Format: ADDIU rx, immediate MIPS16e 389// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 390// To add a constant to a 32-bit integer. 391// 392def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 393 394def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 395 ArithLogic16Defs<0>; 396 397def AddiuRxRyOffMemX16: 398 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 399 400// 401 402// Format: ADDIU rx, pc, immediate MIPS16e 403// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 404// To add a constant to the program counter. 405// 406def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 407// 408// Format: ADDU rz, rx, ry MIPS16e 409// Purpose: Add Unsigned Word (3-Operand) 410// To add 32-bit integers. 411// 412 413def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 414 415// 416// Format: AND rx, ry MIPS16e 417// Purpose: AND 418// To do a bitwise logical AND. 419 420def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 421 422 423// 424// Format: BEQZ rx, offset MIPS16e 425// Purpose: Branch on Equal to Zero (Extended) 426// To test a GPR then do a PC-relative conditional branch. 427// 428def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 429 430// Format: B offset MIPS16e 431// Purpose: Unconditional Branch 432// To do an unconditional PC-relative branch. 433// 434def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 435 436// 437// Format: BNEZ rx, offset MIPS16e 438// Purpose: Branch on Not Equal to Zero (Extended) 439// To test a GPR then do a PC-relative conditional branch. 440// 441def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 442 443// 444// Format: BTEQZ offset MIPS16e 445// Purpose: Branch on T Equal to Zero (Extended) 446// To test special register T then do a PC-relative conditional branch. 447// 448def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; 449 450def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16; 451 452def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>, 453 cbranch16; 454 455def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16; 456 457def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16; 458 459def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16; 460 461def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>, 462 cbranch16; 463 464// 465// Format: BTNEZ offset MIPS16e 466// Purpose: Branch on T Not Equal to Zero (Extended) 467// To test special register T then do a PC-relative conditional branch. 468// 469def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; 470 471def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16; 472 473def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16; 474 475def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16; 476 477def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16; 478 479def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16; 480 481def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>, 482 cbranch16; 483 484// 485// Format: DIV rx, ry MIPS16e 486// Purpose: Divide Word 487// To divide 32-bit signed integers. 488// 489def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 490 let Defs = [HI, LO]; 491} 492 493// 494// Format: DIVU rx, ry MIPS16e 495// Purpose: Divide Unsigned Word 496// To divide 32-bit unsigned integers. 497// 498def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 499 let Defs = [HI, LO]; 500} 501 502 503// 504// Format: JR ra MIPS16e 505// Purpose: Jump Register Through Register ra 506// To execute a branch to the instruction address in the return 507// address register. 508// 509 510def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 511 let isBranch = 1; 512 let isIndirectBranch = 1; 513 let hasDelaySlot = 1; 514 let isTerminator=1; 515 let isBarrier=1; 516} 517 518def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> { 519 let isBranch = 1; 520 let isIndirectBranch = 1; 521 let isTerminator=1; 522 let isBarrier=1; 523} 524 525def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 526 let isBranch = 1; 527 let isIndirectBranch = 1; 528 let isTerminator=1; 529 let isBarrier=1; 530} 531// 532// Format: LB ry, offset(rx) MIPS16e 533// Purpose: Load Byte (Extended) 534// To load a byte from memory as a signed value. 535// 536def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; 537 538// 539// Format: LBU ry, offset(rx) MIPS16e 540// Purpose: Load Byte Unsigned (Extended) 541// To load a byte from memory as a unsigned value. 542// 543def LbuRxRyOffMemX16: 544 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad; 545 546// 547// Format: LH ry, offset(rx) MIPS16e 548// Purpose: Load Halfword signed (Extended) 549// To load a halfword from memory as a signed value. 550// 551def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; 552 553// 554// Format: LHU ry, offset(rx) MIPS16e 555// Purpose: Load Halfword unsigned (Extended) 556// To load a halfword from memory as an unsigned value. 557// 558def LhuRxRyOffMemX16: 559 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad; 560 561// 562// Format: LI rx, immediate MIPS16e 563// Purpose: Load Immediate (Extended) 564// To load a constant into a GPR. 565// 566def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 567 568// 569// Format: LW ry, offset(rx) MIPS16e 570// Purpose: Load Word (Extended) 571// To load a word from memory as a signed value. 572// 573def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad; 574 575// Format: LW rx, offset(sp) MIPS16e 576// Purpose: Load Word (SP-Relative, Extended) 577// To load an SP-relative word from memory as a signed value. 578// 579def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad; 580 581// 582// Format: MOVE r32, rz MIPS16e 583// Purpose: Move 584// To move the contents of a GPR to a GPR. 585// 586def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 587 588// 589// Format: MOVE ry, r32 MIPS16e 590//Purpose: Move 591// To move the contents of a GPR to a GPR. 592// 593def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 594 595// 596// Format: MFHI rx MIPS16e 597// Purpose: Move From HI Register 598// To copy the special purpose HI register to a GPR. 599// 600def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 601 let Uses = [HI]; 602 let neverHasSideEffects = 1; 603} 604 605// 606// Format: MFLO rx MIPS16e 607// Purpose: Move From LO Register 608// To copy the special purpose LO register to a GPR. 609// 610def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 611 let Uses = [LO]; 612 let neverHasSideEffects = 1; 613} 614 615// 616// Pseudo Instruction for mult 617// 618def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 619 let isCommutable = 1; 620 let neverHasSideEffects = 1; 621 let Defs = [HI, LO]; 622} 623 624def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 625 let isCommutable = 1; 626 let neverHasSideEffects = 1; 627 let Defs = [HI, LO]; 628} 629 630// 631// Format: MULT rx, ry MIPS16e 632// Purpose: Multiply Word 633// To multiply 32-bit signed integers. 634// 635def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 636 let isCommutable = 1; 637 let neverHasSideEffects = 1; 638 let Defs = [HI, LO]; 639} 640 641// 642// Format: MULTU rx, ry MIPS16e 643// Purpose: Multiply Unsigned Word 644// To multiply 32-bit unsigned integers. 645// 646def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 647 let isCommutable = 1; 648 let neverHasSideEffects = 1; 649 let Defs = [HI, LO]; 650} 651 652// 653// Format: NEG rx, ry MIPS16e 654// Purpose: Negate 655// To negate an integer value. 656// 657def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 658 659// 660// Format: NOT rx, ry MIPS16e 661// Purpose: Not 662// To complement an integer value 663// 664def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 665 666// 667// Format: OR rx, ry MIPS16e 668// Purpose: Or 669// To do a bitwise logical OR. 670// 671def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 672 673// 674// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 675// (All args are optional) MIPS16e 676// Purpose: Restore Registers and Deallocate Stack Frame 677// To deallocate a stack frame before exit from a subroutine, 678// restoring return address and static registers, and adjusting 679// stack 680// 681 682// fixed form for restoring RA and the frame 683// for direct object emitter, encoding needs to be adjusted for the 684// frame size 685// 686let ra=1, s=0,s0=1,s1=1 in 687def RestoreRaF16: 688 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 689 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 690 let isCodeGenOnly = 1; 691} 692 693// 694// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 695// MIPS16e 696// Purpose: Save Registers and Set Up Stack Frame 697// To set up a stack frame on entry to a subroutine, 698// saving return address and static registers, and adjusting stack 699// 700let ra=1, s=1,s0=1,s1=1 in 701def SaveRaF16: 702 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 703 "save \t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 704 let isCodeGenOnly = 1; 705} 706// 707// Format: SB ry, offset(rx) MIPS16e 708// Purpose: Store Byte (Extended) 709// To store a byte to memory. 710// 711def SbRxRyOffMemX16: 712 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 713 714// 715// The Sel(T) instructions are pseudos 716// T means that they use T8 implicitly. 717// 718// 719// Format: SelBeqZ rd, rs, rt 720// Purpose: if rt==0, do nothing 721// else rs = rt 722// 723def SelBeqZ: Sel<0b00100, "beqz", IIAlu>; 724 725// 726// Format: SelTBteqZCmp rd, rs, rl, rr 727// Purpose: b = Cmp rl, rr. 728// If b==0 then do nothing. 729// if b!=0 then rd = rs 730// 731def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>; 732 733// 734// Format: SelTBteqZCmpi rd, rs, rl, rr 735// Purpose: b = Cmpi rl, imm. 736// If b==0 then do nothing. 737// if b!=0 then rd = rs 738// 739def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>; 740 741// 742// Format: SelTBteqZSlt rd, rs, rl, rr 743// Purpose: b = Slt rl, rr. 744// If b==0 then do nothing. 745// if b!=0 then rd = rs 746// 747def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>; 748 749// 750// Format: SelTBteqZSlti rd, rs, rl, rr 751// Purpose: b = Slti rl, imm. 752// If b==0 then do nothing. 753// if b!=0 then rd = rs 754// 755def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>; 756 757// 758// Format: SelTBteqZSltu rd, rs, rl, rr 759// Purpose: b = Sltu rl, rr. 760// If b==0 then do nothing. 761// if b!=0 then rd = rs 762// 763def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>; 764 765// 766// Format: SelTBteqZSltiu rd, rs, rl, rr 767// Purpose: b = Sltiu rl, imm. 768// If b==0 then do nothing. 769// if b!=0 then rd = rs 770// 771def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>; 772 773// 774// Format: SelBnez rd, rs, rt 775// Purpose: if rt!=0, do nothing 776// else rs = rt 777// 778def SelBneZ: Sel<0b00101, "bnez", IIAlu>; 779 780// 781// Format: SelTBtneZCmp rd, rs, rl, rr 782// Purpose: b = Cmp rl, rr. 783// If b!=0 then do nothing. 784// if b0=0 then rd = rs 785// 786def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>; 787 788// 789// Format: SelTBtnezCmpi rd, rs, rl, rr 790// Purpose: b = Cmpi rl, imm. 791// If b!=0 then do nothing. 792// if b==0 then rd = rs 793// 794def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>; 795 796// 797// Format: SelTBtneZSlt rd, rs, rl, rr 798// Purpose: b = Slt rl, rr. 799// If b!=0 then do nothing. 800// if b==0 then rd = rs 801// 802def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>; 803 804// 805// Format: SelTBtneZSlti rd, rs, rl, rr 806// Purpose: b = Slti rl, imm. 807// If b!=0 then do nothing. 808// if b==0 then rd = rs 809// 810def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>; 811 812// 813// Format: SelTBtneZSltu rd, rs, rl, rr 814// Purpose: b = Sltu rl, rr. 815// If b!=0 then do nothing. 816// if b==0 then rd = rs 817// 818def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>; 819 820// 821// Format: SelTBtneZSltiu rd, rs, rl, rr 822// Purpose: b = Slti rl, imm. 823// If b!=0 then do nothing. 824// if b==0 then rd = rs 825// 826def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>; 827// 828// 829// Format: SH ry, offset(rx) MIPS16e 830// Purpose: Store Halfword (Extended) 831// To store a halfword to memory. 832// 833def ShRxRyOffMemX16: 834 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 835 836// 837// Format: SLL rx, ry, sa MIPS16e 838// Purpose: Shift Word Left Logical (Extended) 839// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 840// 841def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 842 843// 844// Format: SLLV ry, rx MIPS16e 845// Purpose: Shift Word Left Logical Variable 846// To execute a left-shift of a word by a variable number of bits. 847// 848def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 849 850// 851// Format: SLTI rx, immediate MIPS16e 852// Purpose: Set on Less Than Immediate (Extended) 853// To record the result of a less-than comparison with a constant. 854// 855def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>; 856 857// 858// Format: SLTIU rx, immediate MIPS16e 859// Purpose: Set on Less Than Immediate Unsigned (Extended) 860// To record the result of a less-than comparison with a constant. 861// 862def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>; 863 864// 865// Format: SLT rx, ry MIPS16e 866// Purpose: Set on Less Than 867// To record the result of a less-than comparison. 868// 869def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; 870 871def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>; 872 873// Format: SLTU rx, ry MIPS16e 874// Purpose: Set on Less Than Unsigned 875// To record the result of an unsigned less-than comparison. 876// 877def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> { 878 let isCodeGenOnly=1; 879} 880 881 882def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>; 883// 884// Format: SRAV ry, rx MIPS16e 885// Purpose: Shift Word Right Arithmetic Variable 886// To execute an arithmetic right-shift of a word by a variable 887// number of bits. 888// 889def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 890 891 892// 893// Format: SRA rx, ry, sa MIPS16e 894// Purpose: Shift Word Right Arithmetic (Extended) 895// To execute an arithmetic right-shift of a word by a fixed 896// number of bits—1 to 8 bits. 897// 898def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 899 900 901// 902// Format: SRLV ry, rx MIPS16e 903// Purpose: Shift Word Right Logical Variable 904// To execute a logical right-shift of a word by a variable 905// number of bits. 906// 907def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 908 909 910// 911// Format: SRL rx, ry, sa MIPS16e 912// Purpose: Shift Word Right Logical (Extended) 913// To execute a logical right-shift of a word by a fixed 914// number of bits—1 to 31 bits. 915// 916def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 917 918// 919// Format: SUBU rz, rx, ry MIPS16e 920// Purpose: Subtract Unsigned Word 921// To subtract 32-bit integers 922// 923def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 924 925// 926// Format: SW ry, offset(rx) MIPS16e 927// Purpose: Store Word (Extended) 928// To store a word to memory. 929// 930def SwRxRyOffMemX16: 931 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 932 933// 934// Format: SW rx, offset(sp) MIPS16e 935// Purpose: Store Word rx (SP-Relative) 936// To store an SP-relative word to memory. 937// 938def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 939 940// 941// 942// Format: XOR rx, ry MIPS16e 943// Purpose: Xor 944// To do a bitwise logical XOR. 945// 946def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 947 948class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 949 let Predicates = [InMips16Mode]; 950} 951 952// Unary Arith/Logic 953// 954class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 955 Mips16Pat<(OpNode CPU16Regs:$r), 956 (I CPU16Regs:$r)>; 957 958def: ArithLogicU_pat<not, NotRxRy16>; 959def: ArithLogicU_pat<ineg, NegRxRy16>; 960 961class ArithLogic16_pat<SDNode OpNode, Instruction I> : 962 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 963 (I CPU16Regs:$l, CPU16Regs:$r)>; 964 965def: ArithLogic16_pat<add, AdduRxRyRz16>; 966def: ArithLogic16_pat<and, AndRxRxRy16>; 967def: ArithLogic16_pat<mul, MultRxRyRz16>; 968def: ArithLogic16_pat<or, OrRxRxRy16>; 969def: ArithLogic16_pat<sub, SubuRxRyRz16>; 970def: ArithLogic16_pat<xor, XorRxRxRy16>; 971 972// Arithmetic and logical instructions with 2 register operands. 973 974class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 975 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 976 (I CPU16Regs:$in, imm_type:$imm)>; 977 978def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 979def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 980def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 981def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 982 983class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 984 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 985 (I CPU16Regs:$r, CPU16Regs:$ra)>; 986 987def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 988def: shift_rotate_reg16_pat<sra, SravRxRy16>; 989def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 990 991class LoadM16_pat<PatFrag OpNode, Instruction I> : 992 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 993 994def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 995def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 996def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 997def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 998def: LoadM16_pat<load, LwRxRyOffMemX16>; 999 1000class StoreM16_pat<PatFrag OpNode, Instruction I> : 1001 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1002 (I CPU16Regs:$r, addr16:$addr)>; 1003 1004def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1005def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1006def: StoreM16_pat<store, SwRxRyOffMemX16>; 1007 1008// Unconditional branch 1009class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1010 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1011 let Predicates = [RelocPIC, InMips16Mode]; 1012 } 1013 1014// Indirect branch 1015def: Mips16Pat< 1016 (brind CPU16Regs:$rs), 1017 (JrcRx16 CPU16Regs:$rs)>; 1018 1019 1020// Jump and Link (Call) 1021let isCall=1, hasDelaySlot=0 in 1022def JumpLinkReg16: 1023 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1024 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1025 1026// Mips16 pseudos 1027let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1028 hasExtraSrcRegAllocReq = 1 in 1029def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1030 1031 1032// setcc patterns 1033 1034class SetCC_R16<PatFrag cond_op, Instruction I>: 1035 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1036 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1037 1038class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1039 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1040 (I CPU16Regs:$rx, imm_type:$imm16)>; 1041 1042 1043def: Mips16Pat<(i32 addr16:$addr), 1044 (AddiuRxRyOffMemX16 addr16:$addr)>; 1045 1046 1047// Large (>16 bit) immediate loads 1048def : Mips16Pat<(i32 imm:$imm), 1049 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1050 (LiRxImmX16 (LO16 imm:$imm)))>; 1051 1052// Carry MipsPatterns 1053def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1054 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1055def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1056 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1057def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1058 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1059 1060// 1061// Some branch conditional patterns are not generated by llvm at this time. 1062// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1063// comparison they are used and for unsigned a different pattern is used. 1064// I am pushing upstream from the full mips16 port and it seemed that I needed 1065// these earlier and the mips32 port has these but now I cannot create test 1066// cases that use these patterns. While I sort this all out I will leave these 1067// extra patterns commented out and if I can be sure they are really not used, 1068// I will delete the code. I don't want to check the code in uncommented without 1069// a valid test case. In some cases, the compiler is generating patterns with 1070// setcc instead and earlier I had implemented setcc first so may have masked 1071// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1072// figure out how to enable the brcond patterns or else possibly new 1073// combinations of of brcond and setcc. 1074// 1075// 1076// bcond-seteq 1077// 1078def: Mips16Pat 1079 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1080 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1081 >; 1082 1083 1084def: Mips16Pat 1085 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1086 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1087 >; 1088 1089def: Mips16Pat 1090 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1091 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1092 >; 1093 1094// 1095// bcond-setgt (do we need to have this pair of setlt, setgt??) 1096// 1097def: Mips16Pat 1098 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1099 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1100 >; 1101 1102// 1103// bcond-setge 1104// 1105def: Mips16Pat 1106 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1107 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1108 >; 1109 1110// 1111// never called because compiler transforms a >= k to a > (k-1) 1112def: Mips16Pat 1113 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1114 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1115 >; 1116 1117// 1118// bcond-setlt 1119// 1120def: Mips16Pat 1121 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1122 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1123 >; 1124 1125def: Mips16Pat 1126 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1127 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1128 >; 1129 1130// 1131// bcond-setle 1132// 1133def: Mips16Pat 1134 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1135 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1136 >; 1137 1138// 1139// bcond-setne 1140// 1141def: Mips16Pat 1142 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1143 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1144 >; 1145 1146def: Mips16Pat 1147 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1148 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1149 >; 1150 1151def: Mips16Pat 1152 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1153 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1154 >; 1155 1156// 1157// This needs to be there but I forget which code will generate it 1158// 1159def: Mips16Pat 1160 <(brcond CPU16Regs:$rx, bb:$targ16), 1161 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1162 >; 1163 1164// 1165 1166// 1167// bcond-setugt 1168// 1169//def: Mips16Pat 1170// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1171// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1172// >; 1173 1174// 1175// bcond-setuge 1176// 1177//def: Mips16Pat 1178// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1179// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1180// >; 1181 1182 1183// 1184// bcond-setult 1185// 1186//def: Mips16Pat 1187// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1188// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1189// >; 1190 1191def: UncondBranch16_pat<br, BimmX16>; 1192 1193// Small immediates 1194def: Mips16Pat<(i32 immSExt16:$in), 1195 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1196 1197def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1198 1199// 1200// MipsDivRem 1201// 1202def: Mips16Pat 1203 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry), 1204 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1205 1206// 1207// MipsDivRemU 1208// 1209def: Mips16Pat 1210 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry), 1211 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1212 1213// signed a,b 1214// x = (a>=b)?x:y 1215// 1216// if !(a < b) x = y 1217// 1218def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1219 CPU16Regs:$x, CPU16Regs:$y), 1220 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1221 CPU16Regs:$a, CPU16Regs:$b)>; 1222 1223// signed a,b 1224// x = (a>b)?x:y 1225// 1226// if (b < a) x = y 1227// 1228def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1229 CPU16Regs:$x, CPU16Regs:$y), 1230 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1231 CPU16Regs:$b, CPU16Regs:$a)>; 1232 1233// unsigned a,b 1234// x = (a>=b)?x:y 1235// 1236// if !(a < b) x = y; 1237// 1238def : Mips16Pat< 1239 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1240 CPU16Regs:$x, CPU16Regs:$y), 1241 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1242 CPU16Regs:$a, CPU16Regs:$b)>; 1243 1244// unsigned a,b 1245// x = (a>b)?x:y 1246// 1247// if (b < a) x = y 1248// 1249def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1250 CPU16Regs:$x, CPU16Regs:$y), 1251 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1252 CPU16Regs:$b, CPU16Regs:$a)>; 1253 1254// signed 1255// x = (a >= k)?x:y 1256// due to an llvm optimization, i don't think that this will ever 1257// be used. This is transformed into x = (a > k-1)?x:y 1258// 1259// 1260 1261//def : Mips16Pat< 1262// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1263// CPU16Regs:$T, CPU16Regs:$F), 1264// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1265// CPU16Regs:$lhs, immSExt16:$rhs)>; 1266 1267//def : Mips16Pat< 1268// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1269// CPU16Regs:$T, CPU16Regs:$F), 1270// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1271// CPU16Regs:$lhs, immSExt16:$rhs)>; 1272 1273// signed 1274// x = (a < k)?x:y 1275// 1276// if !(a < k) x = y; 1277// 1278def : Mips16Pat< 1279 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1280 CPU16Regs:$x, CPU16Regs:$y), 1281 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1282 CPU16Regs:$a, immSExt16:$b)>; 1283 1284 1285// 1286// 1287// signed 1288// x = (a <= b)? x : y 1289// 1290// if (b < a) x = y 1291// 1292def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1293 CPU16Regs:$x, CPU16Regs:$y), 1294 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1295 CPU16Regs:$b, CPU16Regs:$a)>; 1296 1297// 1298// unnsigned 1299// x = (a <= b)? x : y 1300// 1301// if (b < a) x = y 1302// 1303def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1304 CPU16Regs:$x, CPU16Regs:$y), 1305 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1306 CPU16Regs:$b, CPU16Regs:$a)>; 1307 1308// 1309// signed/unsigned 1310// x = (a == b)? x : y 1311// 1312// if (a != b) x = y 1313// 1314def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1315 CPU16Regs:$x, CPU16Regs:$y), 1316 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1317 CPU16Regs:$b, CPU16Regs:$a)>; 1318 1319// 1320// signed/unsigned 1321// x = (a == 0)? x : y 1322// 1323// if (a != 0) x = y 1324// 1325def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1326 CPU16Regs:$x, CPU16Regs:$y), 1327 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1328 CPU16Regs:$a)>; 1329 1330 1331// 1332// signed/unsigned 1333// x = (a == k)? x : y 1334// 1335// if (a != k) x = y 1336// 1337def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1338 CPU16Regs:$x, CPU16Regs:$y), 1339 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1340 CPU16Regs:$a, immZExt16:$k)>; 1341 1342 1343// 1344// signed/unsigned 1345// x = (a != b)? x : y 1346// 1347// if (a == b) x = y 1348// 1349// 1350def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1351 CPU16Regs:$x, CPU16Regs:$y), 1352 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1353 CPU16Regs:$b, CPU16Regs:$a)>; 1354 1355// 1356// signed/unsigned 1357// x = (a != 0)? x : y 1358// 1359// if (a == 0) x = y 1360// 1361def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1362 CPU16Regs:$x, CPU16Regs:$y), 1363 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1364 CPU16Regs:$a)>; 1365 1366// signed/unsigned 1367// x = (a)? x : y 1368// 1369// if (!a) x = y 1370// 1371def : Mips16Pat<(select CPU16Regs:$a, 1372 CPU16Regs:$x, CPU16Regs:$y), 1373 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1374 CPU16Regs:$a)>; 1375 1376 1377// 1378// signed/unsigned 1379// x = (a != k)? x : y 1380// 1381// if (a == k) x = y 1382// 1383def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1384 CPU16Regs:$x, CPU16Regs:$y), 1385 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1386 CPU16Regs:$a, immZExt16:$k)>; 1387 1388// 1389// When writing C code to test setxx these patterns, 1390// some will be transformed into 1391// other things. So we test using C code but using -O3 and -O0 1392// 1393// seteq 1394// 1395def : Mips16Pat 1396 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1397 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1398 1399def : Mips16Pat 1400 <(seteq CPU16Regs:$lhs, 0), 1401 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1402 1403 1404// 1405// setge 1406// 1407 1408def: Mips16Pat 1409 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1410 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1411 (LiRxImmX16 1))>; 1412 1413// 1414// For constants, llvm transforms this to: 1415// x > (k -1) and then reverses the operands to use setlt. So this pattern 1416// is not used now by the compiler. (Presumably checking that k-1 does not 1417// overflow). The compiler never uses this at a the current time, due to 1418// other optimizations. 1419// 1420//def: Mips16Pat 1421// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1422// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1423// (LiRxImmX16 1))>; 1424 1425// This catches the x >= -32768 case by transforming it to x > -32769 1426// 1427def: Mips16Pat 1428 <(setgt CPU16Regs:$lhs, -32769), 1429 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1430 (LiRxImmX16 1))>; 1431 1432// 1433// setgt 1434// 1435// 1436 1437def: Mips16Pat 1438 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1439 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1440 1441// 1442// setle 1443// 1444def: Mips16Pat 1445 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1446 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1447 1448// 1449// setlt 1450// 1451def: SetCC_R16<setlt, SltCCRxRy16>; 1452 1453def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1454 1455// 1456// setne 1457// 1458def : Mips16Pat 1459 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1460 (SltuCCRxRy16 (LiRxImmX16 0), 1461 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1462 1463 1464// 1465// setuge 1466// 1467def: Mips16Pat 1468 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1469 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1470 (LiRxImmX16 1))>; 1471 1472// this pattern will never be used because the compiler will transform 1473// x >= k to x > (k - 1) and then use SLT 1474// 1475//def: Mips16Pat 1476// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1477// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1478// (LiRxImmX16 1))>; 1479 1480// 1481// setugt 1482// 1483def: Mips16Pat 1484 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1485 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1486 1487// 1488// setule 1489// 1490def: Mips16Pat 1491 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1492 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1493 1494// 1495// setult 1496// 1497def: SetCC_R16<setult, SltuCCRxRy16>; 1498 1499def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1500 1501def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1502 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1503 1504// hi/lo relocs 1505 1506def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1507 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1508 1509// wrapper_pic 1510class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1511 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1512 (ADDiuOp RC:$gp, node:$in)>; 1513 1514 1515def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1516def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1517 1518def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1519 (LbuRxRyOffMemX16 addr16:$src)>; 1520def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1521 (LhuRxRyOffMemX16 addr16:$src)>;