Mips16InstrInfo.td revision dfb8dbb4fd97140aa9bf6b9dadbca25665144c09
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// This are pseudo formats for multiply 15// This first one can be changed to non pseudo now. 16//fmul 17class FMULT16_ins<string asmstr, InstrItinClass itin> : 18 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 19 !strconcat(asmstr, "\t$rx, $ry"), []>; 20 21class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 22 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 23 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 24 let isCodeGenOnly=1; 25} 26// 27// RRR-type instruction format 28// 29 30class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 31 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 32 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 33 34// 35// I8_MOVR32 instruction format (used only by the MOVR32 instructio 36// 37class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 38 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 39 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 40 41// 42// I8_MOV32R instruction format (used only by MOV32R instruction) 43// 44 45class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 46 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 47 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 48 49 50// 51// RR-type instruction format 52// 53 54class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 55 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 56 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 57} 58class FRR16_M_ins<bits<5> f, string asmstr, 59 InstrItinClass itin> : 60 FRR16<f, (outs CPU16Regs:$rx), (ins), 61 !strconcat(asmstr, "\t$rx"), [], itin>; 62 63class FRxRxRy16_ins<bits<5> f, string asmstr, 64 InstrItinClass itin> : 65 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 66 !strconcat(asmstr, "\t$rz, $ry"), 67 [], itin> { 68 let Constraints = "$rx = $rz"; 69} 70 71let rx=0 in 72class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 73 string asmstr, InstrItinClass itin>: 74 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 75 [], itin> ; 76 77// 78// EXT-RI instruction format 79// 80 81class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 82 InstrItinClass itin>: 83 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 84 !strconcat(asmstr, asmstr2), [], itin>; 85 86class FEXT_RI16_ins<bits<5> _op, string asmstr, 87 InstrItinClass itin>: 88 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 89 90class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 91 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 92 93 94class FEXT_2RI16_ins<bits<5> _op, string asmstr, 95 InstrItinClass itin>: 96 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 97 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 98 let Constraints = "$rx_ = $rx"; 99} 100 101// this has an explicit sp argument that we ignore to work around a problem 102// in the compiler 103class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 104 InstrItinClass itin>: 105 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 106 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 107 108// 109// EXT-RRI instruction format 110// 111 112class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 113 InstrItinClass itin>: 114 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 115 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 116 117class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 118 InstrItinClass itin>: 119 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 120 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 121 122// 123// EXT-SHIFT instruction format 124// 125class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 126 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 127 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 128 129// 130// Address operand 131def mem16 : Operand<i32> { 132 let PrintMethod = "printMemOperand"; 133 let MIOperandInfo = (ops CPU16Regs, simm16); 134 let EncoderMethod = "getMemEncoding"; 135} 136 137// 138// Some general instruction class info 139// 140// 141 142class ArithLogic16Defs<bit isCom=0> { 143 bits<5> shamt = 0; 144 bit isCommutable = isCom; 145 bit isReMaterializable = 1; 146 bit neverHasSideEffects = 1; 147} 148 149class MayLoad { 150 bit mayLoad = 1; 151} 152 153class MayStore { 154 bit mayStore = 1; 155} 156// 157 158// Format: ADDIU rx, immediate MIPS16e 159// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 160// To add a constant to a 32-bit integer. 161// 162def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 163 164def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 165 ArithLogic16Defs<0>; 166 167// 168 169// Format: ADDIU rx, pc, immediate MIPS16e 170// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 171// To add a constant to the program counter. 172// 173def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 174// 175// Format: ADDU rz, rx, ry MIPS16e 176// Purpose: Add Unsigned Word (3-Operand) 177// To add 32-bit integers. 178// 179 180def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 181 182// 183// Format: AND rx, ry MIPS16e 184// Purpose: AND 185// To do a bitwise logical AND. 186 187def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 188 189// 190// Format: JR ra MIPS16e 191// Purpose: Jump Register Through Register ra 192// To execute a branch to the instruction address in the return 193// address register. 194// 195 196def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>; 197 198// 199// Format: LB ry, offset(rx) MIPS16e 200// Purpose: Load Byte (Extended) 201// To load a byte from memory as a signed value. 202// 203def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad; 204 205// 206// Format: LBU ry, offset(rx) MIPS16e 207// Purpose: Load Byte Unsigned (Extended) 208// To load a byte from memory as a unsigned value. 209// 210def LbuRxRyOffMemX16: 211 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad; 212 213// 214// Format: LH ry, offset(rx) MIPS16e 215// Purpose: Load Halfword signed (Extended) 216// To load a halfword from memory as a signed value. 217// 218def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad; 219 220// 221// Format: LHU ry, offset(rx) MIPS16e 222// Purpose: Load Halfword unsigned (Extended) 223// To load a halfword from memory as an unsigned value. 224// 225def LhuRxRyOffMemX16: 226 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad; 227 228// 229// Format: LI rx, immediate MIPS16e 230// Purpose: Load Immediate (Extended) 231// To load a constant into a GPR. 232// 233def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 234 235// 236// Format: LW ry, offset(rx) MIPS16e 237// Purpose: Load Word (Extended) 238// To load a word from memory as a signed value. 239// 240def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad; 241 242// Format: LW rx, offset(sp) MIPS16e 243// Purpose: Load Word (SP-Relative, Extended) 244// To load an SP-relative word from memory as a signed value. 245// 246def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad; 247 248// 249// Format: MOVE r32, rz MIPS16e 250// Purpose: Move 251// To move the contents of a GPR to a GPR. 252// 253def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 254 255// 256// Format: MOVE ry, r32 MIPS16e 257//Purpose: Move 258// To move the contents of a GPR to a GPR. 259// 260def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 261 262// 263// Format: MFHI rx MIPS16e 264// Purpose: Move From HI Register 265// To copy the special purpose HI register to a GPR. 266// 267def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 268 let Uses = [HI]; 269 let neverHasSideEffects = 1; 270} 271 272// 273// Format: MFLO rx MIPS16e 274// Purpose: Move From LO Register 275// To copy the special purpose LO register to a GPR. 276// 277def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 278 let Uses = [LO]; 279 let neverHasSideEffects = 1; 280} 281 282// 283// Pseudo Instruction for mult 284// 285def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 286 let isCommutable = 1; 287 let neverHasSideEffects = 1; 288 let Defs = [HI, LO]; 289} 290 291def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 292 let isCommutable = 1; 293 let neverHasSideEffects = 1; 294 let Defs = [HI, LO]; 295} 296 297// 298// Format: MULT rx, ry MIPS16e 299// Purpose: Multiply Word 300// To multiply 32-bit signed integers. 301// 302def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 303 let isCommutable = 1; 304 let neverHasSideEffects = 1; 305 let Defs = [HI, LO]; 306} 307 308// 309// Format: MULTU rx, ry MIPS16e 310// Purpose: Multiply Unsigned Word 311// To multiply 32-bit unsigned integers. 312// 313def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 314 let isCommutable = 1; 315 let neverHasSideEffects = 1; 316 let Defs = [HI, LO]; 317} 318 319// 320// Format: NEG rx, ry MIPS16e 321// Purpose: Negate 322// To negate an integer value. 323// 324def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>; 325 326// 327// Format: NOT rx, ry MIPS16e 328// Purpose: Not 329// To complement an integer value 330// 331def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>; 332 333// 334// Format: OR rx, ry MIPS16e 335// Purpose: Or 336// To do a bitwise logical OR. 337// 338def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 339 340// 341// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 342// (All args are optional) MIPS16e 343// Purpose: Restore Registers and Deallocate Stack Frame 344// To deallocate a stack frame before exit from a subroutine, 345// restoring return address and static registers, and adjusting 346// stack 347// 348 349// fixed form for restoring RA and the frame 350// for direct object emitter, encoding needs to be adjusted for the 351// frame size 352// 353let ra=1, s=0,s0=1,s1=1 in 354def RestoreRaF16: 355 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 356 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 357 let isCodeGenOnly = 1; 358} 359 360// 361// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 362// MIPS16e 363// Purpose: Save Registers and Set Up Stack Frame 364// To set up a stack frame on entry to a subroutine, 365// saving return address and static registers, and adjusting stack 366// 367let ra=1, s=1,s0=1,s1=1 in 368def SaveRaF16: 369 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 370 "save \t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 371 let isCodeGenOnly = 1; 372} 373// 374// Format: SB ry, offset(rx) MIPS16e 375// Purpose: Store Byte (Extended) 376// To store a byte to memory. 377// 378def SbRxRyOffMemX16: 379 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 380 381// 382// Format: SH ry, offset(rx) MIPS16e 383// Purpose: Store Halfword (Extended) 384// To store a halfword to memory. 385// 386def ShRxRyOffMemX16: 387 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 388 389// 390// Format: SLL rx, ry, sa MIPS16e 391// Purpose: Shift Word Left Logical (Extended) 392// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 393// 394def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 395 396// 397// Format: SLLV ry, rx MIPS16e 398// Purpose: Shift Word Left Logical Variable 399// To execute a left-shift of a word by a variable number of bits. 400// 401def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 402 403 404// 405// Format: SRAV ry, rx MIPS16e 406// Purpose: Shift Word Right Arithmetic Variable 407// To execute an arithmetic right-shift of a word by a variable 408// number of bits. 409// 410def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 411 412 413// 414// Format: SRA rx, ry, sa MIPS16e 415// Purpose: Shift Word Right Arithmetic (Extended) 416// To execute an arithmetic right-shift of a word by a fixed 417// number of bits—1 to 8 bits. 418// 419def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 420 421 422// 423// Format: SRLV ry, rx MIPS16e 424// Purpose: Shift Word Right Logical Variable 425// To execute a logical right-shift of a word by a variable 426// number of bits. 427// 428def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 429 430 431// 432// Format: SRL rx, ry, sa MIPS16e 433// Purpose: Shift Word Right Logical (Extended) 434// To execute a logical right-shift of a word by a fixed 435// number of bits—1 to 31 bits. 436// 437def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 438 439// 440// Format: SUBU rz, rx, ry MIPS16e 441// Purpose: Subtract Unsigned Word 442// To subtract 32-bit integers 443// 444def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 445 446// 447// Format: SW ry, offset(rx) MIPS16e 448// Purpose: Store Word (Extended) 449// To store a word to memory. 450// 451def SwRxRyOffMemX16: 452 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 453 454// 455// Format: SW rx, offset(sp) MIPS16e 456// Purpose: Store Word rx (SP-Relative) 457// To store an SP-relative word to memory. 458// 459def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 460 461// 462// 463// Format: XOR rx, ry MIPS16e 464// Purpose: Xor 465// To do a bitwise logical XOR. 466// 467def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 468 469class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 470 let Predicates = [InMips16Mode]; 471} 472 473// Unary Arith/Logic 474// 475class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 476 Mips16Pat<(OpNode CPU16Regs:$r), 477 (I CPU16Regs:$r)>; 478 479def: ArithLogicU_pat<not, NotRxRy16>; 480def: ArithLogicU_pat<ineg, NegRxRy16>; 481 482class ArithLogic16_pat<SDNode OpNode, Instruction I> : 483 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 484 (I CPU16Regs:$l, CPU16Regs:$r)>; 485 486def: ArithLogic16_pat<add, AdduRxRyRz16>; 487def: ArithLogic16_pat<and, AndRxRxRy16>; 488def: ArithLogic16_pat<mul, MultRxRyRz16>; 489def: ArithLogic16_pat<or, OrRxRxRy16>; 490def: ArithLogic16_pat<sub, SubuRxRyRz16>; 491def: ArithLogic16_pat<xor, XorRxRxRy16>; 492 493// Arithmetic and logical instructions with 2 register operands. 494 495class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 496 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 497 (I CPU16Regs:$in, imm_type:$imm)>; 498 499def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 500def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 501def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 502def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 503 504class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 505 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 506 (I CPU16Regs:$r, CPU16Regs:$ra)>; 507 508def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 509def: shift_rotate_reg16_pat<sra, SravRxRy16>; 510def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 511 512class LoadM16_pat<PatFrag OpNode, Instruction I> : 513 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>; 514 515def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 516def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 517def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 518def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 519def: LoadM16_pat<load, LwRxRyOffMemX16>; 520 521class StoreM16_pat<PatFrag OpNode, Instruction I> : 522 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>; 523 524def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 525def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 526def: StoreM16_pat<store, SwRxRyOffMemX16>; 527 528 529// Jump and Link (Call) 530let isCall=1, hasDelaySlot=1 in 531def JumpLinkReg16: 532 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 533 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 534 535// Mips16 pseudos 536let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 537 hasExtraSrcRegAllocReq = 1 in 538def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 539 540// Small immediates 541def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 542 543def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 544 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 545