Mips16InstrInfo.td revision f5926fd844a84adcf1ae4f193146f2877997b82c
1b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 277349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 377349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// The LLVM Compiler Infrastructure 477349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 577349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// This file is distributed under the University of Illinois Open Source 677349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// License. See LICENSE.TXT for details. 777349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 877349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek//===----------------------------------------------------------------------===// 977349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 10b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// This file describes Mips16 instructions. 1141573ebf8fb971f40fa8a3e20648362c359b4916Ted Kremenek// 12b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek//===----------------------------------------------------------------------===// 1377349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 1477349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 1577349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// Mips Address 16d065d6080f0620bb80b933f3f5d52d37bb2ea770Ted Kremenek// 17d065d6080f0620bb80b933f3f5d52d37bb2ea770Ted Kremenekdef addr16 : 18d065d6080f0620bb80b933f3f5d52d37bb2ea770Ted Kremenek ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>; 1977349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek 204adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek// 2199c6ad3f22b865d0f4cce52bc36904403c9ed4c4Ted Kremenek// Address operand 2277349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenekdef mem16 : Operand<i32> { 23cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek let PrintMethod = "printMemOperand"; 24c0c3f5dbc9e78aa53a86c7d5e3eeda23ddad93d6Ted Kremenek let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs); 25f494b579b22f9950f5af021f0bf9879a91bb8b41Steve Naroff let EncoderMethod = "getMemEncoding"; 2677349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek} 2750a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek 2877349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenekdef mem16_ea : Operand<i32> { 2950a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek let PrintMethod = "printMemOperandEA"; 3050a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek let MIOperandInfo = (ops CPU16Regs, simm16); 31f494b579b22f9950f5af021f0bf9879a91bb8b41Steve Naroff let EncoderMethod = "getMemEncoding"; 32cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek} 33b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 344adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek// 3550a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek// 36aa1c4e5a6b87b62d991c55a0d4522bcd778068d7Ted Kremenek// I8 instruction format 37b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 38b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 3950a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenekclass FI816_ins_base<bits<3> _func, string asmstr, 4050a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek string asmstr2, InstrItinClass itin>: 4150a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 4250a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek [], itin>; 4311062b118476368fa5b294954713e5df97d8599fTed Kremenek 4450a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek 4577349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenekclass FI816_SP_ins<bits<3> _func, string asmstr, 46b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek InstrItinClass itin>: 4750a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 4850a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek 49b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 50b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// RI instruction format 51b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 52b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 53b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 548b23361a6a50be6dbd1056add570eb90598474b0Ted Kremenekclass FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 55241677a13cc46647a8f5098b3e3239bd9480dca2Ted Kremenek InstrItinClass itin>: 56b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 57b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(asmstr, asmstr2), [], itin>; 58b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 59b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass FRI16_ins<bits<5> op, string asmstr, 60b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek InstrItinClass itin>: 614adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 62cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek 63b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 64b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek InstrItinClass itin>: 65b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 66846d4e923bf11bcdc2816758aafa331795f29230Ted Kremenek !strconcat(asmstr, asmstr2), [], itin>; 67846d4e923bf11bcdc2816758aafa331795f29230Ted Kremenek 68846d4e923bf11bcdc2816758aafa331795f29230Ted Kremenekclass FRI16R_ins<bits<5> op, string asmstr, 69846d4e923bf11bcdc2816758aafa331795f29230Ted Kremenek InstrItinClass itin>: 700d093d3005dd583675a45a85bd688063572cc8afTed Kremenek FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 714adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek 720d093d3005dd583675a45a85bd688063572cc8afTed Kremenekclass F2RI16_ins<bits<5> _op, string asmstr, 73b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek InstrItinClass itin>: 74b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 7599c6ad3f22b865d0f4cce52bc36904403c9ed4c4Ted Kremenek !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 76e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenek let Constraints = "$rx_ = $rx"; 77e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenek} 78e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenek 79e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenekclass FRI16_B_ins<bits<5> _op, string asmstr, 80e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenek InstrItinClass itin>: 81e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenek FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 82e448ab4f9dd162802f5d7cfea60f7830cc61c654Ted Kremenek !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 83bdb435ddaafd5069becd543d638112f68825b89dTed Kremenek// 84ff944a8c481d6c0f1ad2633e4be9bf8b1dd2a09fZhongxing Xu// Compare a register and immediate and place result in CC 85ff944a8c481d6c0f1ad2633e4be9bf8b1dd2a09fZhongxing Xu// Implicit use of T8 86ff944a8c481d6c0f1ad2633e4be9bf8b1dd2a09fZhongxing Xu// 8799c6ad3f22b865d0f4cce52bc36904403c9ed4c4Ted Kremenek// EXT-CCRR Instruction format 88cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek// 89cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenekclass FEXT_CCRXI16_ins<string asmstr>: 90cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 91cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 92cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek let isCodeGenOnly=1; 9348af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek let usesCustomInserter = 1; 9448af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek} 9548af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek 9648af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek// JAL and JALX instruction format 9748af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek// 9848af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenekclass FJAL16_ins<bits<1> _X, string asmstr, 9948af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek InstrItinClass itin>: 10048af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek FJAL16<_X, (outs), (ins simm20:$imm), 10148af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek !strconcat(asmstr, "\t$imm\n\tnop"),[], 102b22d589e2ccd09cada0bcea136f0966883a8bb11Ted Kremenek itin> { 103efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek let isCodeGenOnly=1; 1041e80aa49ec689d1937e54fb353d6626e0a58f0dbTed Kremenek} 105b22d589e2ccd09cada0bcea136f0966883a8bb11Ted Kremenek// 10621fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek// EXT-I instruction format 10721fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek// 10821fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenekclass FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 10921fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek FEXT_I16<eop, (outs), (ins brtarget:$imm16), 11021fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek !strconcat(asmstr, "\t$imm16"),[], itin>; 11121fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek 11221fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek// 11321fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek// EXT-I8 instruction format 11421fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek// 11521fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek 11602737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenekclass FEXT_I816_ins_base<bits<3> _func, string asmstr, 11702737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek string asmstr2, InstrItinClass itin>: 118efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 1195917d7894e8274b9625275dd4dd86c5d0040a242Ted Kremenek [], itin>; 1205917d7894e8274b9625275dd4dd86c5d0040a242Ted Kremenek 1215917d7894e8274b9625275dd4dd86c5d0040a242Ted Kremenekclass FEXT_I816_ins<bits<3> _func, string asmstr, 122efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek InstrItinClass itin>: 123b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 1244a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek 1254a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenekclass FEXT_I816_SP_ins<bits<3> _func, string asmstr, 126efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek InstrItinClass itin>: 127b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 1284a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek 1294a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek// 130efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// Assembler formats in alphabetical order. 1319dca062461a6244cf0f733346657fa3eee853f9bTed Kremenek// Natural and pseudos are mixed together. 132affb2159712b2373a18a89ed205c1a309d3aec12Ted Kremenek// 133affb2159712b2373a18a89ed205c1a309d3aec12Ted Kremenek// Compare two registers and place result in CC 134efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// Implicit use of T8 135affb2159712b2373a18a89ed205c1a309d3aec12Ted Kremenek// 136b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// CC-RR Instruction format 13707d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek// 138efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenekclass FCCRR16_ins<string asmstr> : 13907d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 14007d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 14107d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek let isCodeGenOnly=1; 142efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek let usesCustomInserter = 1; 14307d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek} 14407d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek 1454a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek// 146efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// EXT-RI instruction format 14707d83aa220567bef263ef76cfc9b0159320bb640Ted Kremenek// 1484d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek 1494d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenekclass FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 1504d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek InstrItinClass itin>: 151efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 1524d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek !strconcat(asmstr, asmstr2), [], itin>; 1534d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek 1544d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenekclass FEXT_RI16_ins<bits<5> _op, string asmstr, 1554d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek InstrItinClass itin>: 156efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 157efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek 158159d2487e6b49f0aa64c44aef96bc9d643929931Ted Kremenekclass FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 159efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek InstrItinClass itin>: 160159d2487e6b49f0aa64c44aef96bc9d643929931Ted Kremenek FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 161efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek !strconcat(asmstr, asmstr2), [], itin>; 162159d2487e6b49f0aa64c44aef96bc9d643929931Ted Kremenek 163efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenekclass FEXT_RI16R_ins<bits<5> _op, string asmstr, 164159d2487e6b49f0aa64c44aef96bc9d643929931Ted Kremenek InstrItinClass itin>: 165b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 1668cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek 1678cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenekclass FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 168efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 1698cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek 1705e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenekclass FEXT_RI16_B_ins<bits<5> _op, string asmstr, 1715e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek InstrItinClass itin>: 172efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 1735e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 17423a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenek 17523a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenekclass FEXT_2RI16_ins<bits<5> _op, string asmstr, 176efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek InstrItinClass itin>: 17723a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenek FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 1782ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 1792ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek let Constraints = "$rx_ = $rx"; 1802ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek} 1812ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek 18223a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenek 18323a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenek// this has an explicit sp argument that we ignore to work around a problem 18423a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenek// in the compiler 18523a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenekclass FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 1861c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu InstrItinClass itin>: 1871c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 1881c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 189efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek 1901c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// 1911c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// EXT-RRI instruction format 1921c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// 193efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek 19423a4f917cd8d1090be7c96c4eda8643086f64d36Ted Kremenekclass FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 195b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek InstrItinClass itin>: 19695c7b00fe857a61a19185483aa0d85492ec9e258Ted Kremenek FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 197cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 19848af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek 19922438a8dfe9f2f273c0b1a47f3f80be782ea6f09Zhongxing Xuclass FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 20022438a8dfe9f2f273c0b1a47f3f80be782ea6f09Zhongxing Xu InstrItinClass itin>: 201cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 20250a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 20350a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek 20450a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek// 20550a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek// 206b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// EXT-RRI-A instruction format 207b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 208b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 209b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 210b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek InstrItinClass itin>: 211b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 212b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 213b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 214729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// 215729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// EXT-SHIFT instruction format 216cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenek// 217cf118d41f7930a18dce97416ef7834a62642f587Ted Kremenekclass FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 218b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa), 21950a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 22050a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek 22150a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek// 22250a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek// EXT-T8I8 22350a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek// 224b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass FEXT_T8I816_ins<string asmstr, string asmstr2>: 225e01c98767dfd7153c3c84637c36659e3bbe16ff7Ted Kremenek MipsPseudo16<(outs), 226e01c98767dfd7153c3c84637c36659e3bbe16ff7Ted Kremenek (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 227ffe0f43806d4823271c2406c1fccc2373115c36aTed Kremenek !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 228e01c98767dfd7153c3c84637c36659e3bbe16ff7Ted Kremenek !strconcat(asmstr, "\t$imm"))),[]> { 229493d7a26d5ea319770ba904b43f2740d43b820cbTed Kremenek let isCodeGenOnly=1; 230493d7a26d5ea319770ba904b43f2740d43b820cbTed Kremenek let usesCustomInserter = 1; 231d2f642b56e87493edfc3b0dab359b5e32d5f8a5eTed Kremenek} 232d2f642b56e87493edfc3b0dab359b5e32d5f8a5eTed Kremenek 233d2f642b56e87493edfc3b0dab359b5e32d5f8a5eTed Kremenek// 234d2f642b56e87493edfc3b0dab359b5e32d5f8a5eTed Kremenek// EXT-T8I8I 235d2f642b56e87493edfc3b0dab359b5e32d5f8a5eTed Kremenek// 236b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 237b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek MipsPseudo16<(outs), 2384adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 239b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 24050a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek !strconcat(asmstr, "\t$targ"))), []> { 24150a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek let isCodeGenOnly=1; 24250a6d0ce344c02782e0207574005c3b2aaa5077cTed Kremenek let usesCustomInserter = 1; 24378d46242e3351484c2b773f5610beba5d316914bTed Kremenek} 24478d46242e3351484c2b773f5610beba5d316914bTed Kremenek// 24502737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek 24602737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek 24702737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek// 24802737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek// I8_MOVR32 instruction format (used only by the MOVR32 instructio 2494a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek// 2504a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenekclass FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 251b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32), 252b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 2534a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek 2544a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek// 2559dca062461a6244cf0f733346657fa3eee853f9bTed Kremenek// I8_MOV32R instruction format (used only by MOV32R instruction) 2569dca062461a6244cf0f733346657fa3eee853f9bTed Kremenek// 257b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 258b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 259b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz), 260b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 261b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 262b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 263b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// This are pseudo formats for multiply 264b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// This first one can be changed to non pseudo now. 2654a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek// 2664a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek// MULT 267b5339121f63f2754d4f26e8f3a092caf9f7d9290Ted Kremenek// 268b5339121f63f2754d4f26e8f3a092caf9f7d9290Ted Kremenekclass FMULT16_ins<string asmstr, InstrItinClass itin> : 2694d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 2701c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu !strconcat(asmstr, "\t$rx, $ry"), []>; 2714d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek 2724d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// 2734d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// MULT-LO 2741c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// 275d763eb91aab5bdecd11825fadb35d6d8cc905f63Ted Kremenekclass FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 276d763eb91aab5bdecd11825fadb35d6d8cc905f63Ted Kremenek MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 277affb2159712b2373a18a89ed205c1a309d3aec12Ted Kremenek !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 278affb2159712b2373a18a89ed205c1a309d3aec12Ted Kremenek let isCodeGenOnly=1; 279affb2159712b2373a18a89ed205c1a309d3aec12Ted Kremenek} 2808cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek 2818cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek// 2828cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek// RR-type instruction format 2838cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek// 2848cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek 2855e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenekclass FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 2865e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 2875e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 2885e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek} 2892ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek 2901e80aa49ec689d1937e54fb353d6626e0a58f0dbTed Kremenekclass FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : 291dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 2921c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 293dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek} 294dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek 295dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenekclass FRRTR16_ins<string asmstr> : 296dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 2972ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 2982ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek 299efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// 30002737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek// maybe refactor but need a $zero as a dummy first parameter 30102737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek// 30202737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenekclass FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 303efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 3045917d7894e8274b9625275dd4dd86c5d0040a242Ted Kremenek !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 3055917d7894e8274b9625275dd4dd86c5d0040a242Ted Kremenek 3065917d7894e8274b9625275dd4dd86c5d0040a242Ted Kremenekclass FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 307efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 3081b9df4c307b650526344ba0a28534268f6920745Ted Kremenek !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 3091b9df4c307b650526344ba0a28534268f6920745Ted Kremenek 3101b9df4c307b650526344ba0a28534268f6920745Ted Kremenek 311efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenekclass FRR16_M_ins<bits<5> f, string asmstr, 312d87a321a3c3902f7acfc6539b8946a00da6e45ccTed Kremenek InstrItinClass itin> : 313d87a321a3c3902f7acfc6539b8946a00da6e45ccTed Kremenek FRR16<f, (outs CPU16Regs:$rx), (ins), 314d87a321a3c3902f7acfc6539b8946a00da6e45ccTed Kremenek !strconcat(asmstr, "\t$rx"), [], itin>; 3157360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenek 3167360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenekclass FRxRxRy16_ins<bits<5> f, string asmstr, 3177360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenek InstrItinClass itin> : 3187360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenek FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 3197360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenek !strconcat(asmstr, "\t$rz, $ry"), 3207360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenek [], itin> { 3217360fda1efd88fd28ca2882579676dbd8569c181Ted Kremenek let Constraints = "$rx = $rz"; 32221fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek} 32321fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek 32421fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremeneklet rx=0 in 32521fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenekclass FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 32621fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek string asmstr, InstrItinClass itin>: 32721fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 32821fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek [], itin> ; 32921fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek 33021fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenek 33121fe8370f660a30e3a0493c74728dcb369b9c58bTed Kremenekclass FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 332efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek string asmstr, InstrItinClass itin>: 3334a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 3344a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek !strconcat(asmstr, "\t $rx"), [], itin> ; 335d87a321a3c3902f7acfc6539b8946a00da6e45ccTed Kremenek 336efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// 3374d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// RRR-type instruction format 3384d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// 3394d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek 3404d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenekclass FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 3414d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 3424d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 3434d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek 3444d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// 3454d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// These Sel patterns support the generation of conditional move 3464d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// pseudo instructions. 3474d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// 3484d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// The nomenclature uses the components making up the pseudo and may 3494d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// be a bit counter intuitive when compared with the end result we seek. 3504d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// For example using a bqez in the example directly below results in the 3514d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// conditional move being done if the tested register is not zero. 3524d839b4949efe9e2b16eeab679c25b28e31ea742Ted Kremenek// I considered in easier to check by keeping the pseudo consistent with 353b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// it's components but it could have been done differently. 354efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// 3558cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek// The simplest case is when can test and operand directly and do the 3568cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek// conditional move based on a simple mips16 conditional 3575e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek// branch instruction. 358efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// for example: 3595e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek// if $op == beqz or bnez: 3605e03fcb5420c33207433dd6f800588e256dd9bdbTed Kremenek// 3618cc13ea74fea1c04042a2f4087665bc5182e8408Ted Kremenek// $op1 $rt, .+4 3622ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek// move $rd, $rs 3632ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek// 3642ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek// if $op == beqz, then if $rt != 0, then the conditional assignment 3652ded35a576e3899553ea0ccfcbf5cbdb3d8cf664Ted Kremenek// $rd = $rs is done. 366dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek 367dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek// if $op == bnez, then if $rt == 0, then the conditional assignment 368dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek// $rd = $rs is done. 369dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek// 370dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek// So this pseudo class only has one operand, i.e. op 371dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek// 372dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenekclass Sel<string op>: 373efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 374dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek CPU16Regs:$rt), 375dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 376dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek //let isCodeGenOnly=1; 377dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek let Constraints = "$rd = $rd_"; 378dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek let usesCustomInserter = 1; 379dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek} 380dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek 381dbfe41acda3078f8fe566318c0097f7ae683c6bbTed Kremenek// 3821c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// The next two instruction classes allow for an operand which tests 383efd5994d6a35b6b16b29cc59a0d9ef8a14d9c6f8Ted Kremenek// two operands and returns a value in register T8 and 3841c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu//then does a conditional branch based on the value of T8 3851c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// 3861c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu 3871c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// op2 can be cmpi or slti/sltiu 3881c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// op1 can bteqz or btnez 3891c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// the operands for op2 are a register and a signed constant 3901c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// 3911c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// $op2 $t, $imm ;test register t and branch conditionally 3921c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// $op1 .+4 ;op1 is a conditional branch 3931c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// move $rd, $rs 3941c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// 3951c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xu// 3961c0c23325312df5d40fe788ffcb48484f190e9a3Zhongxing Xuclass SeliT<string op1, string op2>: 397bdb435ddaafd5069becd543d638112f68825b89dTed Kremenek MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 39899c6ad3f22b865d0f4cce52bc36904403c9ed4c4Ted Kremenek CPU16Regs:$rl, simm16:$imm), 399b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(op2, 4006a6719a3a11087b48d9f1a4eb08b3bd43cb05a65Ted Kremenek !strconcat("\t$rl, $imm\n\t", 401b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 402b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek let isCodeGenOnly=1; 4036a6719a3a11087b48d9f1a4eb08b3bd43cb05a65Ted Kremenek let Constraints = "$rd = $rd_"; 4046a6719a3a11087b48d9f1a4eb08b3bd43cb05a65Ted Kremenek let usesCustomInserter = 1; 4056a6719a3a11087b48d9f1a4eb08b3bd43cb05a65Ted Kremenek} 4064adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek 4074323a57627e796dcfdfdb7d47672dc09ed308edaTed Kremenek// 4086a6719a3a11087b48d9f1a4eb08b3bd43cb05a65Ted Kremenek// op2 can be cmp or slt/sltu 409b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// op1 can be bteqz or btnez 410b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// the operands for op2 are two registers 411af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek// op1 is a conditional branch 412b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 413b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 414b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// $op2 $rl, $rr ;test registers rl,rr 415b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// $op1 .+4 ;op2 is a conditional branch 416b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// move $rd, $rs 417b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 418b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 41905a2378c708688c8ef498a5cea40ed7f5db15fa5Ted Kremenekclass SelT<string op1, string op2>: 42005a2378c708688c8ef498a5cea40ed7f5db15fa5Ted Kremenek MipsPseudo16<(outs CPU16Regs:$rd_), 42111062b118476368fa5b294954713e5df97d8599fTed Kremenek (ins CPU16Regs:$rd, CPU16Regs:$rs, 42211062b118476368fa5b294954713e5df97d8599fTed Kremenek CPU16Regs:$rl, CPU16Regs:$rr), 42352f379500f4290efaf425a9a5cbc631e2e48a559Ted Kremenek !strconcat(op2, 424729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek !strconcat("\t$rl, $rr\n\t", 425e73dc26690776887bd2991461f6814498600d6ebZhongxing Xu !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 42652f379500f4290efaf425a9a5cbc631e2e48a559Ted Kremenek let isCodeGenOnly=1; 42700a3a5f024ac54088ab887712b292171188064f0Ted Kremenek let Constraints = "$rd = $rd_"; 4284adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek let usesCustomInserter = 1; 4294adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek} 43090e72e4106a0c3efa7575e9f9cba0c775bb54552Zhongxing Xu 43190e72e4106a0c3efa7575e9f9cba0c775bb54552Zhongxing Xu// 43200a3a5f024ac54088ab887712b292171188064f0Ted Kremenek// 32 bit constant 4336297a8ec313c722db50f686fd190842b7ea91118Ted Kremenek// 4346297a8ec313c722db50f686fd190842b7ea91118Ted Kremenekdef imm32: Operand<i32>; 4356297a8ec313c722db50f686fd190842b7ea91118Ted Kremenek 4366297a8ec313c722db50f686fd190842b7ea91118Ted Kremenekdef Constant32: 4376297a8ec313c722db50f686fd190842b7ea91118Ted Kremenek MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 4386297a8ec313c722db50f686fd190842b7ea91118Ted Kremenek 43900a3a5f024ac54088ab887712b292171188064f0Ted Kremenekdef LwConstant32: 44000a3a5f024ac54088ab887712b292171188064f0Ted Kremenek MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm), 44100a3a5f024ac54088ab887712b292171188064f0Ted Kremenek "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 44200a3a5f024ac54088ab887712b292171188064f0Ted Kremenek 44305a2378c708688c8ef498a5cea40ed7f5db15fa5Ted Kremenek 444b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 4454adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek// Some general instruction class info 446846d4e923bf11bcdc2816758aafa331795f29230Ted Kremenek// 447512c913a6f93d225faacdb8e20308f5c4065c3ebTed Kremenek// 448b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 44931593ac2782b2039484210052535f40c243dcf72Ted Kremenekclass ArithLogic16Defs<bit isCom=0> { 45031593ac2782b2039484210052535f40c243dcf72Ted Kremenek bits<5> shamt = 0; 4518cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xu bit isCommutable = isCom; 4528cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xu bit isReMaterializable = 1; 453b48c6455dde10395cd4f3b6b054b2de34a73f7f5Ted Kremenek bit neverHasSideEffects = 1; 454b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek} 4558cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xu 4568cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xuclass branch16 { 457b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek bit isBranch = 1; 458d9bc33efa195114d6f2a365c26e5b8dba4e1cc38Ted Kremenek bit isTerminator = 1; 45931593ac2782b2039484210052535f40c243dcf72Ted Kremenek bit isBarrier = 1; 46005a2378c708688c8ef498a5cea40ed7f5db15fa5Ted Kremenek} 4618cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xu 4628cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xuclass cbranch16 { 4630d093d3005dd583675a45a85bd688063572cc8afTed Kremenek bit isBranch = 1; 464b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek bit isTerminator = 1; 4658cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xu} 4668cd5aaea92f12c25d65ecff5fc820def4c81c1aaZhongxing Xu 4670d093d3005dd583675a45a85bd688063572cc8afTed Kremenekclass MayLoad { 468159d2487e6b49f0aa64c44aef96bc9d643929931Ted Kremenek bit mayLoad = 1; 469af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek} 4701c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu 471b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekclass MayStore { 47205a2378c708688c8ef498a5cea40ed7f5db15fa5Ted Kremenek bit mayStore = 1; 473af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek} 474af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek// 475b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 476b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 477af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek// Format: ADDIU rx, immediate MIPS16e 4781c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 479af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek// To add a constant to a 32-bit integer. 48077349cb20bfd7069d081f84c91975bfa8ef60a32Ted Kremenek// 4811c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xudef AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 4821c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu 483b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 484b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek ArithLogic16Defs<0> { 4851c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu let AddedComplexity = 5; 4861c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu} 487b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 488b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek ArithLogic16Defs<0> { 489b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek let isCodeGenOnly = 1; 490b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek} 4911c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu 4924323a57627e796dcfdfdb7d47672dc09ed308edaTed Kremenekdef AddiuRxRyOffMemX16: 493729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 494b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 495b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 4961c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu 497729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// Format: ADDIU rx, pc, immediate MIPS16e 498729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 499729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// To add a constant to the program counter. 500550a0f94938817e3550d79adcc6f1f27410f7593Ted Kremenek// 50160156f0596a7ab9a39ddec74942b60a3da847174Zhongxing Xudef AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 50260156f0596a7ab9a39ddec74942b60a3da847174Zhongxing Xu 503e8a964bdb46349e4fa3433c8e5104d2a0f7f5c65Zhongxing Xu// 50460156f0596a7ab9a39ddec74942b60a3da847174Zhongxing Xu// Format: ADDIU sp, immediate MIPS16e 50560156f0596a7ab9a39ddec74942b60a3da847174Zhongxing Xu// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 506982e674e39b8022ff7dc020f9ed371f3904549c3Ted Kremenek// To add a constant to the stack pointer. 507982e674e39b8022ff7dc020f9ed371f3904549c3Ted Kremenek// 5085c684c4be01fb98077a9b5e07ca1fdc01d8d97cbTed Kremenekdef AddiuSpImm16 509982e674e39b8022ff7dc020f9ed371f3904549c3Ted Kremenek : FI816_SP_ins<0b011, "addiu", IIAlu> { 5105c684c4be01fb98077a9b5e07ca1fdc01d8d97cbTed Kremenek let Defs = [SP]; 5111b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek let Uses = [SP]; 512b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek let AddedComplexity = 5; 513b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek} 514b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 515b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef AddiuSpImmX16 5166d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 5176d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu let Defs = [SP]; 5186d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu let Uses = [SP]; 5196d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu} 520469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek 521c5b1bf10133a8ecbfe9e6b3ec92bae84e3d927e8Ted Kremenek// 522c5b1bf10133a8ecbfe9e6b3ec92bae84e3d927e8Ted Kremenek// Format: ADDU rz, rx, ry MIPS16e 5236d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu// Purpose: Add Unsigned Word (3-Operand) 524c5b1bf10133a8ecbfe9e6b3ec92bae84e3d927e8Ted Kremenek// To add 32-bit integers. 525ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek// 526ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek 527ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenekdef AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 528ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek 529ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek// 530ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek// Format: AND rx, ry MIPS16e 531ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek// Purpose: AND 532ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek// To do a bitwise logical AND. 533ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek 534ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenekdef AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 535ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek 536ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek 537ef44bfb9d0f15ba0391f8346c9f01355fb450a09Ted Kremenek// 538b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// Format: BEQZ rx, offset MIPS16e 539b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// Purpose: Branch on Equal to Zero 540469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek// To test a GPR then do a PC-relative conditional branch. 541b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 542de43424560f1a744de6214dab6bbee28ad8437f5Ted Kremenekdef BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 543de43424560f1a744de6214dab6bbee28ad8437f5Ted Kremenek 544aa1c4e5a6b87b62d991c55a0d4522bcd778068d7Ted Kremenek 545de43424560f1a744de6214dab6bbee28ad8437f5Ted Kremenek// 5469d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor// Format: BEQZ rx, offset MIPS16e 5479d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor// Purpose: Branch on Equal to Zero (Extended) 5489d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor// To test a GPR then do a PC-relative conditional branch. 5499d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor// 550de43424560f1a744de6214dab6bbee28ad8437f5Ted Kremenekdef BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 551b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 5526d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu// Format: B offset MIPS16e 553e1c2a675e0c089e1f53cbd55d2197a8beaa852aeTed Kremenek// Purpose: Unconditional Branch 554e1c2a675e0c089e1f53cbd55d2197a8beaa852aeTed Kremenek// To do an unconditional PC-relative branch. 555e1c2a675e0c089e1f53cbd55d2197a8beaa852aeTed Kremenek// 556e1c2a675e0c089e1f53cbd55d2197a8beaa852aeTed Kremenekdef BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 557e1c2a675e0c089e1f53cbd55d2197a8beaa852aeTed Kremenek 558b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 5594f09027385466f1f4c382c80ca77157e2aef97d9Ted Kremenek// Format: BNEZ rx, offset MIPS16e 5604f09027385466f1f4c382c80ca77157e2aef97d9Ted Kremenek// Purpose: Branch on Not Equal to Zero 561f22679e3e5d5f5754931952e58112b4c863a4137Zhongxing Xu// To test a GPR then do a PC-relative conditional branch. 5624f09027385466f1f4c382c80ca77157e2aef97d9Ted Kremenek// 563b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 5641b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek 5656d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu// 566b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// Format: BNEZ rx, offset MIPS16e 567b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// Purpose: Branch on Not Equal to Zero (Extended) 568b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// To test a GPR then do a PC-relative conditional branch. 569b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 570b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 571aa1c4e5a6b87b62d991c55a0d4522bcd778068d7Ted Kremenek 572c4f8706b6539e06a5de153bd72850bb2e0a71456Zhongxing Xu// 573c4f8706b6539e06a5de153bd72850bb2e0a71456Zhongxing Xu// Format: BTEQZ offset MIPS16e 574c4f8706b6539e06a5de153bd72850bb2e0a71456Zhongxing Xu// Purpose: Branch on T Equal to Zero (Extended) 575b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// To test special register T then do a PC-relative conditional branch. 576b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 577b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 578469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek let Uses = [T8]; 5796d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu} 580469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek 58197ed4f68f5dba3e21e7a490ef0f9ffd3bfead7f8Ted Kremenekdef BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 58297ed4f68f5dba3e21e7a490ef0f9ffd3bfead7f8Ted Kremenek 58397ed4f68f5dba3e21e7a490ef0f9ffd3bfead7f8Ted Kremenekdef BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 584af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek cbranch16; 585af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek 586af3374187c47acea45706eab6744be6b1c66a856Ted Kremenekdef BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 587af3374187c47acea45706eab6744be6b1c66a856Ted Kremenek 588af3374187c47acea45706eab6744be6b1c66a856Ted Kremenekdef BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 58997ed4f68f5dba3e21e7a490ef0f9ffd3bfead7f8Ted Kremenek 59006fb99fb403bff1651429923f666a2ebe2b1522fTed Kremenekdef BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 59106fb99fb403bff1651429923f666a2ebe2b1522fTed Kremenek 59206fb99fb403bff1651429923f666a2ebe2b1522fTed Kremenekdef BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 593469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek cbranch16; 594469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek 595469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek// 596469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek// Format: BTNEZ offset MIPS16e 597469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek// Purpose: Branch on T Not Equal to Zero (Extended) 598469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek// To test special register T then do a PC-relative conditional branch. 599469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek// 600469ecbded3616416ef938ed94a67f86149faf226Ted Kremenekdef BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 601469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek let Uses = [T8]; 602469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek} 603469ecbded3616416ef938ed94a67f86149faf226Ted Kremenek 60402737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenekdef BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 60502737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenek 60602737ed29d7fff2206f7c7ee958cdf0665e35542Ted Kremenekdef BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 6070518999d3adcc289997bd974dce90cc97f5c1c44Sebastian Redl 6080518999d3adcc289997bd974dce90cc97f5c1c44Sebastian Redldef BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 6090518999d3adcc289997bd974dce90cc97f5c1c44Sebastian Redl 6101b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenekdef BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 611b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek 6121b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenekdef BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 6136d69b5d82281992e981caa9bc038e3f6cac6594aZhongxing Xu 6141b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenekdef BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 615dda0468b5aad99a59bd251a1b15c5cfd0243c041Ted Kremenek cbranch16; 616dda0468b5aad99a59bd251a1b15c5cfd0243c041Ted Kremenek 617d8e9f0dc737133d4e8342f39389064620f5a7f8fTed Kremenek// 61848af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek// Format: CMP rx, ry MIPS16e 61948af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek// Purpose: Compare 62048af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek// To compare the contents of two GPRs. 62148af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenek// 62248af2a9c1ed3259512f2d1431720add1fbe8fb5fTed Kremenekdef CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> { 6231c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu let Defs = [T8]; 6244a4e524afef40d6f3ddb25d0e407c814e4ca56a8Ted Kremenek} 6259ef1ec98a8fc17e7560e07641184bc4daee39b46Ted Kremenek 6269ef1ec98a8fc17e7560e07641184bc4daee39b46Ted Kremenek// 6271c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// Format: CMPI rx, immediate MIPS16e 6281c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// Purpose: Compare Immediate 6299ef1ec98a8fc17e7560e07641184bc4daee39b46Ted Kremenek// To compare a constant with the contents of a GPR. 6301c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// 631b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenekdef CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> { 632b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek let Defs = [T8]; 6331c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu} 6341c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu 635b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// 636b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek// Format: CMPI rx, immediate MIPS16e 6371c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// Purpose: Compare Immediate (Extended) 6381c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// To compare a constant with the contents of a GPR. 63990e420321f60860f4c4e7a68ca9f7567824b46ecTed Kremenek// 6406297a8ec313c722db50f686fd190842b7ea91118Ted Kremenekdef CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> { 6411c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu let Defs = [T8]; 642e04a5cb9afb5faa205c0bfa93103d6df691e05b2Ted Kremenek} 643ad8329e58df5b0b2c44dca1447b324467a6c5da1Ted Kremenek 6446297a8ec313c722db50f686fd190842b7ea91118Ted Kremenek 64510c16657eec144def180ee53d1e0249c9ed2b3b5Ted Kremenek// 6461c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// Format: DIV rx, ry MIPS16e 647e04a5cb9afb5faa205c0bfa93103d6df691e05b2Ted Kremenek// Purpose: Divide Word 6481c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// To divide 32-bit signed integers. 649b640b3b5dfccaf259967cb2cb6755c9aa20d4423Ted Kremenek// 65050d0ac299c641bee9024f3fbae2ea0640898a040Ted Kremenekdef DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 6514adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek let Defs = [HI, LO]; 6521c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu} 6534adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek 6544d9985ab390079ccc8b05b6c349026f237567b8fTed Kremenek// 6554adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek// Format: DIVU rx, ry MIPS16e 6561c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// Purpose: Divide Unsigned Word 657c3055ab39ac3535ffd581d33e21b72133099a6ebTed Kremenek// To divide 32-bit unsigned integers. 6581e2b1fc4c4ae775adb2b236a8190f5a93b09ea12Ted Kremenek// 659df7533b5e523a3def04b5c33b56361a94dd97d35Ted Kremenekdef DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 6601c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu let Defs = [HI, LO]; 6611b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek} 662729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// 663e695e1cd7d8a579455e8969be36cbaf10a316a64Ted Kremenek// Format: JAL target MIPS16e 664e695e1cd7d8a579455e8969be36cbaf10a316a64Ted Kremenek// Purpose: Jump and Link 6651b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek// To execute a procedure call within the current 256 MB-aligned 666e695e1cd7d8a579455e8969be36cbaf10a316a64Ted Kremenek// region and preserve the current ISA. 667729a9a276f39e75038ed100fc76055fb709b17f4Ted Kremenek// 668de43424560f1a744de6214dab6bbee28ad8437f5Ted Kremenek 66905a2378c708688c8ef498a5cea40ed7f5db15fa5Ted Kremenekdef Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 670a8538d902fce9cfec20f39b34492268b51643819Ted Kremenek let isBranch = 1; 671a8538d902fce9cfec20f39b34492268b51643819Ted Kremenek let hasDelaySlot = 0; // not true, but we add the nop for now 672a8538d902fce9cfec20f39b34492268b51643819Ted Kremenek let isTerminator=1; 673a8538d902fce9cfec20f39b34492268b51643819Ted Kremenek let isBarrier=1; 674a8538d902fce9cfec20f39b34492268b51643819Ted Kremenek} 6754adc81e540b874bafa15715fd2c5cb662463debdTed Kremenek 6761c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// 677ec96a2d52d16e150baaf629cd35e3fabff5d8915Ted Kremenek// Format: JR ra MIPS16e 67882bae3f6bf7bc4733d9c87659b266e23ad55f420Ted Kremenek// Purpose: Jump Register Through Register ra 6791c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu// To execute a branch to the instruction address in the return 68082bae3f6bf7bc4733d9c87659b266e23ad55f420Ted Kremenek// address register. 6811b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek// 6821b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek 6831b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenekdef JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 6841b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek let isBranch = 1; 68597c4d4759da403bccaaccdadb513164c84c85befZhongxing Xu let isIndirectBranch = 1; 6861b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek let hasDelaySlot = 1; 6878c354758c2d39db87c77c723d81e34b4d967f762Ted Kremenek let isTerminator=1; 6888c354758c2d39db87c77c723d81e34b4d967f762Ted Kremenek let isBarrier=1; 6891b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek} 6901b8bd4d71c2098126041b4de4267175a82f0103cTed Kremenek 691e38718e3251d9f2489f38a5467fdab06f53e8e77Ted Kremenekdef JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 6921c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu let isBranch = 1; 6931c96b24285d05c0eac455ae96d7c9ff43d42bc96Zhongxing Xu let isIndirectBranch = 1; 694b387a3f23e423d62c053be86294b703da1d1a222Ted Kremenek let isTerminator=1; 695c0c3f5dbc9e78aa53a86c7d5e3eeda23ddad93d6Ted Kremenek let isBarrier=1; 696c0c3f5dbc9e78aa53a86c7d5e3eeda23ddad93d6Ted Kremenek} 697c0c3f5dbc9e78aa53a86c7d5e3eeda23ddad93d6Ted Kremenek 698d065d6080f0620bb80b933f3f5d52d37bb2ea770Ted Kremenekdef JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 699 let isBranch = 1; 700 let isIndirectBranch = 1; 701 let isTerminator=1; 702 let isBarrier=1; 703} 704// 705// Format: LB ry, offset(rx) MIPS16e 706// Purpose: Load Byte (Extended) 707// To load a byte from memory as a signed value. 708// 709def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 710 let isCodeGenOnly = 1; 711} 712 713// 714// Format: LBU ry, offset(rx) MIPS16e 715// Purpose: Load Byte Unsigned (Extended) 716// To load a byte from memory as a unsigned value. 717// 718def LbuRxRyOffMemX16: 719 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 720 let isCodeGenOnly = 1; 721} 722 723// 724// Format: LH ry, offset(rx) MIPS16e 725// Purpose: Load Halfword signed (Extended) 726// To load a halfword from memory as a signed value. 727// 728def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 729 let isCodeGenOnly = 1; 730} 731 732// 733// Format: LHU ry, offset(rx) MIPS16e 734// Purpose: Load Halfword unsigned (Extended) 735// To load a halfword from memory as an unsigned value. 736// 737def LhuRxRyOffMemX16: 738 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 739 let isCodeGenOnly = 1; 740} 741 742// 743// Format: LI rx, immediate MIPS16e 744// Purpose: Load Immediate 745// To load a constant into a GPR. 746// 747def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 748 749// 750// Format: LI rx, immediate MIPS16e 751// Purpose: Load Immediate (Extended) 752// To load a constant into a GPR. 753// 754def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 755 756// 757// Format: LW ry, offset(rx) MIPS16e 758// Purpose: Load Word (Extended) 759// To load a word from memory as a signed value. 760// 761def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 762 let isCodeGenOnly = 1; 763} 764 765// Format: LW rx, offset(sp) MIPS16e 766// Purpose: Load Word (SP-Relative, Extended) 767// To load an SP-relative word from memory as a signed value. 768// 769def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{ 770 let Uses = [SP]; 771} 772 773// 774// Format: MOVE r32, rz MIPS16e 775// Purpose: Move 776// To move the contents of a GPR to a GPR. 777// 778def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 779 780// 781// Format: MOVE ry, r32 MIPS16e 782//Purpose: Move 783// To move the contents of a GPR to a GPR. 784// 785def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 786 787// 788// Format: MFHI rx MIPS16e 789// Purpose: Move From HI Register 790// To copy the special purpose HI register to a GPR. 791// 792def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 793 let Uses = [HI]; 794 let neverHasSideEffects = 1; 795} 796 797// 798// Format: MFLO rx MIPS16e 799// Purpose: Move From LO Register 800// To copy the special purpose LO register to a GPR. 801// 802def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 803 let Uses = [LO]; 804 let neverHasSideEffects = 1; 805} 806 807// 808// Pseudo Instruction for mult 809// 810def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 811 let isCommutable = 1; 812 let neverHasSideEffects = 1; 813 let Defs = [HI, LO]; 814} 815 816def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 817 let isCommutable = 1; 818 let neverHasSideEffects = 1; 819 let Defs = [HI, LO]; 820} 821 822// 823// Format: MULT rx, ry MIPS16e 824// Purpose: Multiply Word 825// To multiply 32-bit signed integers. 826// 827def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 828 let isCommutable = 1; 829 let neverHasSideEffects = 1; 830 let Defs = [HI, LO]; 831} 832 833// 834// Format: MULTU rx, ry MIPS16e 835// Purpose: Multiply Unsigned Word 836// To multiply 32-bit unsigned integers. 837// 838def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 839 let isCommutable = 1; 840 let neverHasSideEffects = 1; 841 let Defs = [HI, LO]; 842} 843 844// 845// Format: NEG rx, ry MIPS16e 846// Purpose: Negate 847// To negate an integer value. 848// 849def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 850 851// 852// Format: NOT rx, ry MIPS16e 853// Purpose: Not 854// To complement an integer value 855// 856def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 857 858// 859// Format: OR rx, ry MIPS16e 860// Purpose: Or 861// To do a bitwise logical OR. 862// 863def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 864 865// 866// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 867// (All args are optional) MIPS16e 868// Purpose: Restore Registers and Deallocate Stack Frame 869// To deallocate a stack frame before exit from a subroutine, 870// restoring return address and static registers, and adjusting 871// stack 872// 873 874// fixed form for restoring RA and the frame 875// for direct object emitter, encoding needs to be adjusted for the 876// frame size 877// 878let ra=1, s=0,s0=1,s1=1 in 879def RestoreRaF16: 880 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 881 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad { 882 let isCodeGenOnly = 1; 883 let Defs = [S0, S1, RA, SP]; 884 let Uses = [SP]; 885} 886 887// Use Restore to increment SP since SP is not a Mip 16 register, this 888// is an easy way to do that which does not require a register. 889// 890let ra=0, s=0,s0=0,s1=0 in 891def RestoreIncSpF16: 892 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 893 "restore\t$frame_size", [], IILoad >, MayLoad { 894 let isCodeGenOnly = 1; 895 let Defs = [SP]; 896 let Uses = [SP]; 897} 898 899// 900// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 901// MIPS16e 902// Purpose: Save Registers and Set Up Stack Frame 903// To set up a stack frame on entry to a subroutine, 904// saving return address and static registers, and adjusting stack 905// 906let ra=1, s=1,s0=1,s1=1 in 907def SaveRaF16: 908 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 909 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore { 910 let isCodeGenOnly = 1; 911 let Uses = [RA, SP, S0, S1]; 912 let Defs = [SP]; 913} 914 915// 916// Use Save to decrement the SP by a constant since SP is not 917// a Mips16 register. 918// 919let ra=0, s=0,s0=0,s1=0 in 920def SaveDecSpF16: 921 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 922 "save\t$frame_size", [], IIStore >, MayStore { 923 let isCodeGenOnly = 1; 924 let Uses = [SP]; 925 let Defs = [SP]; 926} 927// 928// Format: SB ry, offset(rx) MIPS16e 929// Purpose: Store Byte (Extended) 930// To store a byte to memory. 931// 932def SbRxRyOffMemX16: 933 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 934 935// 936// The Sel(T) instructions are pseudos 937// T means that they use T8 implicitly. 938// 939// 940// Format: SelBeqZ rd, rs, rt 941// Purpose: if rt==0, do nothing 942// else rs = rt 943// 944def SelBeqZ: Sel<"beqz">; 945 946// 947// Format: SelTBteqZCmp rd, rs, rl, rr 948// Purpose: b = Cmp rl, rr. 949// If b==0 then do nothing. 950// if b!=0 then rd = rs 951// 952def SelTBteqZCmp: SelT<"bteqz", "cmp">; 953 954// 955// Format: SelTBteqZCmpi rd, rs, rl, rr 956// Purpose: b = Cmpi rl, imm. 957// If b==0 then do nothing. 958// if b!=0 then rd = rs 959// 960def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 961 962// 963// Format: SelTBteqZSlt rd, rs, rl, rr 964// Purpose: b = Slt rl, rr. 965// If b==0 then do nothing. 966// if b!=0 then rd = rs 967// 968def SelTBteqZSlt: SelT<"bteqz", "slt">; 969 970// 971// Format: SelTBteqZSlti rd, rs, rl, rr 972// Purpose: b = Slti rl, imm. 973// If b==0 then do nothing. 974// if b!=0 then rd = rs 975// 976def SelTBteqZSlti: SeliT<"bteqz", "slti">; 977 978// 979// Format: SelTBteqZSltu rd, rs, rl, rr 980// Purpose: b = Sltu rl, rr. 981// If b==0 then do nothing. 982// if b!=0 then rd = rs 983// 984def SelTBteqZSltu: SelT<"bteqz", "sltu">; 985 986// 987// Format: SelTBteqZSltiu rd, rs, rl, rr 988// Purpose: b = Sltiu rl, imm. 989// If b==0 then do nothing. 990// if b!=0 then rd = rs 991// 992def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 993 994// 995// Format: SelBnez rd, rs, rt 996// Purpose: if rt!=0, do nothing 997// else rs = rt 998// 999def SelBneZ: Sel<"bnez">; 1000 1001// 1002// Format: SelTBtneZCmp rd, rs, rl, rr 1003// Purpose: b = Cmp rl, rr. 1004// If b!=0 then do nothing. 1005// if b0=0 then rd = rs 1006// 1007def SelTBtneZCmp: SelT<"btnez", "cmp">; 1008 1009// 1010// Format: SelTBtnezCmpi rd, rs, rl, rr 1011// Purpose: b = Cmpi rl, imm. 1012// If b!=0 then do nothing. 1013// if b==0 then rd = rs 1014// 1015def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1016 1017// 1018// Format: SelTBtneZSlt rd, rs, rl, rr 1019// Purpose: b = Slt rl, rr. 1020// If b!=0 then do nothing. 1021// if b==0 then rd = rs 1022// 1023def SelTBtneZSlt: SelT<"btnez", "slt">; 1024 1025// 1026// Format: SelTBtneZSlti rd, rs, rl, rr 1027// Purpose: b = Slti rl, imm. 1028// If b!=0 then do nothing. 1029// if b==0 then rd = rs 1030// 1031def SelTBtneZSlti: SeliT<"btnez", "slti">; 1032 1033// 1034// Format: SelTBtneZSltu rd, rs, rl, rr 1035// Purpose: b = Sltu rl, rr. 1036// If b!=0 then do nothing. 1037// if b==0 then rd = rs 1038// 1039def SelTBtneZSltu: SelT<"btnez", "sltu">; 1040 1041// 1042// Format: SelTBtneZSltiu rd, rs, rl, rr 1043// Purpose: b = Slti rl, imm. 1044// If b!=0 then do nothing. 1045// if b==0 then rd = rs 1046// 1047def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1048// 1049// 1050// Format: SH ry, offset(rx) MIPS16e 1051// Purpose: Store Halfword (Extended) 1052// To store a halfword to memory. 1053// 1054def ShRxRyOffMemX16: 1055 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1056 1057// 1058// Format: SLL rx, ry, sa MIPS16e 1059// Purpose: Shift Word Left Logical (Extended) 1060// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits. 1061// 1062def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1063 1064// 1065// Format: SLLV ry, rx MIPS16e 1066// Purpose: Shift Word Left Logical Variable 1067// To execute a left-shift of a word by a variable number of bits. 1068// 1069def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1070 1071// Format: SLTI rx, immediate MIPS16e 1072// Purpose: Set on Less Than Immediate 1073// To record the result of a less-than comparison with a constant. 1074// 1075// 1076def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1077 let Defs = [T8]; 1078} 1079 1080// 1081// Format: SLTI rx, immediate MIPS16e 1082// Purpose: Set on Less Than Immediate (Extended) 1083// To record the result of a less-than comparison with a constant. 1084// 1085// 1086def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1087 let Defs = [T8]; 1088} 1089 1090def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1091 1092// Format: SLTIU rx, immediate MIPS16e 1093// Purpose: Set on Less Than Immediate Unsigned 1094// To record the result of a less-than comparison with a constant. 1095// 1096// 1097def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1098 let Defs = [T8]; 1099} 1100 1101// 1102// Format: SLTI rx, immediate MIPS16e 1103// Purpose: Set on Less Than Immediate Unsigned (Extended) 1104// To record the result of a less-than comparison with a constant. 1105// 1106// 1107def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1108 let Defs = [T8]; 1109} 1110// 1111// Format: SLTIU rx, immediate MIPS16e 1112// Purpose: Set on Less Than Immediate Unsigned (Extended) 1113// To record the result of a less-than comparison with a constant. 1114// 1115def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1116 1117// 1118// Format: SLT rx, ry MIPS16e 1119// Purpose: Set on Less Than 1120// To record the result of a less-than comparison. 1121// 1122def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{ 1123 let Defs = [T8]; 1124} 1125 1126def SltCCRxRy16: FCCRR16_ins<"slt">; 1127 1128// Format: SLTU rx, ry MIPS16e 1129// Purpose: Set on Less Than Unsigned 1130// To record the result of an unsigned less-than comparison. 1131// 1132def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{ 1133 let Defs = [T8]; 1134} 1135 1136def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1137 let isCodeGenOnly=1; 1138 let Defs = [T8]; 1139} 1140 1141 1142def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1143// 1144// Format: SRAV ry, rx MIPS16e 1145// Purpose: Shift Word Right Arithmetic Variable 1146// To execute an arithmetic right-shift of a word by a variable 1147// number of bits. 1148// 1149def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1150 1151 1152// 1153// Format: SRA rx, ry, sa MIPS16e 1154// Purpose: Shift Word Right Arithmetic (Extended) 1155// To execute an arithmetic right-shift of a word by a fixed 1156// number of bits—1 to 8 bits. 1157// 1158def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1159 1160 1161// 1162// Format: SRLV ry, rx MIPS16e 1163// Purpose: Shift Word Right Logical Variable 1164// To execute a logical right-shift of a word by a variable 1165// number of bits. 1166// 1167def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1168 1169 1170// 1171// Format: SRL rx, ry, sa MIPS16e 1172// Purpose: Shift Word Right Logical (Extended) 1173// To execute a logical right-shift of a word by a fixed 1174// number of bits—1 to 31 bits. 1175// 1176def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1177 1178// 1179// Format: SUBU rz, rx, ry MIPS16e 1180// Purpose: Subtract Unsigned Word 1181// To subtract 32-bit integers 1182// 1183def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1184 1185// 1186// Format: SW ry, offset(rx) MIPS16e 1187// Purpose: Store Word (Extended) 1188// To store a word to memory. 1189// 1190def SwRxRyOffMemX16: 1191 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1192 1193// 1194// Format: SW rx, offset(sp) MIPS16e 1195// Purpose: Store Word rx (SP-Relative) 1196// To store an SP-relative word to memory. 1197// 1198def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore; 1199 1200// 1201// 1202// Format: XOR rx, ry MIPS16e 1203// Purpose: Xor 1204// To do a bitwise logical XOR. 1205// 1206def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1207 1208class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1209 let Predicates = [InMips16Mode]; 1210} 1211 1212// Unary Arith/Logic 1213// 1214class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1215 Mips16Pat<(OpNode CPU16Regs:$r), 1216 (I CPU16Regs:$r)>; 1217 1218def: ArithLogicU_pat<not, NotRxRy16>; 1219def: ArithLogicU_pat<ineg, NegRxRy16>; 1220 1221class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1222 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1223 (I CPU16Regs:$l, CPU16Regs:$r)>; 1224 1225def: ArithLogic16_pat<add, AdduRxRyRz16>; 1226def: ArithLogic16_pat<and, AndRxRxRy16>; 1227def: ArithLogic16_pat<mul, MultRxRyRz16>; 1228def: ArithLogic16_pat<or, OrRxRxRy16>; 1229def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1230def: ArithLogic16_pat<xor, XorRxRxRy16>; 1231 1232// Arithmetic and logical instructions with 2 register operands. 1233 1234class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1235 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1236 (I CPU16Regs:$in, imm_type:$imm)>; 1237 1238def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1239def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1240def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1241def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1242def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1243 1244class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1245 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1246 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1247 1248def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1249def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1250def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1251 1252class LoadM16_pat<PatFrag OpNode, Instruction I> : 1253 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1254 1255def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1256def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1257def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1258def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1259def: LoadM16_pat<load, LwRxRyOffMemX16>; 1260 1261class StoreM16_pat<PatFrag OpNode, Instruction I> : 1262 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1263 (I CPU16Regs:$r, addr16:$addr)>; 1264 1265def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1266def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1267def: StoreM16_pat<store, SwRxRyOffMemX16>; 1268 1269// Unconditional branch 1270class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1271 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1272 let Predicates = [InMips16Mode]; 1273 } 1274 1275def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1276 (Jal16 tglobaladdr:$dst)>; 1277 1278def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1279 (Jal16 texternalsym:$dst)>; 1280 1281// Indirect branch 1282def: Mips16Pat< 1283 (brind CPU16Regs:$rs), 1284 (JrcRx16 CPU16Regs:$rs)>; 1285 1286// Jump and Link (Call) 1287let isCall=1, hasDelaySlot=0 in 1288def JumpLinkReg16: 1289 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1290 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1291 1292// Mips16 pseudos 1293let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1294 hasExtraSrcRegAllocReq = 1 in 1295def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1296 1297 1298// setcc patterns 1299 1300class SetCC_R16<PatFrag cond_op, Instruction I>: 1301 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1302 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1303 1304class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1305 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1306 (I CPU16Regs:$rx, imm_type:$imm16)>; 1307 1308 1309def: Mips16Pat<(i32 addr16:$addr), 1310 (AddiuRxRyOffMemX16 addr16:$addr)>; 1311 1312 1313// Large (>16 bit) immediate loads 1314def : Mips16Pat<(i32 imm:$imm), 1315 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16), 1316 (LiRxImmX16 (LO16 imm:$imm)))>; 1317 1318// Carry MipsPatterns 1319def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1320 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1321def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1322 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1323def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1324 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1325 1326// 1327// Some branch conditional patterns are not generated by llvm at this time. 1328// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1329// comparison they are used and for unsigned a different pattern is used. 1330// I am pushing upstream from the full mips16 port and it seemed that I needed 1331// these earlier and the mips32 port has these but now I cannot create test 1332// cases that use these patterns. While I sort this all out I will leave these 1333// extra patterns commented out and if I can be sure they are really not used, 1334// I will delete the code. I don't want to check the code in uncommented without 1335// a valid test case. In some cases, the compiler is generating patterns with 1336// setcc instead and earlier I had implemented setcc first so may have masked 1337// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1338// figure out how to enable the brcond patterns or else possibly new 1339// combinations of of brcond and setcc. 1340// 1341// 1342// bcond-seteq 1343// 1344def: Mips16Pat 1345 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1346 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1347 >; 1348 1349 1350def: Mips16Pat 1351 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1352 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1353 >; 1354 1355def: Mips16Pat 1356 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1357 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16) 1358 >; 1359 1360// 1361// bcond-setgt (do we need to have this pair of setlt, setgt??) 1362// 1363def: Mips16Pat 1364 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1365 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1366 >; 1367 1368// 1369// bcond-setge 1370// 1371def: Mips16Pat 1372 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1373 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1374 >; 1375 1376// 1377// never called because compiler transforms a >= k to a > (k-1) 1378def: Mips16Pat 1379 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1380 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1381 >; 1382 1383// 1384// bcond-setlt 1385// 1386def: Mips16Pat 1387 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1388 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1389 >; 1390 1391def: Mips16Pat 1392 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1393 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1394 >; 1395 1396// 1397// bcond-setle 1398// 1399def: Mips16Pat 1400 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1401 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1402 >; 1403 1404// 1405// bcond-setne 1406// 1407def: Mips16Pat 1408 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1409 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1410 >; 1411 1412def: Mips16Pat 1413 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1414 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1415 >; 1416 1417def: Mips16Pat 1418 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1419 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1420 >; 1421 1422// 1423// This needs to be there but I forget which code will generate it 1424// 1425def: Mips16Pat 1426 <(brcond CPU16Regs:$rx, bb:$targ16), 1427 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16) 1428 >; 1429 1430// 1431 1432// 1433// bcond-setugt 1434// 1435//def: Mips16Pat 1436// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1437// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1438// >; 1439 1440// 1441// bcond-setuge 1442// 1443//def: Mips16Pat 1444// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1445// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1446// >; 1447 1448 1449// 1450// bcond-setult 1451// 1452//def: Mips16Pat 1453// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1454// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1455// >; 1456 1457def: UncondBranch16_pat<br, BimmX16>; 1458 1459// Small immediates 1460def: Mips16Pat<(i32 immSExt16:$in), 1461 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1462 1463def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1464 1465// 1466// MipsDivRem 1467// 1468def: Mips16Pat 1469 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), 1470 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1471 1472// 1473// MipsDivRemU 1474// 1475def: Mips16Pat 1476 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry), 1477 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1478 1479// signed a,b 1480// x = (a>=b)?x:y 1481// 1482// if !(a < b) x = y 1483// 1484def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1485 CPU16Regs:$x, CPU16Regs:$y), 1486 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1487 CPU16Regs:$a, CPU16Regs:$b)>; 1488 1489// signed a,b 1490// x = (a>b)?x:y 1491// 1492// if (b < a) x = y 1493// 1494def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1495 CPU16Regs:$x, CPU16Regs:$y), 1496 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1497 CPU16Regs:$b, CPU16Regs:$a)>; 1498 1499// unsigned a,b 1500// x = (a>=b)?x:y 1501// 1502// if !(a < b) x = y; 1503// 1504def : Mips16Pat< 1505 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1506 CPU16Regs:$x, CPU16Regs:$y), 1507 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1508 CPU16Regs:$a, CPU16Regs:$b)>; 1509 1510// unsigned a,b 1511// x = (a>b)?x:y 1512// 1513// if (b < a) x = y 1514// 1515def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1516 CPU16Regs:$x, CPU16Regs:$y), 1517 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1518 CPU16Regs:$b, CPU16Regs:$a)>; 1519 1520// signed 1521// x = (a >= k)?x:y 1522// due to an llvm optimization, i don't think that this will ever 1523// be used. This is transformed into x = (a > k-1)?x:y 1524// 1525// 1526 1527//def : Mips16Pat< 1528// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1529// CPU16Regs:$T, CPU16Regs:$F), 1530// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1531// CPU16Regs:$lhs, immSExt16:$rhs)>; 1532 1533//def : Mips16Pat< 1534// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1535// CPU16Regs:$T, CPU16Regs:$F), 1536// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1537// CPU16Regs:$lhs, immSExt16:$rhs)>; 1538 1539// signed 1540// x = (a < k)?x:y 1541// 1542// if !(a < k) x = y; 1543// 1544def : Mips16Pat< 1545 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1546 CPU16Regs:$x, CPU16Regs:$y), 1547 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1548 CPU16Regs:$a, immSExt16:$b)>; 1549 1550 1551// 1552// 1553// signed 1554// x = (a <= b)? x : y 1555// 1556// if (b < a) x = y 1557// 1558def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1559 CPU16Regs:$x, CPU16Regs:$y), 1560 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1561 CPU16Regs:$b, CPU16Regs:$a)>; 1562 1563// 1564// unnsigned 1565// x = (a <= b)? x : y 1566// 1567// if (b < a) x = y 1568// 1569def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1570 CPU16Regs:$x, CPU16Regs:$y), 1571 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1572 CPU16Regs:$b, CPU16Regs:$a)>; 1573 1574// 1575// signed/unsigned 1576// x = (a == b)? x : y 1577// 1578// if (a != b) x = y 1579// 1580def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1581 CPU16Regs:$x, CPU16Regs:$y), 1582 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1583 CPU16Regs:$b, CPU16Regs:$a)>; 1584 1585// 1586// signed/unsigned 1587// x = (a == 0)? x : y 1588// 1589// if (a != 0) x = y 1590// 1591def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1592 CPU16Regs:$x, CPU16Regs:$y), 1593 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1594 CPU16Regs:$a)>; 1595 1596 1597// 1598// signed/unsigned 1599// x = (a == k)? x : y 1600// 1601// if (a != k) x = y 1602// 1603def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1604 CPU16Regs:$x, CPU16Regs:$y), 1605 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1606 CPU16Regs:$a, immZExt16:$k)>; 1607 1608 1609// 1610// signed/unsigned 1611// x = (a != b)? x : y 1612// 1613// if (a == b) x = y 1614// 1615// 1616def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1617 CPU16Regs:$x, CPU16Regs:$y), 1618 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1619 CPU16Regs:$b, CPU16Regs:$a)>; 1620 1621// 1622// signed/unsigned 1623// x = (a != 0)? x : y 1624// 1625// if (a == 0) x = y 1626// 1627def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1628 CPU16Regs:$x, CPU16Regs:$y), 1629 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1630 CPU16Regs:$a)>; 1631 1632// signed/unsigned 1633// x = (a)? x : y 1634// 1635// if (!a) x = y 1636// 1637def : Mips16Pat<(select CPU16Regs:$a, 1638 CPU16Regs:$x, CPU16Regs:$y), 1639 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1640 CPU16Regs:$a)>; 1641 1642 1643// 1644// signed/unsigned 1645// x = (a != k)? x : y 1646// 1647// if (a == k) x = y 1648// 1649def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1650 CPU16Regs:$x, CPU16Regs:$y), 1651 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1652 CPU16Regs:$a, immZExt16:$k)>; 1653 1654// 1655// When writing C code to test setxx these patterns, 1656// some will be transformed into 1657// other things. So we test using C code but using -O3 and -O0 1658// 1659// seteq 1660// 1661def : Mips16Pat 1662 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1663 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1664 1665def : Mips16Pat 1666 <(seteq CPU16Regs:$lhs, 0), 1667 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1668 1669 1670// 1671// setge 1672// 1673 1674def: Mips16Pat 1675 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1676 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1677 (LiRxImmX16 1))>; 1678 1679// 1680// For constants, llvm transforms this to: 1681// x > (k -1) and then reverses the operands to use setlt. So this pattern 1682// is not used now by the compiler. (Presumably checking that k-1 does not 1683// overflow). The compiler never uses this at a the current time, due to 1684// other optimizations. 1685// 1686//def: Mips16Pat 1687// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1688// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1689// (LiRxImmX16 1))>; 1690 1691// This catches the x >= -32768 case by transforming it to x > -32769 1692// 1693def: Mips16Pat 1694 <(setgt CPU16Regs:$lhs, -32769), 1695 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1696 (LiRxImmX16 1))>; 1697 1698// 1699// setgt 1700// 1701// 1702 1703def: Mips16Pat 1704 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1705 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1706 1707// 1708// setle 1709// 1710def: Mips16Pat 1711 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1712 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1713 1714// 1715// setlt 1716// 1717def: SetCC_R16<setlt, SltCCRxRy16>; 1718 1719def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1720 1721// 1722// setne 1723// 1724def : Mips16Pat 1725 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1726 (SltuCCRxRy16 (LiRxImmX16 0), 1727 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1728 1729 1730// 1731// setuge 1732// 1733def: Mips16Pat 1734 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1735 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1736 (LiRxImmX16 1))>; 1737 1738// this pattern will never be used because the compiler will transform 1739// x >= k to x > (k - 1) and then use SLT 1740// 1741//def: Mips16Pat 1742// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1743// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1744// (LiRxImmX16 1))>; 1745 1746// 1747// setugt 1748// 1749def: Mips16Pat 1750 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1751 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1752 1753// 1754// setule 1755// 1756def: Mips16Pat 1757 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1758 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1759 1760// 1761// setult 1762// 1763def: SetCC_R16<setult, SltuCCRxRy16>; 1764 1765def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1766 1767def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1768 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1769 1770// hi/lo relocs 1771 1772def : Mips16Pat<(MipsHi tglobaladdr:$in), 1773 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1774def : Mips16Pat<(MipsHi tjumptable:$in), 1775 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1776def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1777 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1778 1779// wrapper_pic 1780class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1781 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1782 (ADDiuOp RC:$gp, node:$in)>; 1783 1784 1785def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1786def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1787 1788def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1789 (LbuRxRyOffMemX16 addr16:$src)>; 1790def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1791 (LhuRxRyOffMemX16 addr16:$src)>; 1792