Mips32r6InstrInfo.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips32r6 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14include "Mips32r6InstrFormats.td" 15 16// Notes about removals/changes from MIPS32r6: 17// Unclear: ssnop 18// Reencoded: cache, pref 19// Reencoded: clo, clz 20// Reencoded: jr -> jalr 21// Reencoded: jr.hb -> jalr.hb 22// Reencoded: ldc2 23// Reencoded: ll, sc 24// Reencoded: lwc2 25// Reencoded: sdbbp 26// Reencoded: sdc2 27// Reencoded: swc2 28// Removed: bc1any2, bc1any4 29// Removed: bc2[ft] 30// Removed: bc2f, bc2t 31// Removed: bgezal 32// Removed: bltzal 33// Removed: c.cond.fmt, bc1[ft] 34// Removed: div, divu 35// Removed: jalx 36// Removed: ldxc1 37// Removed: luxc1 38// Removed: lwxc1 39// Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds] 40// Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul 41// Removed: movf, movt 42// Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt 43// Removed: movn, movz 44// Removed: mult, multu 45// Removed: prefx 46// Removed: sdxc1 47// Removed: suxc1 48// Removed: swxc1 49// Rencoded: [ls][wd]c2 50 51def brtarget21 : Operand<OtherVT> { 52 let EncoderMethod = "getBranchTarget21OpValue"; 53 let OperandType = "OPERAND_PCREL"; 54 let DecoderMethod = "DecodeBranchTarget21"; 55 let ParserMatchClass = MipsJumpTargetAsmOperand; 56} 57 58def brtarget26 : Operand<OtherVT> { 59 let EncoderMethod = "getBranchTarget26OpValue"; 60 let OperandType = "OPERAND_PCREL"; 61 let DecoderMethod = "DecodeBranchTarget26"; 62 let ParserMatchClass = MipsJumpTargetAsmOperand; 63} 64 65def jmpoffset16 : Operand<OtherVT> { 66 let EncoderMethod = "getJumpOffset16OpValue"; 67 let ParserMatchClass = MipsJumpTargetAsmOperand; 68} 69 70def calloffset16 : Operand<iPTR> { 71 let EncoderMethod = "getJumpOffset16OpValue"; 72 let ParserMatchClass = MipsJumpTargetAsmOperand; 73} 74 75//===----------------------------------------------------------------------===// 76// 77// Instruction Encodings 78// 79//===----------------------------------------------------------------------===// 80 81class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>; 82class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>; 83class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>; 84class AUI_ENC : AUI_FM; 85class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>; 86 87class BALC_ENC : BRANCH_OFF26_FM<0b111010>; 88class BC_ENC : BRANCH_OFF26_FM<0b110010>; 89class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 90 DecodeDisambiguates<"AddiGroupBranch">; 91class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>, 92 DecodeDisambiguatedBy<"DaddiGroupBranch">; 93class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 94 DecodeDisambiguates<"DaddiGroupBranch">; 95class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>, 96 DecodeDisambiguatedBy<"DaddiGroupBranch">; 97 98class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>, 99 DecodeDisambiguates<"BgtzlGroupBranch">; 100class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>, 101 DecodeDisambiguates<"BlezlGroupBranch">; 102class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>, 103 DecodeDisambiguatedBy<"BgtzGroupBranch">; 104 105class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>, 106 DecodeDisambiguatedBy<"BlezlGroupBranch">; 107class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>, 108 DecodeDisambiguates<"BgtzGroupBranch">; 109class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>, 110 DecodeDisambiguatedBy<"BgtzlGroupBranch">; 111 112class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>; 113class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>; 114class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>; 115 116class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>; 117class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>; 118class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>; 119class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>; 120 121class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>; 122class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>; 123 124class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>; 125class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>; 126class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>, 127 DecodeDisambiguatedBy<"DaddiGroupBranch">; 128class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>, 129 DecodeDisambiguatedBy<"AddiGroupBranch">; 130class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; 131class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; 132class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; 133class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>; 134class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; 135class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; 136class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; 137class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; 138 139class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>; 140class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>; 141class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>; 142class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>; 143 144class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; 145class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; 146 147class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>; 148class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>; 149 150class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>; 151class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>; 152 153class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; 154class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; 155class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; 156class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>; 157 158class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>; 159class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>; 160class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>; 161class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>; 162 163class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>; 164class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; 165class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>; 166class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; 167 168class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; 169class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; 170class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; 171class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; 172 173class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> { 174 dag OutOperandList = (outs FGROpnd:$fd); 175 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 176 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); 177 list<dag> Pattern = []; 178} 179 180//===----------------------------------------------------------------------===// 181// 182// Instruction Multiclasses 183// 184//===----------------------------------------------------------------------===// 185 186multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, 187 RegisterOperand FGROpnd>{ 188 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>, 189 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>, 190 ISA_MIPS32R6; 191 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, 192 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, 193 ISA_MIPS32R6; 194 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>, 195 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, 196 ISA_MIPS32R6; 197 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>, 198 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, 199 ISA_MIPS32R6; 200 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>, 201 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>, 202 ISA_MIPS32R6; 203 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>, 204 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, 205 ISA_MIPS32R6; 206 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>, 207 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>, 208 ISA_MIPS32R6; 209 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>, 210 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, 211 ISA_MIPS32R6; 212 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>, 213 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>, 214 ISA_MIPS32R6; 215 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>, 216 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>, 217 ISA_MIPS32R6; 218 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>, 219 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, 220 ISA_MIPS32R6; 221 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>, 222 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>, 223 ISA_MIPS32R6; 224 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>, 225 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, 226 ISA_MIPS32R6; 227 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>, 228 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>, 229 ISA_MIPS32R6; 230 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>, 231 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, 232 ISA_MIPS32R6; 233 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>, 234 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>, 235 ISA_MIPS32R6; 236} 237 238//===----------------------------------------------------------------------===// 239// 240// Instruction Descriptions 241// 242//===----------------------------------------------------------------------===// 243 244class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 245 dag OutOperandList = (outs GPROpnd:$rs); 246 dag InOperandList = (ins simm19_lsl2:$imm); 247 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 248 list<dag> Pattern = []; 249} 250 251class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>; 252class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>; 253class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>; 254 255class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 256 Operand ImmOpnd> { 257 dag OutOperandList = (outs GPROpnd:$rd); 258 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); 259 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); 260 list<dag> Pattern = []; 261} 262 263class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>; 264 265class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 266 dag OutOperandList = (outs GPROpnd:$rs); 267 dag InOperandList = (ins simm16:$imm); 268 string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); 269 list<dag> Pattern = []; 270} 271 272class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>; 273class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>; 274 275class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 276 dag OutOperandList = (outs GPROpnd:$rs); 277 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); 278 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); 279 list<dag> Pattern = []; 280} 281 282class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>; 283 284class BRANCH_DESC_BASE { 285 bit isBranch = 1; 286 bit isTerminator = 1; 287 bit hasDelaySlot = 0; 288} 289 290class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE { 291 dag InOperandList = (ins opnd:$offset); 292 dag OutOperandList = (outs); 293 string AsmString = !strconcat(instr_asm, "\t$offset"); 294 bit isBarrier = 1; 295} 296 297class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd, 298 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 299 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); 300 dag OutOperandList = (outs); 301 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); 302 list<Register> Defs = [AT]; 303} 304 305class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 306 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 307 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset); 308 dag OutOperandList = (outs); 309 string AsmString = !strconcat(instr_asm, "\t$rs, $offset"); 310 list<Register> Defs = [AT]; 311} 312 313class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd, 314 RegisterOperand GPROpnd> : BRANCH_DESC_BASE { 315 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 316 dag OutOperandList = (outs); 317 string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); 318 list<Register> Defs = [AT]; 319} 320 321class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> { 322 bit isCall = 1; 323 list<Register> Defs = [RA]; 324} 325 326class BC_DESC : BC_DESC_BASE<"bc", brtarget26>; 327class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>; 328class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>; 329 330class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>; 331class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>; 332 333class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>; 334class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>; 335 336class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>; 337class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>; 338 339class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 340 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset); 341 dag OutOperandList = (outs); 342 string AsmString = instr_asm; 343 bit hasDelaySlot = 1; 344} 345 346class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">; 347class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">; 348 349class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { 350 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset); 351 dag OutOperandList = (outs); 352 string AsmString = instr_asm; 353 bit hasDelaySlot = 1; 354} 355 356class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">; 357class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">; 358 359class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>; 360class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>; 361 362class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, 363 RegisterOperand GPROpnd> { 364 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); 365 string AsmString = !strconcat(opstr, "\t$rt, $offset"); 366 list<dag> Pattern = []; 367 bit isTerminator = 1; 368 bit hasDelaySlot = 0; 369 string DecoderMethod = "DecodeSimm16"; 370} 371 372class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, 373 GPR32Opnd> { 374 bit isCall = 1; 375 list<Register> Defs = [RA]; 376} 377 378class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> { 379 bit isBarrier = 1; 380 list<Register> Defs = [AT]; 381} 382 383class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 384 dag OutOperandList = (outs GPROpnd:$rd); 385 dag InOperandList = (ins GPROpnd:$rt); 386 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 387 list<dag> Pattern = []; 388} 389 390class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>; 391 392class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 393 dag OutOperandList = (outs GPROpnd:$rd); 394 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 395 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 396 list<dag> Pattern = []; 397} 398 399class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>; 400class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>; 401class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>; 402class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>; 403 404class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> { 405 list<Register> Defs = [RA]; 406} 407 408class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> { 409 list<Register> Defs = [RA]; 410} 411 412class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> { 413 list<Register> Defs = [RA]; 414} 415 416class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> { 417 list<Register> Defs = [RA]; 418} 419 420class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> { 421 list<Register> Defs = [RA]; 422} 423 424class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> { 425 list<Register> Defs = [RA]; 426} 427class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 428 dag OutOperandList = (outs GPROpnd:$rd); 429 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 430 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 431 list<dag> Pattern = []; 432} 433 434class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>; 435class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>; 436class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>; 437class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>; 438 439class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 440 dag OutOperandList = (outs FGROpnd:$fd); 441 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); 442 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 443 list<dag> Pattern = []; 444 string Constraints = "$fd_in = $fd"; 445} 446 447class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>; 448class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>; 449 450class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { 451 dag OutOperandList = (outs GPROpnd:$rd); 452 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); 453 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 454 list<dag> Pattern = []; 455} 456 457class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>; 458class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>; 459 460class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>; 461class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>; 462class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>; 463class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>; 464 465class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 466 dag OutOperandList = (outs FGROpnd:$fd); 467 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 468 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 469 list<dag> Pattern = []; 470} 471 472class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>; 473class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>; 474class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>; 475class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>; 476 477class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>; 478class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>; 479class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>; 480class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>; 481 482class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 483 dag OutOperandList = (outs FGROpnd:$fd); 484 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); 485 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); 486 list<dag> Pattern = []; 487} 488 489class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; 490class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; 491class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; 492class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; 493 494class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { 495 dag OutOperandList = (outs FGROpnd:$fd); 496 dag InOperandList = (ins FGROpnd:$fs); 497 string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); 498 list<dag> Pattern = []; 499} 500 501class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; 502class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; 503class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; 504class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; 505 506//===----------------------------------------------------------------------===// 507// 508// Instruction Definitions 509// 510//===----------------------------------------------------------------------===// 511 512def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; 513def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; 514def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; 515def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6; 516def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; 517def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6; 518def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6; 519def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6; 520def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; 521def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; 522def BC : BC_ENC, BC_DESC, ISA_MIPS32R6; 523def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; 524def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; 525def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; 526def BGEC; // Also aliased to blec with operands swapped 527def BGEUC; // Also aliased to bleuc with operands swapped 528def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; 529def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; 530def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; 531def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; 532def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; 533def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; 534def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; 535def BLTC; // Also aliased to bgtc with operands swapped 536def BLTUC; // Also aliased to bgtuc with operands swapped 537def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; 538def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; 539def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; 540def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; 541def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; 542def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; 543def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; 544def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; 545def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; 546defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; 547defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; 548def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; 549def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; 550def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; 551def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6; 552// def LSA; // See MSA 553def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; 554def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; 555def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6; 556def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6; 557def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6; 558def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6; 559def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6; 560def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6; 561def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6; 562def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6; 563def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6; 564def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6; 565def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6; 566def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6; 567def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6; 568def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6; 569def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6; 570def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; 571def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; 572def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; 573def NAL; // BAL with rd=0 574def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; 575def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; 576def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6; 577def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6; 578def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6; 579def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6; 580def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6; 581def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6; 582def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6; 583def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6; 584