Mips64InstrInfo.td revision 1d4d32398ddb19520b2a84acae3b7807ad74602b
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37let DecoderNamespace = "Mips64" in { 38 39multiclass Atomic2Ops64<PatFrag Op> { 40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, 41 Requires<[NotN64, HasStdEnc]>; 42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 43 Requires<[IsN64, HasStdEnc]> { 44 let isCodeGenOnly = 1; 45 } 46} 47 48multiclass AtomicCmpSwap64<PatFrag Op> { 49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 50 Requires<[NotN64, HasStdEnc]>; 51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 52 Requires<[IsN64, HasStdEnc]> { 53 let isCodeGenOnly = 1; 54 } 55} 56} 57let usesCustomInserter = 1, Predicates = [HasStdEnc], 58 DecoderNamespace = "Mips64" in { 59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 67} 68 69/// Pseudo instructions for loading and storing accumulator registers. 70let isPseudo = 1 in { 71 defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>; 72 defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>; 73} 74 75//===----------------------------------------------------------------------===// 76// Instruction definition 77//===----------------------------------------------------------------------===// 78let DecoderNamespace = "Mips64" in { 79/// Arithmetic Instructions (ALU Immediate) 80def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; 81def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>, 82 ADDI_FM<0x19>, IsAsCheapAsAMove; 83def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>, 84 ADDI_FM<0xc>; 85def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 86 SLTI_FM<0xa>; 87def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 88 SLTI_FM<0xb>; 89def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>, 90 ADDI_FM<0xd>; 91def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>, 92 ADDI_FM<0xe>; 93def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 94 95/// Arithmetic Instructions (3-Operand, R-Type) 96def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; 97def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>, 98 ADD_FM<0, 0x2d>; 99def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>, 100 ADD_FM<0, 0x2f>; 101def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 102def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 103def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 104def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 105def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 106def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>; 107 108/// Shift Instructions 109def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>, 110 SRA_FM<0x38, 0>; 111def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>, 112 SRA_FM<0x3a, 0>; 113def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>, 114 SRA_FM<0x3b, 0>; 115def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>; 116def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>; 117def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>; 118def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>; 119def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>; 120def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>; 121} 122// Rotate Instructions 123let Predicates = [HasMips64r2, HasStdEnc], 124 DecoderNamespace = "Mips64" in { 125 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>, 126 SRA_FM<0x3a, 1>; 127 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, 128 SRLV_FM<0x16, 1>; 129} 130 131let DecoderNamespace = "Mips64" in { 132/// Load and Store Instructions 133/// aligned 134defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>; 135defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>; 136defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>; 137defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>; 138defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>; 139defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>; 140defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>; 141defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>; 142defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>; 143defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>; 144defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>; 145 146/// load/store left/right 147defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 148defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 149defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 150defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 151 152defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 153defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 154defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 155defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 156 157/// Load-linked, Store-conditional 158let Predicates = [NotN64, HasStdEnc] in { 159 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>; 160 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>; 161} 162 163let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 164 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>; 165 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>; 166} 167 168/// Jump and Branch Instructions 169def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 170def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>; 171def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>; 172def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>; 173def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>; 174def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>; 175def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>; 176} 177let DecoderNamespace = "Mips64" in 178def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 179def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>; 180def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 181 182let DecoderNamespace = "Mips64" in { 183/// Multiply and Divide Instructions. 184def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 185 MULT_FM<0, 0x1c>; 186def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 187 MULT_FM<0, 0x1d>; 188def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult, 189 IIImul>; 190def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu, 191 IIImul>; 192def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>; 193def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>; 194def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem, 195 IIIdiv, 0, 1, 1>; 196def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU, 197 IIIdiv, 0, 1, 1>; 198 199def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 200def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 201def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 202def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 203 204/// Sign Ext In Register Instructions. 205def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 206def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 207 208/// Count Leading 209def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>; 210def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>; 211 212/// Double Word Swap Bytes/HalfWords 213def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>; 214def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>; 215 216def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 217 218} 219let DecoderNamespace = "Mips64" in { 220def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM; 221 222def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>; 223let Pattern = []<dag> in { 224 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>; 225 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>; 226} 227def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>; 228let Pattern = []<dag> in { 229 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>; 230 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>; 231} 232 233let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 234 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 235 "dsll\t$rd, $rt, 32", [], IIAlu>; 236 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 237 "sll\t$rd, $rt, 0", [], IIAlu>; 238 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 239 "sll\t$rd, $rt, 0", [], IIAlu>; 240} 241} 242//===----------------------------------------------------------------------===// 243// Arbitrary patterns that map to one or more instructions 244//===----------------------------------------------------------------------===// 245 246// extended loads 247let Predicates = [NotN64, HasStdEnc] in { 248 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 249 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 250 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 251 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 252} 253let Predicates = [IsN64, HasStdEnc] in { 254 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 255 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 256 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 257 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 258} 259 260// hi/lo relocs 261def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 262def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 263def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 264def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 265def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 266def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 267 268def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 269def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 270def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 271def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 272def : MipsPat<(MipsLo tglobaltlsaddr:$in), 273 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 274def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 275 276def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 277 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 278def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 279 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 280def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 281 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 282def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 283 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 284def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 285 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 286 287def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 288def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 289def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 290def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 291def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 292def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 293 294defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 295 ZERO_64>; 296 297def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 298 (BLEZ64 i64:$lhs, bb:$dst)>; 299def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 300 (BGEZ64 i64:$lhs, bb:$dst)>; 301 302// setcc patterns 303defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 304defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 305defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 306defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 307defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 308 309// truncate 310def : MipsPat<(i32 (trunc CPU64Regs:$src)), 311 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 312 Requires<[IsN64, HasStdEnc]>; 313 314// 32-to-64-bit extension 315def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 316def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 317def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 318 319// Sign extend in register 320def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 321 (SLL64_64 CPU64Regs:$src)>; 322 323// bswap MipsPattern 324def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 325 326// mflo/hi patterns. 327def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)), 328 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>; 329 330//===----------------------------------------------------------------------===// 331// Instruction aliases 332//===----------------------------------------------------------------------===// 333def : InstAlias<"move $dst, $src", 334 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 335 Requires<[HasMips64]>; 336def : InstAlias<"move $dst, $src", 337 (OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 338 Requires<[HasMips64]>; 339def : InstAlias<"and $rs, $rt, $imm", 340 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 341 1>, 342 Requires<[HasMips64]>; 343def : InstAlias<"slt $rs, $rt, $imm", 344 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>, 345 Requires<[HasMips64]>; 346def : InstAlias<"xor $rs, $rt, $imm", 347 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 348 1>, 349 Requires<[HasMips64]>; 350def : InstAlias<"not $rt, $rs", 351 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, 352 Requires<[HasMips64]>; 353def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; 354def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>, 355 Requires<[HasMips64]>; 356def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>, 357 Requires<[HasMips64]>; 358def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>, 359 Requires<[HasMips64]>; 360def : InstAlias<"daddu $rs, $rt, $imm", 361 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 362 1>; 363def : InstAlias<"dadd $rs, $rt, $imm", 364 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 365 1>; 366def : InstAlias<"or $rs, $rt, $imm", 367 (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 368 1>, Requires<[HasMips64]>; 369def : InstAlias<"bnez $rs,$offset", 370 (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>, 371 Requires<[HasMips64]>; 372def : InstAlias<"beqz $rs,$offset", 373 (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>, 374 Requires<[HasMips64]>; 375 376/// Move between CPU and coprocessor registers 377let DecoderNamespace = "Mips64" in { 378def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 379 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 380 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>; 381def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 382 (ins CPU64RegsOpnd:$rt), 383 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>; 384def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 385 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 386 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>; 387def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 388 (ins CPU64RegsOpnd:$rt), 389 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>; 390} 391 392// Two operand (implicit 0 selector) versions: 393def : InstAlias<"dmfc0 $rt, $rd", 394 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 395def : InstAlias<"dmtc0 $rt, $rd", 396 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 397def : InstAlias<"dmfc2 $rt, $rd", 398 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 399def : InstAlias<"dmtc2 $rt, $rd", 400 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 401 402