Mips64InstrInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Unsigned Operand 19def uimm16_64 : Operand<i64> { 20 let PrintMethod = "printUnsignedImm"; 21} 22 23// Transformation Function - get Imm - 32. 24def Subtract32 : SDNodeXForm<imm, [{ 25 return getImm(N, (unsigned)N->getZExtValue() - 32); 26}]>; 27 28// shamt must fit in 6 bits. 29def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 30 31//===----------------------------------------------------------------------===// 32// Instructions specific format 33//===----------------------------------------------------------------------===// 34let usesCustomInserter = 1 in { 35 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 36 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 37 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 38 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 39 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 40 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 41 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 42 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 43} 44 45/// Pseudo instructions for loading and storing accumulator registers. 46let isPseudo = 1, isCodeGenOnly = 1 in { 47 def LOAD_ACC128 : Load<"", ACC128>; 48 def STORE_ACC128 : Store<"", ACC128>; 49} 50 51//===----------------------------------------------------------------------===// 52// Instruction definition 53//===----------------------------------------------------------------------===// 54let DecoderNamespace = "Mips64" in { 55/// Arithmetic Instructions (ALU Immediate) 56def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>; 57def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, 58 immSExt16, add>, 59 ADDI_FM<0x19>, IsAsCheapAsAMove; 60 61let isCodeGenOnly = 1 in { 62def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 63 SLTI_FM<0xa>; 64def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 65 SLTI_FM<0xb>; 66def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 67 ADDI_FM<0xc>; 68def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 69 ADDI_FM<0xd>; 70def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 71 ADDI_FM<0xe>; 72def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM; 73} 74 75/// Arithmetic Instructions (3-Operand, R-Type) 76def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>; 77def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, 78 ADD_FM<0, 0x2d>; 79def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, 80 ADD_FM<0, 0x2f>; 81def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>; 82 83let isCodeGenOnly = 1 in { 84def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 85def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 86def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; 87def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; 88def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; 89def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 90} 91 92/// Shift Instructions 93def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>, 94 SRA_FM<0x38, 0>; 95def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>, 96 SRA_FM<0x3a, 0>; 97def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>, 98 SRA_FM<0x3b, 0>; 99def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 100 SRLV_FM<0x14, 0>; 101def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 102 SRLV_FM<0x16, 0>; 103def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 104 SRLV_FM<0x17, 0>; 105def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, 106 SRA_FM<0x3c, 0>; 107def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, 108 SRA_FM<0x3e, 0>; 109def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, 110 SRA_FM<0x3f, 0>; 111 112// Rotate Instructions 113let Predicates = [HasMips64r2, HasStdEnc] in { 114 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, 115 immZExt6>, SRA_FM<0x3a, 1>; 116 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, 117 SRLV_FM<0x16, 1>; 118 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, 119 SRA_FM<0x3e, 1>; 120} 121 122/// Load and Store Instructions 123/// aligned 124let isCodeGenOnly = 1 in { 125def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>; 126def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>; 127def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>; 128def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>; 129def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>; 130def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>; 131def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>; 132def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; 133} 134 135def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>; 136def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>; 137def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>; 138 139/// load/store left/right 140let isCodeGenOnly = 1 in { 141def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>; 142def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>; 143def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>; 144def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>; 145} 146 147def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>; 148def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>; 149def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>; 150def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>; 151 152/// Load-linked, Store-conditional 153def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>; 154def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>; 155 156/// Jump and Branch Instructions 157let isCodeGenOnly = 1 in { 158def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; 159def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 160def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 161def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 162def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 163def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 164def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 165def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 166def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 167def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; 168} 169 170/// Multiply and Divide Instructions. 171def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 172 MULT_FM<0, 0x1c>; 173def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 174 MULT_FM<0, 0x1d>; 175def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 176 II_DMULT>; 177def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 178 II_DMULTU>; 179def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 180 MULT_FM<0, 0x1e>; 181def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 182 MULT_FM<0, 0x1f>; 183def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 184 II_DDIV, 0, 1, 1>; 185def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 186 II_DDIVU, 0, 1, 1>; 187 188let isCodeGenOnly = 1 in { 189def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>; 190def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>; 191def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>; 192def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>; 193def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>; 194def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>; 195def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>; 196 197/// Sign Ext In Register Instructions. 198def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>; 199def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>; 200} 201 202/// Count Leading 203def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>; 204def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>; 205 206/// Double Word Swap Bytes/HalfWords 207def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>; 208def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; 209 210def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 211 212let isCodeGenOnly = 1 in 213def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 214 215def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; 216def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>; 217def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>; 218 219def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; 220def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>; 221def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>; 222 223let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 224 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 225 "dsll\t$rd, $rt, 32", [], II_DSLL>; 226 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 227 "sll\t$rd, $rt, 0", [], II_SLL>; 228 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 229 "sll\t$rd, $rt, 0", [], II_SLL>; 230} 231 232// Cavium Octeon cmMIPS instructions 233let Predicates = [HasCnMips] in { 234 235class Count1s<string opstr, RegisterOperand RO>: 236 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 237 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 238 let TwoOperandAliasConstraint = "$rd = $rs"; 239} 240 241class ExtsCins<string opstr, SDPatternOperator Op = null_frag>: 242 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 243 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), 244 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], 245 NoItinerary, FrmR, opstr> { 246 let TwoOperandAliasConstraint = "$rt = $rs"; 247} 248 249class SetCC64_R<string opstr, PatFrag cond_op> : 250 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 251 !strconcat(opstr, "\t$rd, $rs, $rt"), 252 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))], 253 II_SEQ_SNE, FrmR, opstr> { 254 let TwoOperandAliasConstraint = "$rd = $rs"; 255} 256 257// Unsigned Byte Add 258let Pattern = [(set GPR64Opnd:$rd, 259 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in 260def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 261 ADD_FM<0x1c, 0x28>; 262 263// Multiply Doubleword to GPR 264let Defs = [HI0, LO0, P0, P1, P2] in 265def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 266 ADD_FM<0x1c, 0x03>; 267 268// Extract a signed bit field /+32 269def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>; 270def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>; 271 272// Clear and insert a bit field /+32 273def CINS : ExtsCins<"cins">, EXTS_FM<0x32>; 274def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>; 275 276// Move to multiplier/product register 277def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>; 278def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>; 279def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>; 280def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>; 281def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>; 282def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>; 283 284// Count Ones in a Word/Doubleword 285def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>; 286def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>; 287 288// Set on equal/not equal 289def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>; 290def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>; 291} 292 293} 294 295//===----------------------------------------------------------------------===// 296// Arbitrary patterns that map to one or more instructions 297//===----------------------------------------------------------------------===// 298 299// extended loads 300let Predicates = [HasStdEnc] in { 301 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 302 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 303 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 304 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 305} 306 307// hi/lo relocs 308def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 309def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 310def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 311def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 312def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 313def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 314 315def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 316def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 317def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 318def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 319def : MipsPat<(MipsLo tglobaltlsaddr:$in), 320 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 321def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 322 323def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 324 (DADDiu GPR64:$hi, tglobaladdr:$lo)>; 325def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 326 (DADDiu GPR64:$hi, tblockaddress:$lo)>; 327def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 328 (DADDiu GPR64:$hi, tjumptable:$lo)>; 329def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 330 (DADDiu GPR64:$hi, tconstpool:$lo)>; 331def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 332 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>; 333 334def : WrapperPat<tglobaladdr, DADDiu, GPR64>; 335def : WrapperPat<tconstpool, DADDiu, GPR64>; 336def : WrapperPat<texternalsym, DADDiu, GPR64>; 337def : WrapperPat<tblockaddress, DADDiu, GPR64>; 338def : WrapperPat<tjumptable, DADDiu, GPR64>; 339def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; 340 341defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 342 ZERO_64>; 343 344def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 345 (BLEZ64 i64:$lhs, bb:$dst)>; 346def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 347 (BGEZ64 i64:$lhs, bb:$dst)>; 348 349// setcc patterns 350defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; 351defm : SetlePats<GPR64, SLT64, SLTu64>; 352defm : SetgtPats<GPR64, SLT64, SLTu64>; 353defm : SetgePats<GPR64, SLT64, SLTu64>; 354defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; 355 356// truncate 357def : MipsPat<(i32 (trunc GPR64:$src)), 358 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, 359 Requires<[HasStdEnc]>; 360 361// 32-to-64-bit extension 362def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; 363def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 364def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 365 366// Sign extend in register 367def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 368 (SLL64_64 GPR64:$src)>; 369 370// bswap MipsPattern 371def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 372 373//===----------------------------------------------------------------------===// 374// Instruction aliases 375//===----------------------------------------------------------------------===// 376def : InstAlias<"move $dst, $src", 377 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 378 Requires<[HasMips64]>; 379def : InstAlias<"daddu $rs, $rt, $imm", 380 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 381 0>; 382def : InstAlias<"dadd $rs, $rt, $imm", 383 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 384 0>; 385def : InstAlias<"daddu $rs, $imm", 386 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 387 0>; 388def : InstAlias<"dadd $rs, $imm", 389 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 390 0>; 391def : InstAlias<"add $rs, $imm", 392 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 393 0>; 394def : InstAlias<"addu $rs, $imm", 395 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 396 0>; 397let isPseudo=1, usesCustomInserter=1, isCodeGenOnly=1 in { 398def SUBi : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm), 399 "sub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>; 400def SUBiu : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm), 401 "subu\t$rt, $rs, $imm", [], II_DSUB, Pseudo>; 402def DSUBi : MipsInst<(outs GPR64Opnd: $rt), (ins GPR64Opnd: $rs, simm16_64: $imm), 403 "ssub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>; 404def DSUBiu : MipsInst<(outs GPR64Opnd: $rt), (ins GPR64Opnd: $rs, simm16_64: $imm), 405 "ssubu\t$rt, $rs, $imm", [], II_DSUB, Pseudo>; 406} 407def : InstAlias<"dsubu $rt, $rs, $imm", 408 (DSUBiu GPR64Opnd:$rt, GPR64Opnd:$rs, simm16_64: $imm), 409 0>; 410def : InstAlias<"sub $rs, $imm", 411 (SUBi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 412 0>; 413def : InstAlias<"subu $rs, $imm", 414 (SUBiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 415 0>; 416def : InstAlias<"dsub $rs, $imm", 417 (DSUBi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 418 0>; 419def : InstAlias<"dsubu $rs, $imm", 420 (DSUBiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 421 0>; 422 423/// Move between CPU and coprocessor registers 424let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 425def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>; 426def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>; 427def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>; 428def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>; 429} 430 431// Two operand (implicit 0 selector) versions: 432def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 433def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 434def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 435def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 436 437