Mips64InstrInfo.td revision 6a8309e62afd88fbea4f1c39121de6dc4dc0d899
1013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// 3013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// The LLVM Compiler Infrastructure 4013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// 5013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// This file is distributed under the University of Illinois Open Source 6013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// License. See LICENSE.TXT for details. 7013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// 8013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===----------------------------------------------------------------------===// 9013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// 10013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// This file describes Mips64 instructions. 11013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// 128b0e8ac5f582de80356019406e2975079bf0829dcommit-bot@chromium.org//===----------------------------------------------------------------------===// 13013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 14013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===----------------------------------------------------------------------===// 15013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Mips Operand, Complex Patterns and Transformations Definitions. 16013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===----------------------------------------------------------------------===// 17013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 1807adb6359fd137ccb633b2c64ee2287c8edfd701commit-bot@chromium.org// Instruction operand types 19186c0ccac25229534ec6fb84726043083304d4d1commit-bot@chromium.orgdef shamt_64 : Operand<i64>; 2007adb6359fd137ccb633b2c64ee2287c8edfd701commit-bot@chromium.org 21013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Unsigned Operand 22013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comdef uimm16_64 : Operand<i64> { 2307adb6359fd137ccb633b2c64ee2287c8edfd701commit-bot@chromium.org let PrintMethod = "printUnsignedImm"; 24013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com} 25013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 26013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Transformation Function - get Imm - 32. 27013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comdef Subtract32 : SDNodeXForm<imm, [{ 28013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com return getImm(N, (unsigned)N->getZExtValue() - 32); 29013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com}]>; 30013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 31013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// shamt must fit in 6 bits. 32013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comdef immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33e4fafb146e85cdfcf9d5418597b6818aa0754adatfarina@chromium.org 34013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===----------------------------------------------------------------------===// 35013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Instructions specific format 36fa9e5fa42a555712fb7a29d08d2ae2bdef0ed68ecommit-bot@chromium.org//===----------------------------------------------------------------------===// 37013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Shifts 38013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// 64-bit shift instructions. 39013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comlet DecoderNamespace = "Mips64" in { 40013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comclass shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>: 41013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>; 42013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 43013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Mul, Div 44013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comclass Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 45013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 46013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comclass Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 47013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 48013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 49013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.commulticlass Atomic2Ops64<PatFrag Op> { 50013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>, 51013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com Requires<[NotN64, HasStdEnc]>; 52013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 53013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com Requires<[IsN64, HasStdEnc]> { 54013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com let isCodeGenOnly = 1; 55013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com } 56013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com} 57013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 58013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.commulticlass AtomicCmpSwap64<PatFrag Op> { 59013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 60013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com Requires<[NotN64, HasStdEnc]>; 61013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 62013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com Requires<[IsN64, HasStdEnc]> { 63013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com let isCodeGenOnly = 1; 64013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com } 65013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com} 66013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com} 67013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comlet usesCustomInserter = 1, Predicates = [HasStdEnc], 68013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com DecoderNamespace = "Mips64" in { 69013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 70013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 71013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 72013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 73013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 74013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 75013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 76013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 77013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com} 78013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com 79013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===----------------------------------------------------------------------===// 80013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com// Instruction definition 81013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com//===----------------------------------------------------------------------===// 82013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comlet DecoderNamespace = "Mips64" in { 83013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.com/// Arithmetic Instructions (ALU Immediate) 84013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comdef DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>; 85013c5d9107a4abd50e879ca66cf60b0c3a8256d4scroggo@google.comdef DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>, 86 ADDI_FM<0x19>, IsAsCheapAsAMove; 87def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>, 88 ADDI_FM<0xc>; 89def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 90 SLTI_FM<0xa>; 91def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 92 SLTI_FM<0xb>; 93def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, 94 ADDI_FM<0xd>; 95def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, 96 ADDI_FM<0xe>; 97def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 98 99/// Arithmetic Instructions (3-Operand, R-Type) 100def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; 101def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>; 102def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>; 103def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 104def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 105def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 106def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 107def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 108def NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>; 109 110/// Shift Instructions 111def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>; 112def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>; 113def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>; 114def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>; 115def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>; 116def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>; 117def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>; 118def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>; 119def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>; 120} 121// Rotate Instructions 122let Predicates = [HasMips64r2, HasStdEnc], 123 DecoderNamespace = "Mips64" in { 124 def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>; 125 def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>; 126} 127 128let DecoderNamespace = "Mips64" in { 129/// Load and Store Instructions 130/// aligned 131defm LB64 : LoadM<"lb", sextloadi8, CPU64Regs>, LW_FM<0x20>; 132defm LBu64 : LoadM<"lbu", zextloadi8, CPU64Regs>, LW_FM<0x24>; 133defm LH64 : LoadM<"lh", sextloadi16, CPU64Regs>, LW_FM<0x21>; 134defm LHu64 : LoadM<"lhu", zextloadi16, CPU64Regs>, LW_FM<0x25>; 135defm LW64 : LoadM<"lw", sextloadi32, CPU64Regs>, LW_FM<0x23>; 136defm LWu64 : LoadM<"lwu", zextloadi32, CPU64Regs>, LW_FM<0x27>; 137defm SB64 : StoreM<"sb", truncstorei8, CPU64Regs>, LW_FM<0x28>; 138defm SH64 : StoreM<"sh", truncstorei16, CPU64Regs>, LW_FM<0x29>; 139defm SW64 : StoreM<"sw", truncstorei32, CPU64Regs>, LW_FM<0x2b>; 140defm LD : LoadM<"ld", load, CPU64Regs>, LW_FM<0x37>; 141defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>; 142 143/// load/store left/right 144let isCodeGenOnly = 1 in { 145 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 146 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 147 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 148 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 149} 150defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 151defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 152defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 153defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 154 155/// Load-linked, Store-conditional 156let Predicates = [NotN64, HasStdEnc] in { 157 def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>; 158 def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>; 159} 160 161let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 162 def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>; 163 def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>; 164} 165 166/// Jump and Branch Instructions 167def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 168def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 169def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 170def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; 171def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; 172def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; 173def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; 174} 175let DecoderNamespace = "Mips64" in 176def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 177def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 178 179let DecoderNamespace = "Mips64" in { 180/// Multiply and Divide Instructions. 181def DMULT : Mult64<0x1c, "dmult", IIImul>; 182def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 183def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 184def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 185 186def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 187def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 188def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 189def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 190 191/// Sign Ext In Register Instructions. 192def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10>; 193def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>; 194 195/// Count Leading 196def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>; 197def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>; 198 199/// Double Word Swap Bytes/HalfWords 200def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; 201def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; 202 203def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 204} 205let DecoderNamespace = "Mips64" in { 206def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 207 208def DEXT : ExtBase<3, "dext", CPU64Regs>; 209let Pattern = []<dag> in { 210 def DEXTU : ExtBase<2, "dextu", CPU64Regs>; 211 def DEXTM : ExtBase<1, "dextm", CPU64Regs>; 212} 213def DINS : InsBase<7, "dins", CPU64Regs>; 214let Pattern = []<dag> in { 215 def DINSU : InsBase<6, "dinsu", CPU64Regs>; 216 def DINSM : InsBase<5, "dinsm", CPU64Regs>; 217} 218 219let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 220 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 221 "dsll\t$rd, $rt, 32", [], IIAlu>; 222 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 223 "sll\t$rd, $rt, 0", [], IIAlu>; 224 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 225 "sll\t$rd, $rt, 0", [], IIAlu>; 226} 227} 228//===----------------------------------------------------------------------===// 229// Arbitrary patterns that map to one or more instructions 230//===----------------------------------------------------------------------===// 231 232// extended loads 233let Predicates = [NotN64, HasStdEnc] in { 234 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 235 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 236 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 237 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 238} 239let Predicates = [IsN64, HasStdEnc] in { 240 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 241 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 242 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 243 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 244} 245 246// hi/lo relocs 247def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 248def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 249def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 250def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 251def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 252def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 253 254def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 255def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 256def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 257def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 258def : MipsPat<(MipsLo tglobaltlsaddr:$in), 259 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 260def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 261 262def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 263 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 264def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 265 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 266def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 267 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 268def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 269 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 270def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 271 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 272 273def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 274def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 275def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 276def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 277def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 278def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 279 280defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 281 ZERO_64>; 282 283// setcc patterns 284defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 285defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 286defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 287defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 288defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 289 290// truncate 291def : MipsPat<(i32 (trunc CPU64Regs:$src)), 292 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 293 Requires<[IsN64, HasStdEnc]>; 294 295// 32-to-64-bit extension 296def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 297def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 298def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 299 300// Sign extend in register 301def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 302 (SLL64_64 CPU64Regs:$src)>; 303 304// bswap MipsPattern 305def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 306 307//===----------------------------------------------------------------------===// 308// Instruction aliases 309//===----------------------------------------------------------------------===// 310def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 311 312/// Move between CPU and coprocessor registers 313let DecoderNamespace = "Mips64" in { 314def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), 315 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 316def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), 317 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; 318def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), 319 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 320def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), 321 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; 322def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), 323 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; 324def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), 325 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; 326def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), 327 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; 328def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), 329 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; 330} 331// Two operand (implicit 0 selector) versions: 332def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 333def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 334def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 335def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 336def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 337def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 338def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 339def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 340 341