Mips64InstrInfo.td revision 782638aa0d18f7db7970eb0d8dded84fe7f0c450 
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Mips Operand, Complex Patterns and Transformations Definitions.
16//===----------------------------------------------------------------------===//
17
18// Instruction operand types
19def shamt_64       : Operand<i64>;
20
21// Unsigned Operand
22def uimm16_64      : Operand<i64> {
23  let PrintMethod = "printUnsignedImm";
24}
25
26// Transformation Function - get Imm - 32.
27def Subtract32 : SDNodeXForm<imm, [{
28  return getImm(N, (unsigned)N->getZExtValue() - 32);
29}]>;
30
31// shamt must fit in 6 bits.
32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
33
34//===----------------------------------------------------------------------===//
35// Instructions specific format
36//===----------------------------------------------------------------------===//
37let DecoderNamespace = "Mips64" in {
38
39multiclass Atomic2Ops64<PatFrag Op> {
40  def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
41             Requires<[NotN64, HasStdEnc]>;
42  def _P8  : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
43             Requires<[IsN64, HasStdEnc]> {
44    let isCodeGenOnly = 1;
45  }
46}
47
48multiclass AtomicCmpSwap64<PatFrag Op>  {
49  def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
50             Requires<[NotN64, HasStdEnc]>;
51  def _P8  : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
52             Requires<[IsN64, HasStdEnc]> {
53    let isCodeGenOnly = 1;
54  }
55}
56}
57let usesCustomInserter = 1, Predicates = [HasStdEnc],
58  DecoderNamespace = "Mips64" in {
59  defm ATOMIC_LOAD_ADD_I64  : Atomic2Ops64<atomic_load_add_64>;
60  defm ATOMIC_LOAD_SUB_I64  : Atomic2Ops64<atomic_load_sub_64>;
61  defm ATOMIC_LOAD_AND_I64  : Atomic2Ops64<atomic_load_and_64>;
62  defm ATOMIC_LOAD_OR_I64   : Atomic2Ops64<atomic_load_or_64>;
63  defm ATOMIC_LOAD_XOR_I64  : Atomic2Ops64<atomic_load_xor_64>;
64  defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
65  defm ATOMIC_SWAP_I64      : Atomic2Ops64<atomic_swap_64>;
66  defm ATOMIC_CMP_SWAP_I64  : AtomicCmpSwap64<atomic_cmp_swap_64>;
67}
68
69/// Pseudo instructions for loading and storing accumulator registers.
70let isPseudo = 1 in {
71  defm LOAD_AC128  : LoadM<"load_ac128", ACRegs128>;
72  defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
73}
74
75//===----------------------------------------------------------------------===//
76// Instruction definition
77//===----------------------------------------------------------------------===//
78let DecoderNamespace = "Mips64" in {
79/// Arithmetic Instructions (ALU Immediate)
80def DADDi   : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
81def DADDiu  : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith,
82                          immSExt16, add>,
83              ADDI_FM<0x19>, IsAsCheapAsAMove;
84def SLTi64  : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
85              SLTI_FM<0xa>;
86def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
87              SLTI_FM<0xb>;
88def ANDi64 : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
89                         and>,
90             ADDI_FM<0xc>;
91def ORi64   : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
92                          or>,
93              ADDI_FM<0xd>;
94def XORi64  : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
95                          xor>,
96              ADDI_FM<0xe>;
97def LUi64   : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
98
99/// Arithmetic Instructions (3-Operand, R-Type)
100def DADD   : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
101def DADDu  : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
102                              ADD_FM<0, 0x2d>;
103def DSUBu  : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
104                              ADD_FM<0, 0x2f>;
105def SLT64  : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
106def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
107def AND64  : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
108def OR64   : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
109def XOR64  : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
110def NOR64  : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
111
112/// Shift Instructions
113def DSLL   : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
114             SRA_FM<0x38, 0>;
115def DSRL   : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
116             SRA_FM<0x3a, 0>;
117def DSRA   : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
118             SRA_FM<0x3b, 0>;
119def DSLLV  : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
120def DSRLV  : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
121def DSRAV  : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
122def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
123def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
124def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
125}
126// Rotate Instructions
127let Predicates = [HasMips64r2, HasStdEnc],
128    DecoderNamespace = "Mips64" in {
129  def DROTR  : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
130               SRA_FM<0x3a, 1>;
131  def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
132               SRLV_FM<0x16, 1>;
133}
134
135let DecoderNamespace = "Mips64" in {
136/// Load and Store Instructions
137///  aligned
138defm LB64  : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>;
139defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>;
140defm LH64  : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>;
141defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>;
142defm LW64  : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>;
143defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>;
144defm SB64  : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>;
145defm SH64  : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>;
146defm SW64  : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>;
147defm LD    : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>;
148defm SD    : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>;
149
150/// load/store left/right
151defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
152defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
153defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
154defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
155
156defm LDL   : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
157defm LDR   : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
158defm SDL   : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
159defm SDR   : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
160
161/// Load-linked, Store-conditional
162let Predicates = [NotN64, HasStdEnc] in {
163  def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
164  def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
165}
166
167let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
168  def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
169  def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
170}
171
172/// Jump and Branch Instructions
173def JR64   : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
174def BEQ64  : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>;
175def BNE64  : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>;
176def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>;
177def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>;
178def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>;
179def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>;
180}
181let DecoderNamespace = "Mips64" in
182def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
183def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
184def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
185
186let DecoderNamespace = "Mips64" in {
187/// Multiply and Divide Instructions.
188def DMULT  : Mult<"dmult", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
189             MULT_FM<0, 0x1c>;
190def DMULTu : Mult<"dmultu", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
191             MULT_FM<0, 0x1d>;
192def PseudoDMULT  : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
193                                 IIImult>;
194def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
195                                 IIImult>;
196def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
197def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
198def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
199                                IIIdiv, 0, 1, 1>;
200def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
201                                IIIdiv, 0, 1, 1>;
202
203def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
204def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
205def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
206def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
207
208/// Sign Ext In Register Instructions.
209def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
210def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
211
212/// Count Leading
213def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
214def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
215
216/// Double Word Swap Bytes/HalfWords
217def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
218def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
219
220def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
221
222}
223let DecoderNamespace = "Mips64" in {
224def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
225
226def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
227let Pattern = []<dag> in {
228  def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
229  def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
230}
231def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
232let Pattern = []<dag> in {
233  def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
234  def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
235}
236
237let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
238  def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
239                     "dsll\t$rd, $rt, 32", [], IIArith>;
240  def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
241                    "sll\t$rd, $rt, 0", [], IIArith>;
242  def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
243                    "sll\t$rd, $rt, 0", [], IIArith>;
244}
245}
246//===----------------------------------------------------------------------===//
247//  Arbitrary patterns that map to one or more instructions
248//===----------------------------------------------------------------------===//
249
250// extended loads
251let Predicates = [NotN64, HasStdEnc] in {
252  def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
253  def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64 addr:$src)>;
254  def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
255  def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
256}
257let Predicates = [IsN64, HasStdEnc] in {
258  def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64_P8 addr:$src)>;
259  def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64_P8 addr:$src)>;
260  def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
261  def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
262}
263
264// hi/lo relocs
265def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
266def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
267def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
268def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
269def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
270def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
271
272def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
273def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
274def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
275def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
276def : MipsPat<(MipsLo tglobaltlsaddr:$in),
277              (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
278def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
279
280def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
281              (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
282def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
283              (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
284def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
285              (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
286def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
287              (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
288def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
289              (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
290
291def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
292def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
293def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
294def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
295def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
296def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
297
298defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
299                  ZERO_64>;
300
301def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
302              (BLEZ64 i64:$lhs, bb:$dst)>;
303def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
304              (BGEZ64 i64:$lhs, bb:$dst)>;
305
306// setcc patterns
307defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
308defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
309defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
310defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
311defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
312
313// truncate
314def : MipsPat<(i32 (trunc CPU64Regs:$src)),
315              (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
316      Requires<[IsN64, HasStdEnc]>;
317
318// 32-to-64-bit extension
319def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
320def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
321def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
322
323// Sign extend in register
324def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
325              (SLL64_64 CPU64Regs:$src)>;
326
327// bswap MipsPattern
328def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
329
330// mflo/hi patterns.
331def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
332              (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
333
334//===----------------------------------------------------------------------===//
335// Instruction aliases
336//===----------------------------------------------------------------------===//
337def : InstAlias<"move $dst, $src",
338                (DADDu CPU64RegsOpnd:$dst,  CPU64RegsOpnd:$src, ZERO_64), 1>,
339      Requires<[HasMips64]>;
340def : InstAlias<"and $rs, $rt, $imm",
341                (ANDi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
342                1>,
343      Requires<[HasMips64]>;
344def : InstAlias<"slt $rs, $rt, $imm",
345                (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
346      Requires<[HasMips64]>;
347def : InstAlias<"xor $rs, $rt, $imm",
348                (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
349                1>,
350      Requires<[HasMips64]>;
351def : InstAlias<"not $rt, $rs",
352                (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
353      Requires<[HasMips64]>;
354def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
355def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
356      Requires<[HasMips64]>;
357def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>,
358                 Requires<[HasMips64]>;
359def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>,
360                 Requires<[HasMips64]>;
361def : InstAlias<"daddu $rs, $rt, $imm",
362                (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
363                1>;
364def : InstAlias<"dadd $rs, $rt, $imm",
365                (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
366                1>;
367def : InstAlias<"or $rs, $rt, $imm",
368                (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
369                1>, Requires<[HasMips64]>;
370def : InstAlias<"bnez $rs,$offset",
371                 (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
372                 Requires<[HasMips64]>;
373def : InstAlias<"beqz $rs,$offset",
374                 (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
375                 Requires<[HasMips64]>;
376
377/// Move between CPU and coprocessor registers
378let DecoderNamespace = "Mips64" in {
379def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
380                         (ins CPU64RegsOpnd:$rd, uimm16:$sel),
381                         "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
382def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
383                         (ins CPU64RegsOpnd:$rt),
384                         "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
385def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
386                         (ins CPU64RegsOpnd:$rd, uimm16:$sel),
387                         "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
388def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
389                         (ins CPU64RegsOpnd:$rt),
390                         "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
391}
392
393// Two operand (implicit 0 selector) versions:
394def : InstAlias<"dmfc0 $rt, $rd",
395                (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
396def : InstAlias<"dmtc0 $rt, $rd",
397                (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
398def : InstAlias<"dmfc2 $rt, $rd",
399                (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
400def : InstAlias<"dmtc2 $rt, $rd",
401                (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
402
403