Mips64InstrInfo.td revision ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75
1d5bb405f54ca7cb5c1d86f01e4a7bf74f1f79aaaalokp@chromium.org//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2d5bb405f54ca7cb5c1d86f01e4a7bf74f1f79aaaalokp@chromium.org// 3d5bb405f54ca7cb5c1d86f01e4a7bf74f1f79aaaalokp@chromium.org// The LLVM Compiler Infrastructure 4d5bb405f54ca7cb5c1d86f01e4a7bf74f1f79aaaalokp@chromium.org// 5d5bb405f54ca7cb5c1d86f01e4a7bf74f1f79aaaalokp@chromium.org// This file is distributed under the University of Illinois Open Source 6d5bb405f54ca7cb5c1d86f01e4a7bf74f1f79aaaalokp@chromium.org// License. See LICENSE.TXT for details. 7fc8b72005b887731ca97db23354e61bdad4d8cd9alokp@chromium.org// 836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// 10fc8b72005b887731ca97db23354e61bdad4d8cd9alokp@chromium.org// This file describes Mips64 instructions. 1136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// 1236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 1336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 1436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 1536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Mips Operand, Complex Patterns and Transformations Definitions. 1636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 17c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org 1836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Instruction operand types 1936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef shamt_64 : Operand<i64>; 2036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 2136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Unsigned Operand 2236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef uimm16_64 : Operand<i64> { 2336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org let PrintMethod = "printUnsignedImm"; 2436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 25c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org 2636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Transformation Function - get Imm - 32. 2736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef Subtract32 : SDNodeXForm<imm, [{ 2836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org return getImm(N, (unsigned)N->getZExtValue() - 32); 2936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org}]>; 3036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 31c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org// shamt must fit in 6 bits. 3236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 3336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 3436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 3536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Instructions specific format 3636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 3736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Shifts 3836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// 64-bit shift instructions. 39c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.orglet DecoderNamespace = "Mips64" in { 4036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgclass shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm, 4136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org SDNode OpNode>: 4236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt, 4336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org CPU64Regs>; 4436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 45c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org// Mul, Div 4636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgclass Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 4736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 4836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgclass Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 4936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 5036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 5136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgmulticlass Atomic2Ops64<PatFrag Op, string Opstr> { 5236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, 53c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org Requires<[NotN64, HasStdEnc]>; 5436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, 5536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org Requires<[IsN64, HasStdEnc]> { 5636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org let isCodeGenOnly = 1; 5736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org } 5836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 5936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 6036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgmulticlass AtomicCmpSwap64<PatFrag Op, string Width> { 6136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, 6236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org Requires<[NotN64, HasStdEnc]>; 6336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, 6436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org Requires<[IsN64, HasStdEnc]> { 6536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org let isCodeGenOnly = 1; 6636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org } 6736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 6836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 6936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orglet usesCustomInserter = 1, Predicates = [HasStdEnc], 7036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org DecoderNamespace = "Mips64" in { 7136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; 7236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; 73c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; 7436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; 7536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; 7636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; 7736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; 7836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; 7936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 8036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 81c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org//===----------------------------------------------------------------------===// 8236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Instruction definition 8336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org//===----------------------------------------------------------------------===// 8436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orglet DecoderNamespace = "Mips64" in { 8536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org/// Arithmetic Instructions (ALU Immediate) 8636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DADDi : ArithLogicI<"daddi", simm16_64, immSExt16, CPU64Regs>, 87c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.org ADDI_FM<0x18>; 8836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DADDiu : ArithLogicI<"daddiu", simm16_64, immSExt16, CPU64Regs, add>, 8936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org ADDI_FM<0x19>, IsAsCheapAsAMove; 9036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DANDi : ArithLogicI<"andi", uimm16_64, immZExt16, CPU64Regs, and>, 9136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org ADDI_FM<0xc>; 9236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 9336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 947095d7a9bc09fa5776913b2ec973d4955b585d77Geoff Langdef ORi64 : ArithLogicI<"ori", uimm16_64, immZExt16, CPU64Regs, or>, 9536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org ADDI_FM<0xd>; 96c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.orgdef XORi64 : ArithLogicI<"xori", uimm16_64, immZExt16, CPU64Regs, xor>, 9736124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org ADDI_FM<0xe>; 9836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; 9936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 10036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org/// Arithmetic Instructions (3-Operand, R-Type) 10136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>; 10236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DADDu : ArithLogicR<"daddu", IIAlu, CPU64Regs, 1, add>, ADD_FM<0, 0x2d>; 10336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DSUBu : ArithLogicR<"dsubu", IIAlu, CPU64Regs, 0, sub>, ADD_FM<0, 0x2f>; 10436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 10536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 10636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef AND64 : ArithLogicR<"and", IIAlu, CPU64Regs, 1, and>, ADD_FM<0, 0x24>; 107c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.orgdef OR64 : ArithLogicR<"or", IIAlu, CPU64Regs, 1, or>, ADD_FM<0, 0x25>; 10836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef XOR64 : ArithLogicR<"xor", IIAlu, CPU64Regs, 1, xor>, ADD_FM<0, 0x26>; 10936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 11036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org 11136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org/// Shift Instructions 11236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>; 11336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>; 1147095d7a9bc09fa5776913b2ec973d4955b585d77Geoff Langdef DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; 11536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>; 11636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orgdef DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>; 117c745adb0b20dca8f0ac3c425733d51b3c5b623d3alokp@chromium.orgdef DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>; 11836124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orglet Pattern = []<dag> in { 11936124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def DSLL32 : shift_rotate_imm64<0x3c, 0x00, "dsll32", shl>; 12036124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def DSRL32 : shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl>; 12136124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org def DSRA32 : shift_rotate_imm64<0x3f, 0x00, "dsra32", sra>; 12236124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 12336124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org} 12436124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org// Rotate Instructions 12536124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.orglet Predicates = [HasMips64r2, HasStdEnc], 12636124de8ce9855c1cfdfb6529b47822e12123274alokp@chromium.org DecoderNamespace = "Mips64" in { 127 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; 128 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; 129} 130 131let DecoderNamespace = "Mips64" in { 132/// Load and Store Instructions 133/// aligned 134defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 135defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 136defm LH64 : LoadM64<0x21, "lh", sextloadi16>; 137defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>; 138defm LW64 : LoadM64<0x23, "lw", sextloadi32>; 139defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>; 140defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 141defm SH64 : StoreM64<0x29, "sh", truncstorei16>; 142defm SW64 : StoreM64<0x2b, "sw", truncstorei32>; 143defm LD : LoadM64<0x37, "ld", load>; 144defm SD : StoreM64<0x3f, "sd", store>; 145 146/// load/store left/right 147let isCodeGenOnly = 1 in { 148 defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>; 149 defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>; 150 defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>; 151 defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>; 152} 153defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>; 154defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>; 155defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>; 156defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>; 157 158/// Load-linked, Store-conditional 159def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, 160 Requires<[NotN64, HasStdEnc]>; 161def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, 162 Requires<[IsN64, HasStdEnc]> { 163 let isCodeGenOnly = 1; 164} 165def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, 166 Requires<[NotN64, HasStdEnc]>; 167def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, 168 Requires<[IsN64, HasStdEnc]> { 169 let isCodeGenOnly = 1; 170} 171 172/// Jump and Branch Instructions 173def JR64 : IndirectBranch<CPU64Regs>; 174def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; 175def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; 176def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 177def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 178def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>; 179def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 180} 181let DecoderNamespace = "Mips64" in 182def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; 183def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall; 184 185let DecoderNamespace = "Mips64" in { 186/// Multiply and Divide Instructions. 187def DMULT : Mult64<0x1c, "dmult", IIImul>; 188def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 189def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 190def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 191 192def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>; 193def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; 194def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; 195def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; 196 197/// Sign Ext In Register Instructions. 198def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>; 199def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>; 200 201/// Count Leading 202def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; 203def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; 204 205/// Double Word Swap Bytes/HalfWords 206def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; 207def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; 208 209def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 210} 211let DecoderNamespace = "Mips64" in { 212def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 213 214def DEXT : ExtBase<3, "dext", CPU64Regs>; 215let Pattern = []<dag> in { 216 def DEXTU : ExtBase<2, "dextu", CPU64Regs>; 217 def DEXTM : ExtBase<1, "dextm", CPU64Regs>; 218} 219def DINS : InsBase<7, "dins", CPU64Regs>; 220let Pattern = []<dag> in { 221 def DINSU : InsBase<6, "dinsu", CPU64Regs>; 222 def DINSM : InsBase<5, "dinsm", CPU64Regs>; 223} 224 225let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 226 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 227 "dsll\t$rd, $rt, 32", [], IIAlu>; 228 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 229 "sll\t$rd, $rt, 0", [], IIAlu>; 230 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 231 "sll\t$rd, $rt, 0", [], IIAlu>; 232} 233} 234//===----------------------------------------------------------------------===// 235// Arbitrary patterns that map to one or more instructions 236//===----------------------------------------------------------------------===// 237 238// extended loads 239let Predicates = [NotN64, HasStdEnc] in { 240 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 241 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 242 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 243 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 244} 245let Predicates = [IsN64, HasStdEnc] in { 246 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 247 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 248 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 249 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 250} 251 252// hi/lo relocs 253def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 254def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 255def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 256def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 257def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 258def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 259 260def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 261def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 262def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 263def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 264def : MipsPat<(MipsLo tglobaltlsaddr:$in), 265 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 266def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 267 268def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 269 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 270def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 271 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 272def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 273 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 274def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 275 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 276def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 277 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 278 279def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 280def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 281def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 282def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 283def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 284def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 285 286defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 287 ZERO_64>; 288 289// setcc patterns 290defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 291defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 292defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 293defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 294defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 295 296// truncate 297def : MipsPat<(i32 (trunc CPU64Regs:$src)), 298 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 299 Requires<[IsN64, HasStdEnc]>; 300 301// 32-to-64-bit extension 302def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 303def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 304def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 305 306// Sign extend in register 307def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 308 (SLL64_64 CPU64Regs:$src)>; 309 310// bswap MipsPattern 311def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 312 313//===----------------------------------------------------------------------===// 314// Instruction aliases 315//===----------------------------------------------------------------------===// 316def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 317 318/// Move between CPU and coprocessor registers 319let DecoderNamespace = "Mips64" in { 320def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), 321 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 322def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), 323 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; 324def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), 325 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 326def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), 327 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; 328def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), 329 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; 330def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), 331 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; 332def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), 333 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; 334def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), 335 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; 336} 337// Two operand (implicit 0 selector) versions: 338def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 339def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 340def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 341def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 342def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 343def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 344def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 345def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 346 347