Mips64InstrInfo.td revision c4889013553a4e407e110d1f76d9b6cf1396e702
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37// Shifts 38// 64-bit shift instructions. 39let DecoderNamespace = "Mips64" in { 40class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>: 41 shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>; 42 43// Mul, Div 44class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 45 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 46class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 47 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 48 49multiclass Atomic2Ops64<PatFrag Op, string Opstr> { 50 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, 51 Requires<[NotN64, HasStdEnc]>; 52 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, 53 Requires<[IsN64, HasStdEnc]> { 54 let isCodeGenOnly = 1; 55 } 56} 57 58multiclass AtomicCmpSwap64<PatFrag Op, string Width> { 59 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, 60 Requires<[NotN64, HasStdEnc]>; 61 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, 62 Requires<[IsN64, HasStdEnc]> { 63 let isCodeGenOnly = 1; 64 } 65} 66} 67let usesCustomInserter = 1, Predicates = [HasStdEnc], 68 DecoderNamespace = "Mips64" in { 69 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; 70 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; 71 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; 72 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; 73 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; 74 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; 75 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; 76 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; 77} 78 79//===----------------------------------------------------------------------===// 80// Instruction definition 81//===----------------------------------------------------------------------===// 82let DecoderNamespace = "Mips64" in { 83/// Arithmetic Instructions (ALU Immediate) 84def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>; 85def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>, 86 ADDI_FM<0x19>, IsAsCheapAsAMove; 87def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>, 88 ADDI_FM<0xc>; 89def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 90def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 91def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, 92 ADDI_FM<0xd>; 93def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, 94 ADDI_FM<0xe>; 95def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; 96 97/// Arithmetic Instructions (3-Operand, R-Type) 98def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; 99def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>; 100def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>; 101def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 102def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 103def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 104def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 105def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 106def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 107 108/// Shift Instructions 109def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>; 110def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>; 111def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>; 112def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>; 113def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>; 114def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>; 115def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>; 116def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>; 117def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>; 118} 119// Rotate Instructions 120let Predicates = [HasMips64r2, HasStdEnc], 121 DecoderNamespace = "Mips64" in { 122 def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>; 123 def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>; 124} 125 126let DecoderNamespace = "Mips64" in { 127/// Load and Store Instructions 128/// aligned 129defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 130defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 131defm LH64 : LoadM64<0x21, "lh", sextloadi16>; 132defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>; 133defm LW64 : LoadM64<0x23, "lw", sextloadi32>; 134defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>; 135defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 136defm SH64 : StoreM64<0x29, "sh", truncstorei16>; 137defm SW64 : StoreM64<0x2b, "sw", truncstorei32>; 138defm LD : LoadM64<0x37, "ld", load>; 139defm SD : StoreM64<0x3f, "sd", store>; 140 141/// load/store left/right 142let isCodeGenOnly = 1 in { 143 defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>; 144 defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>; 145 defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>; 146 defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>; 147} 148defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>; 149defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>; 150defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>; 151defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>; 152 153/// Load-linked, Store-conditional 154def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, 155 Requires<[NotN64, HasStdEnc]>; 156def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, 157 Requires<[IsN64, HasStdEnc]> { 158 let isCodeGenOnly = 1; 159} 160def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, 161 Requires<[NotN64, HasStdEnc]>; 162def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, 163 Requires<[IsN64, HasStdEnc]> { 164 let isCodeGenOnly = 1; 165} 166 167/// Jump and Branch Instructions 168def JR64 : IndirectBranch<CPU64Regs>; 169def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 170def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 171def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 172def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 173def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>; 174def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 175} 176let DecoderNamespace = "Mips64" in 177def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; 178def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall; 179 180let DecoderNamespace = "Mips64" in { 181/// Multiply and Divide Instructions. 182def DMULT : Mult64<0x1c, "dmult", IIImul>; 183def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 184def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 185def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 186 187def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>; 188def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; 189def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; 190def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; 191 192/// Sign Ext In Register Instructions. 193def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>; 194def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>; 195 196/// Count Leading 197def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; 198def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; 199 200/// Double Word Swap Bytes/HalfWords 201def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; 202def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; 203 204def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 205} 206let DecoderNamespace = "Mips64" in { 207def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 208 209def DEXT : ExtBase<3, "dext", CPU64Regs>; 210let Pattern = []<dag> in { 211 def DEXTU : ExtBase<2, "dextu", CPU64Regs>; 212 def DEXTM : ExtBase<1, "dextm", CPU64Regs>; 213} 214def DINS : InsBase<7, "dins", CPU64Regs>; 215let Pattern = []<dag> in { 216 def DINSU : InsBase<6, "dinsu", CPU64Regs>; 217 def DINSM : InsBase<5, "dinsm", CPU64Regs>; 218} 219 220let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 221 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 222 "dsll\t$rd, $rt, 32", [], IIAlu>; 223 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 224 "sll\t$rd, $rt, 0", [], IIAlu>; 225 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 226 "sll\t$rd, $rt, 0", [], IIAlu>; 227} 228} 229//===----------------------------------------------------------------------===// 230// Arbitrary patterns that map to one or more instructions 231//===----------------------------------------------------------------------===// 232 233// extended loads 234let Predicates = [NotN64, HasStdEnc] in { 235 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 236 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 237 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 238 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 239} 240let Predicates = [IsN64, HasStdEnc] in { 241 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 242 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 243 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 244 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 245} 246 247// hi/lo relocs 248def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 249def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 250def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 251def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 252def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 253def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 254 255def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 256def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 257def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 258def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 259def : MipsPat<(MipsLo tglobaltlsaddr:$in), 260 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 261def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 262 263def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 264 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 265def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 266 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 267def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 268 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 269def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 270 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 271def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 272 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 273 274def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 275def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 276def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 277def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 278def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 279def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 280 281defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 282 ZERO_64>; 283 284// setcc patterns 285defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 286defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 287defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 288defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 289defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 290 291// truncate 292def : MipsPat<(i32 (trunc CPU64Regs:$src)), 293 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 294 Requires<[IsN64, HasStdEnc]>; 295 296// 32-to-64-bit extension 297def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 298def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 299def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 300 301// Sign extend in register 302def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 303 (SLL64_64 CPU64Regs:$src)>; 304 305// bswap MipsPattern 306def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 307 308//===----------------------------------------------------------------------===// 309// Instruction aliases 310//===----------------------------------------------------------------------===// 311def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 312 313/// Move between CPU and coprocessor registers 314let DecoderNamespace = "Mips64" in { 315def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), 316 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 317def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), 318 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; 319def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), 320 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 321def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), 322 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; 323def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), 324 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; 325def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), 326 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; 327def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), 328 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; 329def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), 330 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; 331} 332// Two operand (implicit 0 selector) versions: 333def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 334def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 335def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 336def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 337def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 338def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 339def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 340def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 341 342