Mips64InstrInfo.td revision cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37// Shifts 38// 64-bit shift instructions. 39let DecoderNamespace = "Mips64" in { 40class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>: 41 shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>; 42 43// Mul, Div 44class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: 45 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 46class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 47 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; 48 49multiclass Atomic2Ops64<PatFrag Op, string Opstr> { 50 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, 51 Requires<[NotN64, HasStdEnc]>; 52 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, 53 Requires<[IsN64, HasStdEnc]> { 54 let isCodeGenOnly = 1; 55 } 56} 57 58multiclass AtomicCmpSwap64<PatFrag Op, string Width> { 59 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, 60 Requires<[NotN64, HasStdEnc]>; 61 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, 62 Requires<[IsN64, HasStdEnc]> { 63 let isCodeGenOnly = 1; 64 } 65} 66} 67let usesCustomInserter = 1, Predicates = [HasStdEnc], 68 DecoderNamespace = "Mips64" in { 69 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; 70 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; 71 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; 72 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; 73 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; 74 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; 75 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; 76 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; 77} 78 79//===----------------------------------------------------------------------===// 80// Instruction definition 81//===----------------------------------------------------------------------===// 82let DecoderNamespace = "Mips64" in { 83/// Arithmetic Instructions (ALU Immediate) 84def DADDi : ArithLogicI<"daddi", simm16_64, immSExt16, CPU64Regs>, 85 ADDI_FM<0x18>; 86def DADDiu : ArithLogicI<"daddiu", simm16_64, immSExt16, CPU64Regs, add>, 87 ADDI_FM<0x19>, IsAsCheapAsAMove; 88def DANDi : ArithLogicI<"andi", uimm16_64, immZExt16, CPU64Regs, and>, 89 ADDI_FM<0xc>; 90def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 91def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; 92def ORi64 : ArithLogicI<"ori", uimm16_64, immZExt16, CPU64Regs, or>, 93 ADDI_FM<0xd>; 94def XORi64 : ArithLogicI<"xori", uimm16_64, immZExt16, CPU64Regs, xor>, 95 ADDI_FM<0xe>; 96def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; 97 98/// Arithmetic Instructions (3-Operand, R-Type) 99def DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>; 100def DADDu : ArithLogicR<"daddu", IIAlu, CPU64Regs, 1, add>, ADD_FM<0, 0x2d>; 101def DSUBu : ArithLogicR<"dsubu", IIAlu, CPU64Regs, 0, sub>, ADD_FM<0, 0x2f>; 102def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 103def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; 104def AND64 : ArithLogicR<"and", IIAlu, CPU64Regs, 1, and>, ADD_FM<0, 0x24>; 105def OR64 : ArithLogicR<"or", IIAlu, CPU64Regs, 1, or>, ADD_FM<0, 0x25>; 106def XOR64 : ArithLogicR<"xor", IIAlu, CPU64Regs, 1, xor>, ADD_FM<0, 0x26>; 107def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; 108 109/// Shift Instructions 110def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>; 111def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>; 112def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>; 113def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>; 114def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>; 115def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>; 116def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>; 117def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>; 118def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>; 119} 120// Rotate Instructions 121let Predicates = [HasMips64r2, HasStdEnc], 122 DecoderNamespace = "Mips64" in { 123 def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>; 124 def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>; 125} 126 127let DecoderNamespace = "Mips64" in { 128/// Load and Store Instructions 129/// aligned 130defm LB64 : LoadM64<0x20, "lb", sextloadi8>; 131defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; 132defm LH64 : LoadM64<0x21, "lh", sextloadi16>; 133defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>; 134defm LW64 : LoadM64<0x23, "lw", sextloadi32>; 135defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>; 136defm SB64 : StoreM64<0x28, "sb", truncstorei8>; 137defm SH64 : StoreM64<0x29, "sh", truncstorei16>; 138defm SW64 : StoreM64<0x2b, "sw", truncstorei32>; 139defm LD : LoadM64<0x37, "ld", load>; 140defm SD : StoreM64<0x3f, "sd", store>; 141 142/// load/store left/right 143let isCodeGenOnly = 1 in { 144 defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>; 145 defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>; 146 defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>; 147 defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>; 148} 149defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>; 150defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>; 151defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>; 152defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>; 153 154/// Load-linked, Store-conditional 155def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, 156 Requires<[NotN64, HasStdEnc]>; 157def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, 158 Requires<[IsN64, HasStdEnc]> { 159 let isCodeGenOnly = 1; 160} 161def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, 162 Requires<[NotN64, HasStdEnc]>; 163def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, 164 Requires<[IsN64, HasStdEnc]> { 165 let isCodeGenOnly = 1; 166} 167 168/// Jump and Branch Instructions 169def JR64 : IndirectBranch<CPU64Regs>; 170def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; 171def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; 172def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; 173def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; 174def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>; 175def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; 176} 177let DecoderNamespace = "Mips64" in 178def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; 179def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall; 180 181let DecoderNamespace = "Mips64" in { 182/// Multiply and Divide Instructions. 183def DMULT : Mult64<0x1c, "dmult", IIImul>; 184def DMULTu : Mult64<0x1d, "dmultu", IIImul>; 185def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; 186def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; 187 188def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>; 189def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; 190def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; 191def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; 192 193/// Sign Ext In Register Instructions. 194def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>; 195def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>; 196 197/// Count Leading 198def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; 199def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; 200 201/// Double Word Swap Bytes/HalfWords 202def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; 203def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; 204 205def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>; 206} 207let DecoderNamespace = "Mips64" in { 208def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; 209 210def DEXT : ExtBase<3, "dext", CPU64Regs>; 211let Pattern = []<dag> in { 212 def DEXTU : ExtBase<2, "dextu", CPU64Regs>; 213 def DEXTM : ExtBase<1, "dextm", CPU64Regs>; 214} 215def DINS : InsBase<7, "dins", CPU64Regs>; 216let Pattern = []<dag> in { 217 def DINSU : InsBase<6, "dinsu", CPU64Regs>; 218 def DINSM : InsBase<5, "dinsm", CPU64Regs>; 219} 220 221let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 222 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 223 "dsll\t$rd, $rt, 32", [], IIAlu>; 224 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 225 "sll\t$rd, $rt, 0", [], IIAlu>; 226 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 227 "sll\t$rd, $rt, 0", [], IIAlu>; 228} 229} 230//===----------------------------------------------------------------------===// 231// Arbitrary patterns that map to one or more instructions 232//===----------------------------------------------------------------------===// 233 234// extended loads 235let Predicates = [NotN64, HasStdEnc] in { 236 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 237 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 238 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 239 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 240} 241let Predicates = [IsN64, HasStdEnc] in { 242 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 243 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 244 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 245 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 246} 247 248// hi/lo relocs 249def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 250def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 251def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 252def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 253def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 254def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 255 256def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 257def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 258def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 259def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 260def : MipsPat<(MipsLo tglobaltlsaddr:$in), 261 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 262def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 263 264def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 265 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 266def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 267 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 268def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 269 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 270def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 271 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 272def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 273 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 274 275def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 276def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 277def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 278def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 279def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 280def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 281 282defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 283 ZERO_64>; 284 285// setcc patterns 286defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 287defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 288defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 289defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 290defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 291 292// truncate 293def : MipsPat<(i32 (trunc CPU64Regs:$src)), 294 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 295 Requires<[IsN64, HasStdEnc]>; 296 297// 32-to-64-bit extension 298def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 299def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 300def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 301 302// Sign extend in register 303def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 304 (SLL64_64 CPU64Regs:$src)>; 305 306// bswap MipsPattern 307def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 308 309//===----------------------------------------------------------------------===// 310// Instruction aliases 311//===----------------------------------------------------------------------===// 312def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 313 314/// Move between CPU and coprocessor registers 315let DecoderNamespace = "Mips64" in { 316def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), 317 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 318def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), 319 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; 320def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), 321 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 322def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), 323 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; 324def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), 325 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; 326def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), 327 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; 328def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), 329 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; 330def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), 331 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; 332} 333// Two operand (implicit 0 selector) versions: 334def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 335def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 336def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 337def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 338def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 339def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 340def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 341def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 342 343