Mips64InstrInfo.td revision dbf51ee4596791d8cf38538b80805b2c3a577836
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37// Shifts 38// 64-bit shift instructions. 39let DecoderNamespace = "Mips64" in { 40class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>: 41 shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>; 42 43multiclass Atomic2Ops64<PatFrag Op> { 44 def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>, 45 Requires<[NotN64, HasStdEnc]>; 46 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 47 Requires<[IsN64, HasStdEnc]> { 48 let isCodeGenOnly = 1; 49 } 50} 51 52multiclass AtomicCmpSwap64<PatFrag Op> { 53 def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 54 Requires<[NotN64, HasStdEnc]>; 55 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 56 Requires<[IsN64, HasStdEnc]> { 57 let isCodeGenOnly = 1; 58 } 59} 60} 61let usesCustomInserter = 1, Predicates = [HasStdEnc], 62 DecoderNamespace = "Mips64" in { 63 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 64 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 65 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 66 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 67 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 68 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 69 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 70 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 71} 72 73//===----------------------------------------------------------------------===// 74// Instruction definition 75//===----------------------------------------------------------------------===// 76let DecoderNamespace = "Mips64" in { 77/// Arithmetic Instructions (ALU Immediate) 78def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>; 79def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>, 80 ADDI_FM<0x19>, IsAsCheapAsAMove; 81def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>, 82 ADDI_FM<0xc>; 83def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 84 SLTI_FM<0xa>; 85def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 86 SLTI_FM<0xb>; 87def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, 88 ADDI_FM<0xd>; 89def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, 90 ADDI_FM<0xe>; 91def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 92 93/// Arithmetic Instructions (3-Operand, R-Type) 94def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; 95def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>; 96def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>; 97def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 98def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 99def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 100def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 101def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 102def NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>; 103 104/// Shift Instructions 105def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>; 106def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>; 107def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>; 108def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>; 109def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>; 110def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>; 111def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>; 112def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>; 113def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>; 114} 115// Rotate Instructions 116let Predicates = [HasMips64r2, HasStdEnc], 117 DecoderNamespace = "Mips64" in { 118 def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>; 119 def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>; 120} 121 122let DecoderNamespace = "Mips64" in { 123/// Load and Store Instructions 124/// aligned 125defm LB64 : LoadM<"lb", sextloadi8, CPU64Regs>, LW_FM<0x20>; 126defm LBu64 : LoadM<"lbu", zextloadi8, CPU64Regs>, LW_FM<0x24>; 127defm LH64 : LoadM<"lh", sextloadi16, CPU64Regs>, LW_FM<0x21>; 128defm LHu64 : LoadM<"lhu", zextloadi16, CPU64Regs>, LW_FM<0x25>; 129defm LW64 : LoadM<"lw", sextloadi32, CPU64Regs>, LW_FM<0x23>; 130defm LWu64 : LoadM<"lwu", zextloadi32, CPU64Regs>, LW_FM<0x27>; 131defm SB64 : StoreM<"sb", truncstorei8, CPU64Regs>, LW_FM<0x28>; 132defm SH64 : StoreM<"sh", truncstorei16, CPU64Regs>, LW_FM<0x29>; 133defm SW64 : StoreM<"sw", truncstorei32, CPU64Regs>, LW_FM<0x2b>; 134defm LD : LoadM<"ld", load, CPU64Regs>, LW_FM<0x37>; 135defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>; 136 137/// load/store left/right 138let isCodeGenOnly = 1 in { 139 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 140 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 141 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 142 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 143} 144defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 145defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 146defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 147defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 148 149/// Load-linked, Store-conditional 150let Predicates = [NotN64, HasStdEnc] in { 151 def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>; 152 def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>; 153} 154 155let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 156 def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>; 157 def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>; 158} 159 160/// Jump and Branch Instructions 161def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 162def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 163def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 164def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; 165def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; 166def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; 167def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; 168} 169let DecoderNamespace = "Mips64" in 170def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 171def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 172 173let DecoderNamespace = "Mips64" in { 174/// Multiply and Divide Instructions. 175def DMULT : Mult<"dmult", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1c>; 176def DMULTu : Mult<"dmultu", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1d>; 177def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64Regs, [HI64, LO64]>, 178 MULT_FM<0, 0x1e>; 179def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64Regs, [HI64, LO64]>, 180 MULT_FM<0, 0x1f>; 181 182def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 183def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 184def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 185def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 186 187/// Sign Ext In Register Instructions. 188def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 189def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 190 191/// Count Leading 192def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>; 193def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>; 194 195/// Double Word Swap Bytes/HalfWords 196def DSBH : SubwordSwap<"dsbh", CPU64Regs>, SEB_FM<2, 0x24>; 197def DSHD : SubwordSwap<"dshd", CPU64Regs>, SEB_FM<5, 0x24>; 198 199def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 200 201} 202let DecoderNamespace = "Mips64" in { 203def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>, RDHWR_FM; 204 205def DEXT : ExtBase<"dext", CPU64Regs>, EXT_FM<3>; 206let Pattern = []<dag> in { 207 def DEXTU : ExtBase<"dextu", CPU64Regs>, EXT_FM<2>; 208 def DEXTM : ExtBase<"dextm", CPU64Regs>, EXT_FM<1>; 209} 210def DINS : InsBase<"dins", CPU64Regs>, EXT_FM<7>; 211let Pattern = []<dag> in { 212 def DINSU : InsBase<"dinsu", CPU64Regs>, EXT_FM<6>; 213 def DINSM : InsBase<"dinsm", CPU64Regs>, EXT_FM<5>; 214} 215 216let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 217 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 218 "dsll\t$rd, $rt, 32", [], IIAlu>; 219 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 220 "sll\t$rd, $rt, 0", [], IIAlu>; 221 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 222 "sll\t$rd, $rt, 0", [], IIAlu>; 223} 224} 225//===----------------------------------------------------------------------===// 226// Arbitrary patterns that map to one or more instructions 227//===----------------------------------------------------------------------===// 228 229// extended loads 230let Predicates = [NotN64, HasStdEnc] in { 231 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 232 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 233 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 234 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 235} 236let Predicates = [IsN64, HasStdEnc] in { 237 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 238 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 239 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 240 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 241} 242 243// hi/lo relocs 244def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 245def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 246def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 247def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 248def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 249def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 250 251def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 252def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 253def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 254def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 255def : MipsPat<(MipsLo tglobaltlsaddr:$in), 256 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 257def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 258 259def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 260 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 261def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 262 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 263def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 264 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 265def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 266 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 267def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 268 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 269 270def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 271def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 272def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 273def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 274def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 275def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 276 277defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 278 ZERO_64>; 279 280// setcc patterns 281defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 282defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 283defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 284defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 285defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 286 287// truncate 288def : MipsPat<(i32 (trunc CPU64Regs:$src)), 289 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 290 Requires<[IsN64, HasStdEnc]>; 291 292// 32-to-64-bit extension 293def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 294def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 295def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 296 297// Sign extend in register 298def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 299 (SLL64_64 CPU64Regs:$src)>; 300 301// bswap MipsPattern 302def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 303 304//===----------------------------------------------------------------------===// 305// Instruction aliases 306//===----------------------------------------------------------------------===// 307def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>; 308 309/// Move between CPU and coprocessor registers 310let DecoderNamespace = "Mips64" in { 311def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt), 312 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 313def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel), 314 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">; 315def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt), 316 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 317def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel), 318 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">; 319def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt), 320 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">; 321def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel), 322 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">; 323def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt), 324 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">; 325def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel), 326 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">; 327} 328// Two operand (implicit 0 selector) versions: 329def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 330def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 331def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 332def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 333def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 334def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 335def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>; 336def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>; 337 338