Mips64InstrInfo.td revision ddbdeefa286374a1f036d5e80987306749d3f729
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37let DecoderNamespace = "Mips64" in { 38 39multiclass Atomic2Ops64<PatFrag Op> { 40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 41 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>; 42} 43 44multiclass AtomicCmpSwap64<PatFrag Op> { 45 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 46 Requires<[NotN64, HasStdEnc]>; 47 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 48 Requires<[IsN64, HasStdEnc]>; 49} 50} 51let usesCustomInserter = 1, Predicates = [HasStdEnc], 52 DecoderNamespace = "Mips64" in { 53 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 54 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 55 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 56 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 57 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 58 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 59 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 60 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 61} 62 63/// Pseudo instructions for loading and storing accumulator registers. 64let isPseudo = 1, isCodeGenOnly = 1 in { 65 defm LOAD_AC128 : LoadM<"", ACRegs128>; 66 defm STORE_AC128 : StoreM<"", ACRegs128>; 67} 68 69//===----------------------------------------------------------------------===// 70// Instruction definition 71//===----------------------------------------------------------------------===// 72let DecoderNamespace = "Mips64" in { 73/// Arithmetic Instructions (ALU Immediate) 74def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; 75def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith, 76 immSExt16, add>, 77 ADDI_FM<0x19>, IsAsCheapAsAMove; 78def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 79 SLTI_FM<0xa>; 80def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 81 SLTI_FM<0xb>; 82def ANDi64 : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16, 83 and>, 84 ADDI_FM<0xc>; 85def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16, 86 or>, 87 ADDI_FM<0xd>; 88def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16, 89 xor>, 90 ADDI_FM<0xe>; 91def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 92 93/// Arithmetic Instructions (3-Operand, R-Type) 94def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; 95def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>, 96 ADD_FM<0, 0x2d>; 97def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>, 98 ADD_FM<0, 0x2f>; 99def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 100def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 101def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>; 102def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>; 103def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>; 104def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>; 105 106/// Shift Instructions 107def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>, 108 SRA_FM<0x38, 0>; 109def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>, 110 SRA_FM<0x3a, 0>; 111def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>, 112 SRA_FM<0x3b, 0>; 113def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>; 114def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>; 115def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>; 116def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>; 117def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>; 118def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>; 119} 120// Rotate Instructions 121let Predicates = [HasMips64r2, HasStdEnc], 122 DecoderNamespace = "Mips64" in { 123 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>, 124 SRA_FM<0x3a, 1>; 125 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, 126 SRLV_FM<0x16, 1>; 127} 128 129let DecoderNamespace = "Mips64" in { 130/// Load and Store Instructions 131/// aligned 132defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>; 133defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>; 134defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>; 135defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>; 136defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>; 137defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>; 138defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>; 139defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>; 140defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>; 141defm LD : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>; 142defm SD : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>; 143 144/// load/store left/right 145defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 146defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 147defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 148defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 149 150defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 151defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 152defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 153defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 154 155/// Load-linked, Store-conditional 156let Predicates = [NotN64, HasStdEnc] in { 157 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>; 158 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>; 159} 160 161let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 162 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>; 163 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>; 164} 165 166/// Jump and Branch Instructions 167def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 168def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>; 169def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>; 170def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>; 171def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>; 172def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>; 173def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>; 174} 175let DecoderNamespace = "Mips64" in 176def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 177def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>; 178def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 179 180let DecoderNamespace = "Mips64" in { 181/// Multiply and Divide Instructions. 182def DMULT : Mult<"dmult", IIImult, CPU64RegsOpnd, [HI64, LO64]>, 183 MULT_FM<0, 0x1c>; 184def DMULTu : Mult<"dmultu", IIImult, CPU64RegsOpnd, [HI64, LO64]>, 185 MULT_FM<0, 0x1d>; 186def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult, 187 IIImult>; 188def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu, 189 IIImult>; 190def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>; 191def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>; 192def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem, 193 IIIdiv, 0, 1, 1>; 194def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU, 195 IIIdiv, 0, 1, 1>; 196 197def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 198def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 199def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 200def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 201 202/// Sign Ext In Register Instructions. 203def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 204def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 205 206/// Count Leading 207def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>; 208def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>; 209 210/// Double Word Swap Bytes/HalfWords 211def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>; 212def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>; 213 214def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 215 216} 217let DecoderNamespace = "Mips64" in { 218def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM; 219 220def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>; 221let Pattern = []<dag> in { 222 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>; 223 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>; 224} 225def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>; 226let Pattern = []<dag> in { 227 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>; 228 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>; 229} 230 231let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 232 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 233 "dsll\t$rd, $rt, 32", [], IIArith>; 234 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 235 "sll\t$rd, $rt, 0", [], IIArith>; 236 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 237 "sll\t$rd, $rt, 0", [], IIArith>; 238} 239} 240//===----------------------------------------------------------------------===// 241// Arbitrary patterns that map to one or more instructions 242//===----------------------------------------------------------------------===// 243 244// extended loads 245let Predicates = [NotN64, HasStdEnc] in { 246 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 247 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 248 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 249 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 250} 251let Predicates = [IsN64, HasStdEnc] in { 252 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 253 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 254 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 255 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 256} 257 258// hi/lo relocs 259def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 260def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 261def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 262def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 263def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 264def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 265 266def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 267def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 268def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 269def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 270def : MipsPat<(MipsLo tglobaltlsaddr:$in), 271 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 272def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 273 274def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 275 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 276def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 277 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 278def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 279 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 280def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 281 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 282def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 283 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 284 285def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 286def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 287def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 288def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 289def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 290def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 291 292defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 293 ZERO_64>; 294 295def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 296 (BLEZ64 i64:$lhs, bb:$dst)>; 297def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 298 (BGEZ64 i64:$lhs, bb:$dst)>; 299 300// setcc patterns 301defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 302defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 303defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 304defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 305defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 306 307// truncate 308def : MipsPat<(i32 (trunc CPU64Regs:$src)), 309 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 310 Requires<[IsN64, HasStdEnc]>; 311 312// 32-to-64-bit extension 313def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 314def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 315def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 316 317// Sign extend in register 318def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 319 (SLL64_64 CPU64Regs:$src)>; 320 321// bswap MipsPattern 322def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 323 324// mflo/hi patterns. 325def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)), 326 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>; 327 328//===----------------------------------------------------------------------===// 329// Instruction aliases 330//===----------------------------------------------------------------------===// 331def : InstAlias<"move $dst, $src", 332 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 333 Requires<[HasMips64]>; 334def : InstAlias<"and $rs, $rt, $imm", 335 (ANDi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 336 1>, 337 Requires<[HasMips64]>; 338def : InstAlias<"slt $rs, $rt, $imm", 339 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>, 340 Requires<[HasMips64]>; 341def : InstAlias<"xor $rs, $rt, $imm", 342 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 343 1>, 344 Requires<[HasMips64]>; 345def : InstAlias<"not $rt, $rs", 346 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, 347 Requires<[HasMips64]>; 348def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; 349def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>, 350 Requires<[HasMips64]>; 351def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>, 352 Requires<[HasMips64]>; 353def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>, 354 Requires<[HasMips64]>; 355def : InstAlias<"daddu $rs, $rt, $imm", 356 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 357 1>; 358def : InstAlias<"dadd $rs, $rt, $imm", 359 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 360 1>; 361def : InstAlias<"or $rs, $rt, $imm", 362 (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 363 1>, Requires<[HasMips64]>; 364def : InstAlias<"bnez $rs,$offset", 365 (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>, 366 Requires<[HasMips64]>; 367def : InstAlias<"beqz $rs,$offset", 368 (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>, 369 Requires<[HasMips64]>; 370 371/// Move between CPU and coprocessor registers 372let DecoderNamespace = "Mips64" in { 373def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 374 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 375 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>; 376def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 377 (ins CPU64RegsOpnd:$rt), 378 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>; 379def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 380 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 381 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>; 382def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 383 (ins CPU64RegsOpnd:$rt), 384 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>; 385} 386 387// Two operand (implicit 0 selector) versions: 388def : InstAlias<"dmfc0 $rt, $rd", 389 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 390def : InstAlias<"dmtc0 $rt, $rd", 391 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 392def : InstAlias<"dmfc2 $rt, $rd", 393 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 394def : InstAlias<"dmtc2 $rt, $rd", 395 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 396 397