Mips64InstrInfo.td revision e72fac60e3dbcf14ec68cedc1e86feafec1652eb
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37let DecoderNamespace = "Mips64" in { 38 39multiclass Atomic2Ops64<PatFrag Op> { 40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, 41 Requires<[NotN64, HasStdEnc]>; 42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 43 Requires<[IsN64, HasStdEnc]> { 44 let isCodeGenOnly = 1; 45 } 46} 47 48multiclass AtomicCmpSwap64<PatFrag Op> { 49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 50 Requires<[NotN64, HasStdEnc]>; 51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 52 Requires<[IsN64, HasStdEnc]> { 53 let isCodeGenOnly = 1; 54 } 55} 56} 57let usesCustomInserter = 1, Predicates = [HasStdEnc], 58 DecoderNamespace = "Mips64" in { 59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 67} 68 69//===----------------------------------------------------------------------===// 70// Instruction definition 71//===----------------------------------------------------------------------===// 72let DecoderNamespace = "Mips64" in { 73/// Arithmetic Instructions (ALU Immediate) 74def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; 75def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>, 76 ADDI_FM<0x19>, IsAsCheapAsAMove; 77def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>, 78 ADDI_FM<0xc>; 79def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 80 SLTI_FM<0xa>; 81def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 82 SLTI_FM<0xb>; 83def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>, 84 ADDI_FM<0xd>; 85def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>, 86 ADDI_FM<0xe>; 87def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 88 89/// Arithmetic Instructions (3-Operand, R-Type) 90def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; 91def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>, 92 ADD_FM<0, 0x2d>; 93def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>, 94 ADD_FM<0, 0x2f>; 95def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 96def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 97def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 98def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 99def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 100def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>; 101 102/// Shift Instructions 103def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>, 104 SRA_FM<0x38, 0>; 105def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>, 106 SRA_FM<0x3a, 0>; 107def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>, 108 SRA_FM<0x3b, 0>; 109def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>; 110def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>; 111def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>; 112def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>; 113def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>; 114def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>; 115} 116// Rotate Instructions 117let Predicates = [HasMips64r2, HasStdEnc], 118 DecoderNamespace = "Mips64" in { 119 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>, 120 SRA_FM<0x3a, 1>; 121 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, 122 SRLV_FM<0x16, 1>; 123} 124 125let DecoderNamespace = "Mips64" in { 126/// Load and Store Instructions 127/// aligned 128defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>; 129defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>; 130defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>; 131defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>; 132defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>; 133defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>; 134defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>; 135defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>; 136defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>; 137defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>; 138defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>; 139 140/// load/store left/right 141defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 142defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 143defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 144defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 145 146defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 147defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 148defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 149defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 150 151/// Load-linked, Store-conditional 152let Predicates = [NotN64, HasStdEnc] in { 153 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>; 154 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>; 155} 156 157let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 158 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>; 159 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>; 160} 161 162/// Jump and Branch Instructions 163def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 164def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 165def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 166def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; 167def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; 168def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; 169def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; 170} 171let DecoderNamespace = "Mips64" in 172def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 173def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 174 175let DecoderNamespace = "Mips64" in { 176/// Multiply and Divide Instructions. 177def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 178 MULT_FM<0, 0x1c>; 179def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 180 MULT_FM<0, 0x1d>; 181def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, 182 MULT_FM<0, 0x1e>; 183def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, 184 MULT_FM<0, 0x1f>; 185 186def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 187def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 188def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 189def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 190 191/// Sign Ext In Register Instructions. 192def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 193def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 194 195/// Count Leading 196def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>; 197def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>; 198 199/// Double Word Swap Bytes/HalfWords 200def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>; 201def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>; 202 203def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 204 205} 206let DecoderNamespace = "Mips64" in { 207def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM; 208 209def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>; 210let Pattern = []<dag> in { 211 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>; 212 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>; 213} 214def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>; 215let Pattern = []<dag> in { 216 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>; 217 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>; 218} 219 220let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 221 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 222 "dsll\t$rd, $rt, 32", [], IIAlu>; 223 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 224 "sll\t$rd, $rt, 0", [], IIAlu>; 225 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 226 "sll\t$rd, $rt, 0", [], IIAlu>; 227} 228} 229//===----------------------------------------------------------------------===// 230// Arbitrary patterns that map to one or more instructions 231//===----------------------------------------------------------------------===// 232 233// extended loads 234let Predicates = [NotN64, HasStdEnc] in { 235 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 236 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 237 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 238 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 239} 240let Predicates = [IsN64, HasStdEnc] in { 241 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 242 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 243 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 244 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 245} 246 247// hi/lo relocs 248def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 249def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 250def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 251def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 252def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 253def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 254 255def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 256def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 257def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 258def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 259def : MipsPat<(MipsLo tglobaltlsaddr:$in), 260 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 261def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 262 263def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 264 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 265def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 266 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 267def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 268 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 269def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 270 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 271def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 272 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 273 274def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 275def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 276def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 277def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 278def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 279def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 280 281defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 282 ZERO_64>; 283 284// setcc patterns 285defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 286defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 287defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 288defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 289defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 290 291// truncate 292def : MipsPat<(i32 (trunc CPU64Regs:$src)), 293 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 294 Requires<[IsN64, HasStdEnc]>; 295 296// 32-to-64-bit extension 297def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 298def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 299def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 300 301// Sign extend in register 302def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 303 (SLL64_64 CPU64Regs:$src)>; 304 305// bswap MipsPattern 306def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 307 308//===----------------------------------------------------------------------===// 309// Instruction aliases 310//===----------------------------------------------------------------------===// 311def : InstAlias<"move $dst, $src", (DADDu CPU64RegsOpnd:$dst, 312 CPU64RegsOpnd:$src,ZERO_64)>, 313 Requires<[HasMips64]>; 314def : InstAlias<"and $rs, $rt, $imm", 315 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>, 316 Requires<[HasMips64]>; 317def : InstAlias<"slt $rs, $rt, $imm", 318 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm)>, 319 Requires<[HasMips64]>; 320def : InstAlias<"xor $rs, $rt, $imm", 321 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm)>, 322 Requires<[HasMips64]>; 323def : InstAlias<"not $rt, $rs", 324 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64)>, 325 Requires<[HasMips64]>; 326def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs)>, Requires<[HasMips64]>; 327def : InstAlias<"daddu $rs, $rt, $imm", 328 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>; 329def : InstAlias<"dadd $rs, $rt, $imm", 330 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm)>; 331 332/// Move between CPU and coprocessor registers 333 334let DecoderNamespace = "Mips64" in { 335def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 336 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 337 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>; 338def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 339 (ins CPU64RegsOpnd:$rt), 340 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>; 341def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 342 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 343 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>; 344def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 345 (ins CPU64RegsOpnd:$rt), 346 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>; 347} 348 349// Two operand (implicit 0 selector) versions: 350def : InstAlias<"dmfc0 $rt, $rd", 351 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>; 352def : InstAlias<"dmtc0 $rt, $rd", 353 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>; 354def : InstAlias<"dmfc2 $rt, $rd", 355 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0)>; 356def : InstAlias<"dmtc2 $rt, $rd", 357 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt)>; 358 359