Mips64InstrInfo.td revision f5926fd844a84adcf1ae4f193146f2877997b82c
1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Instruction operand types 19def shamt_64 : Operand<i64>; 20 21// Unsigned Operand 22def uimm16_64 : Operand<i64> { 23 let PrintMethod = "printUnsignedImm"; 24} 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34//===----------------------------------------------------------------------===// 35// Instructions specific format 36//===----------------------------------------------------------------------===// 37let DecoderNamespace = "Mips64" in { 38 39multiclass Atomic2Ops64<PatFrag Op> { 40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>, 41 Requires<[NotN64, HasStdEnc]>; 42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, 43 Requires<[IsN64, HasStdEnc]> { 44 let isCodeGenOnly = 1; 45 } 46} 47 48multiclass AtomicCmpSwap64<PatFrag Op> { 49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, 50 Requires<[NotN64, HasStdEnc]>; 51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, 52 Requires<[IsN64, HasStdEnc]> { 53 let isCodeGenOnly = 1; 54 } 55} 56} 57let usesCustomInserter = 1, Predicates = [HasStdEnc], 58 DecoderNamespace = "Mips64" in { 59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; 60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; 61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; 62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; 63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; 64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; 65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; 66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; 67} 68 69/// Pseudo instructions for loading, storing and copying accumulator registers. 70let isPseudo = 1 in { 71 defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>; 72 defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>; 73} 74 75def COPY_AC128 : PseudoSE<(outs ACRegs128:$dst), (ins ACRegs128:$src), []>; 76 77//===----------------------------------------------------------------------===// 78// Instruction definition 79//===----------------------------------------------------------------------===// 80let DecoderNamespace = "Mips64" in { 81/// Arithmetic Instructions (ALU Immediate) 82def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>; 83def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>, 84 ADDI_FM<0x19>, IsAsCheapAsAMove; 85def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>, 86 ADDI_FM<0xc>; 87def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, 88 SLTI_FM<0xa>; 89def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, 90 SLTI_FM<0xb>; 91def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>, 92 ADDI_FM<0xd>; 93def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>, 94 ADDI_FM<0xe>; 95def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM; 96 97/// Arithmetic Instructions (3-Operand, R-Type) 98def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>; 99def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>, 100 ADD_FM<0, 0x2d>; 101def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>, 102 ADD_FM<0, 0x2f>; 103def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; 104def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; 105def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 106def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 107def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 108def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>; 109 110/// Shift Instructions 111def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>, 112 SRA_FM<0x38, 0>; 113def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>, 114 SRA_FM<0x3a, 0>; 115def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>, 116 SRA_FM<0x3b, 0>; 117def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>; 118def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>; 119def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>; 120def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>; 121def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>; 122def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>; 123} 124// Rotate Instructions 125let Predicates = [HasMips64r2, HasStdEnc], 126 DecoderNamespace = "Mips64" in { 127 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>, 128 SRA_FM<0x3a, 1>; 129 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>, 130 SRLV_FM<0x16, 1>; 131} 132 133let DecoderNamespace = "Mips64" in { 134/// Load and Store Instructions 135/// aligned 136defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>; 137defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>; 138defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>; 139defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>; 140defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>; 141defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>; 142defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>; 143defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>; 144defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>; 145defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>; 146defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>; 147 148/// load/store left/right 149defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; 150defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; 151defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; 152defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; 153 154defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; 155defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; 156defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; 157defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; 158 159/// Load-linked, Store-conditional 160let Predicates = [NotN64, HasStdEnc] in { 161 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>; 162 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>; 163} 164 165let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { 166 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>; 167 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>; 168} 169 170/// Jump and Branch Instructions 171def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>; 172def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; 173def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; 174def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; 175def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; 176def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; 177def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; 178} 179let DecoderNamespace = "Mips64" in 180def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; 181def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>; 182def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 183 184let DecoderNamespace = "Mips64" in { 185/// Multiply and Divide Instructions. 186def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 187 MULT_FM<0, 0x1c>; 188def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>, 189 MULT_FM<0, 0x1d>; 190def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult, 191 IIImul>; 192def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu, 193 IIImul>; 194def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>; 195def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>; 196def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem, 197 IIIdiv, 0>; 198def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU, 199 IIIdiv, 0>; 200 201def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; 202def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; 203def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>; 204def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>; 205 206/// Sign Ext In Register Instructions. 207def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>; 208def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>; 209 210/// Count Leading 211def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>; 212def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>; 213 214/// Double Word Swap Bytes/HalfWords 215def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>; 216def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>; 217 218def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>; 219 220} 221let DecoderNamespace = "Mips64" in { 222def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM; 223 224def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>; 225let Pattern = []<dag> in { 226 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>; 227 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>; 228} 229def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>; 230let Pattern = []<dag> in { 231 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>; 232 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>; 233} 234 235let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 236 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 237 "dsll\t$rd, $rt, 32", [], IIAlu>; 238 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), 239 "sll\t$rd, $rt, 0", [], IIAlu>; 240 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), 241 "sll\t$rd, $rt, 0", [], IIAlu>; 242} 243} 244//===----------------------------------------------------------------------===// 245// Arbitrary patterns that map to one or more instructions 246//===----------------------------------------------------------------------===// 247 248// extended loads 249let Predicates = [NotN64, HasStdEnc] in { 250 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 251 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 252 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 253 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 254} 255let Predicates = [IsN64, HasStdEnc] in { 256 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; 257 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; 258 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; 259 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; 260} 261 262// hi/lo relocs 263def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 264def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 265def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 266def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 267def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 268def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 269 270def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 271def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 272def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 273def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 274def : MipsPat<(MipsLo tglobaltlsaddr:$in), 275 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 276def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 277 278def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)), 279 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>; 280def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)), 281 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>; 282def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)), 283 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>; 284def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)), 285 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>; 286def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)), 287 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>; 288 289def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>; 290def : WrapperPat<tconstpool, DADDiu, CPU64Regs>; 291def : WrapperPat<texternalsym, DADDiu, CPU64Regs>; 292def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>; 293def : WrapperPat<tjumptable, DADDiu, CPU64Regs>; 294def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>; 295 296defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 297 ZERO_64>; 298 299// setcc patterns 300defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>; 301defm : SetlePats<CPU64Regs, SLT64, SLTu64>; 302defm : SetgtPats<CPU64Regs, SLT64, SLTu64>; 303defm : SetgePats<CPU64Regs, SLT64, SLTu64>; 304defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; 305 306// truncate 307def : MipsPat<(i32 (trunc CPU64Regs:$src)), 308 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, 309 Requires<[IsN64, HasStdEnc]>; 310 311// 32-to-64-bit extension 312def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 313def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; 314def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; 315 316// Sign extend in register 317def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)), 318 (SLL64_64 CPU64Regs:$src)>; 319 320// bswap MipsPattern 321def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; 322 323// mflo/hi patterns. 324def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)), 325 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>; 326 327//===----------------------------------------------------------------------===// 328// Instruction aliases 329//===----------------------------------------------------------------------===// 330def : InstAlias<"move $dst, $src", 331 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 332 Requires<[HasMips64]>; 333def : InstAlias<"move $dst, $src", 334 (OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>, 335 Requires<[HasMips64]>; 336def : InstAlias<"and $rs, $rt, $imm", 337 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 338 1>, 339 Requires<[HasMips64]>; 340def : InstAlias<"slt $rs, $rt, $imm", 341 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>, 342 Requires<[HasMips64]>; 343def : InstAlias<"xor $rs, $rt, $imm", 344 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 345 1>, 346 Requires<[HasMips64]>; 347def : InstAlias<"not $rt, $rs", 348 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, 349 Requires<[HasMips64]>; 350def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; 351def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>, 352 Requires<[HasMips64]>; 353def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>, 354 Requires<[HasMips64]>; 355def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>, 356 Requires<[HasMips64]>; 357def : InstAlias<"daddu $rs, $rt, $imm", 358 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 359 1>; 360def : InstAlias<"dadd $rs, $rt, $imm", 361 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 362 1>; 363def : InstAlias<"or $rs, $rt, $imm", 364 (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), 365 1>, Requires<[HasMips64]>; 366/// Move between CPU and coprocessor registers 367 368let DecoderNamespace = "Mips64" in { 369def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 370 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 371 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>; 372def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 373 (ins CPU64RegsOpnd:$rt), 374 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>; 375def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt), 376 (ins CPU64RegsOpnd:$rd, uimm16:$sel), 377 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>; 378def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel), 379 (ins CPU64RegsOpnd:$rt), 380 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>; 381} 382 383// Two operand (implicit 0 selector) versions: 384def : InstAlias<"dmfc0 $rt, $rd", 385 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 386def : InstAlias<"dmtc0 $rt, $rd", 387 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 388def : InstAlias<"dmfc2 $rt, $rd", 389 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>; 390def : InstAlias<"dmtc2 $rt, $rd", 391 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>; 392 393