1//=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64r6 instructions.
11//
12//===----------------------------------------------------------------------===//
13
14// Notes about removals/changes from MIPS32r6:
15// Reencoded: dclo, dclz
16
17//===----------------------------------------------------------------------===//
18//
19// Instruction Encodings
20//
21//===----------------------------------------------------------------------===//
22
23class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
24class DAUI_ENC    : DAUI_FM;
25class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
26class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
27class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
28class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
29class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
30class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
31class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
32class DLSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_DLSA>;
33class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
34class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
35class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011100>;
36class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011101>;
37class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
38class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011101>;
39class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
40class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
41class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
42
43//===----------------------------------------------------------------------===//
44//
45// Instruction Descriptions
46//
47//===----------------------------------------------------------------------===//
48
49class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
50  dag OutOperandList = (outs GPROpnd:$rs);
51  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
52  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
53  string Constraints = "$rs = $rt";
54}
55
56class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
57class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
58class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
59class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd>;
60class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
61class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
62class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
63class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
64class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
65class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2>;
66class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
67class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
68class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
69class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
70class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
71class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
72class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
73class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
74class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
75class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
76class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
77
78//===----------------------------------------------------------------------===//
79//
80// Instruction Definitions
81//
82//===----------------------------------------------------------------------===//
83
84def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
85def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
86def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
87def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
88def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
89def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
90def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
91def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
92def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
93def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
94def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
95def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
96def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
97def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
98def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
99def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
100def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
101def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
102def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
103let DecoderNamespace = "Mips32r6_64r6_GP64" in {
104  def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
105  def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
106}
107
108//===----------------------------------------------------------------------===//
109//
110// Instruction Aliases
111//
112//===----------------------------------------------------------------------===//
113
114def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;
115
116//===----------------------------------------------------------------------===//
117//
118// Patterns and Pseudo Instructions
119//
120//===----------------------------------------------------------------------===//
121
122// i64 selects
123def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
124              (OR64 (SELNEZ64 i64:$t, i64:$cond),
125                    (SELEQZ64 i64:$f, i64:$cond))>,
126              ISA_MIPS64R6;
127def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
128              (OR64 (SELEQZ64 i64:$t, i64:$cond),
129                    (SELNEZ64 i64:$f, i64:$cond))>,
130              ISA_MIPS64R6;
131def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
132              (OR64 (SELNEZ64 i64:$t, i64:$cond),
133                    (SELEQZ64 i64:$f, i64:$cond))>,
134              ISA_MIPS64R6;
135def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
136              (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
137                    (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
138              ISA_MIPS64R6;
139def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
140              (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
141                    (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
142              ISA_MIPS64R6;
143def : MipsPat<
144  (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
145  (OR64 (SELEQZ64 i64:$t,
146                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
147                                 sub_32)),
148        (SELNEZ64 i64:$f,
149                  (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
150                                 sub_32)))>,
151  ISA_MIPS64R6;
152def : MipsPat<
153  (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
154  (OR64 (SELEQZ64 i64:$t,
155                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
156                                 sub_32)),
157        (SELNEZ64 i64:$f,
158                  (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
159                                 sub_32)))>,
160  ISA_MIPS64R6;
161
162def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
163              (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
164def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
165              (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
166def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
167              (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
168def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
169              (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
170
171// i64 selects from an i32 comparison
172// One complicating factor here is that bits 32-63 of an i32 are undefined.
173// FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
174//        This would allow us to remove the sign-extensions here.
175def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
176              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
177                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
178              ISA_MIPS64R6;
179def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
180              (OR64 (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)),
181                    (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)))>,
182              ISA_MIPS64R6;
183def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
184              (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
185                    (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
186              ISA_MIPS64R6;
187def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
188              (OR64 (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
189                                                      immZExt16:$imm))),
190                    (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
191                                                      immZExt16:$imm))))>,
192              ISA_MIPS64R6;
193def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
194              (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
195                                                      immZExt16:$imm))),
196                    (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
197                                                      immZExt16:$imm))))>,
198              ISA_MIPS64R6;
199
200def : MipsPat<(select i32:$cond, i64:$t, immz),
201              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
202              ISA_MIPS64R6;
203def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
204              (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
205              ISA_MIPS64R6;
206def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
207              (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
208              ISA_MIPS64R6;
209def : MipsPat<(select i32:$cond, immz, i64:$f),
210              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
211              ISA_MIPS64R6;
212def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
213              (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
214              ISA_MIPS64R6;
215def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
216              (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
217              ISA_MIPS64R6;
218