MipsAsmPrinter.cpp revision 5e195a4c8d8cd4498ab7e0aa16a3b6f273daf457
1//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to GAS-format MIPS assembly language. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-asm-printer" 16#include "InstPrinter/MipsInstPrinter.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "Mips.h" 19#include "MipsAsmPrinter.h" 20#include "MipsInstrInfo.h" 21#include "MipsMCInstLower.h" 22#include "llvm/ADT/SmallString.h" 23#include "llvm/ADT/StringExtras.h" 24#include "llvm/ADT/Twine.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunctionPass.h" 28#include "llvm/CodeGen/MachineInstr.h" 29#include "llvm/CodeGen/MachineMemOperand.h" 30#include "llvm/IR/BasicBlock.h" 31#include "llvm/IR/DataLayout.h" 32#include "llvm/IR/InlineAsm.h" 33#include "llvm/IR/Instructions.h" 34#include "llvm/MC/MCAsmInfo.h" 35#include "llvm/MC/MCELFStreamer.h" 36#include "llvm/MC/MCInst.h" 37#include "llvm/MC/MCSymbol.h" 38#include "llvm/Support/ELF.h" 39#include "llvm/Support/TargetRegistry.h" 40#include "llvm/Support/raw_ostream.h" 41#include "llvm/Target/Mangler.h" 42#include "llvm/Target/TargetLoweringObjectFile.h" 43#include "llvm/Target/TargetOptions.h" 44 45using namespace llvm; 46 47bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { 48 // Initialize TargetLoweringObjectFile. 49 if (Subtarget->allowMixed16_32()) 50 const_cast<TargetLoweringObjectFile&>(getObjFileLowering()) 51 .Initialize(OutContext, TM); 52 MipsFI = MF.getInfo<MipsFunctionInfo>(); 53 AsmPrinter::runOnMachineFunction(MF); 54 return true; 55} 56 57bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { 58 MCOp = MCInstLowering.LowerOperand(MO); 59 return MCOp.isValid(); 60} 61 62#include "MipsGenMCPseudoLowering.inc" 63 64void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { 65 if (MI->isDebugValue()) { 66 SmallString<128> Str; 67 raw_svector_ostream OS(Str); 68 69 PrintDebugValueComment(MI, OS); 70 return; 71 } 72 73 MachineBasicBlock::const_instr_iterator I = MI; 74 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 75 76 do { 77 // Do any auto-generated pseudo lowerings. 78 if (emitPseudoExpansionLowering(OutStreamer, &*I)) 79 continue; 80 81 // The inMips16Mode() test is not permanent. 82 // Some instructions are marked as pseudo right now which 83 // would make the test fail for the wrong reason but 84 // that will be fixed soon. We need this here because we are 85 // removing another test for this situation downstream in the 86 // callchain. 87 // 88 if (I->isPseudo() && !Subtarget->inMips16Mode()) 89 llvm_unreachable("Pseudo opcode found in EmitInstruction()"); 90 91 MCInst TmpInst0; 92 MCInstLowering.Lower(I, TmpInst0); 93 OutStreamer.EmitInstruction(TmpInst0); 94 } while ((++I != E) && I->isInsideBundle()); // Delay slot check 95} 96 97//===----------------------------------------------------------------------===// 98// 99// Mips Asm Directives 100// 101// -- Frame directive "frame Stackpointer, Stacksize, RARegister" 102// Describe the stack frame. 103// 104// -- Mask directives "(f)mask bitmask, offset" 105// Tells the assembler which registers are saved and where. 106// bitmask - contain a little endian bitset indicating which registers are 107// saved on function prologue (e.g. with a 0x80000000 mask, the 108// assembler knows the register 31 (RA) is saved at prologue. 109// offset - the position before stack pointer subtraction indicating where 110// the first saved register on prologue is located. (e.g. with a 111// 112// Consider the following function prologue: 113// 114// .frame $fp,48,$ra 115// .mask 0xc0000000,-8 116// addiu $sp, $sp, -48 117// sw $ra, 40($sp) 118// sw $fp, 36($sp) 119// 120// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and 121// 30 (FP) are saved at prologue. As the save order on prologue is from 122// left to right, RA is saved first. A -8 offset means that after the 123// stack pointer subtration, the first register in the mask (RA) will be 124// saved at address 48-8=40. 125// 126//===----------------------------------------------------------------------===// 127 128//===----------------------------------------------------------------------===// 129// Mask directives 130//===----------------------------------------------------------------------===// 131 132// Create a bitmask with all callee saved registers for CPU or Floating Point 133// registers. For CPU registers consider RA, GP and FP for saving if necessary. 134void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { 135 // CPU and FPU Saved Registers Bitmasks 136 unsigned CPUBitmask = 0, FPUBitmask = 0; 137 int CPUTopSavedRegOff, FPUTopSavedRegOff; 138 139 // Set the CPU and FPU Bitmasks 140 const MachineFrameInfo *MFI = MF->getFrameInfo(); 141 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 142 // size of stack area to which FP callee-saved regs are saved. 143 unsigned CPURegSize = Mips::GPR32RegClass.getSize(); 144 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize(); 145 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize(); 146 bool HasAFGR64Reg = false; 147 unsigned CSFPRegsSize = 0; 148 unsigned i, e = CSI.size(); 149 150 // Set FPU Bitmask. 151 for (i = 0; i != e; ++i) { 152 unsigned Reg = CSI[i].getReg(); 153 if (Mips::GPR32RegClass.contains(Reg)) 154 break; 155 156 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); 157 if (Mips::AFGR64RegClass.contains(Reg)) { 158 FPUBitmask |= (3 << RegNum); 159 CSFPRegsSize += AFGR64RegSize; 160 HasAFGR64Reg = true; 161 continue; 162 } 163 164 FPUBitmask |= (1 << RegNum); 165 CSFPRegsSize += FGR32RegSize; 166 } 167 168 // Set CPU Bitmask. 169 for (; i != e; ++i) { 170 unsigned Reg = CSI[i].getReg(); 171 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); 172 CPUBitmask |= (1 << RegNum); 173 } 174 175 // FP Regs are saved right below where the virtual frame pointer points to. 176 FPUTopSavedRegOff = FPUBitmask ? 177 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0; 178 179 // CPU Regs are saved below FP Regs. 180 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0; 181 182 // Print CPUBitmask 183 O << "\t.mask \t"; printHex32(CPUBitmask, O); 184 O << ',' << CPUTopSavedRegOff << '\n'; 185 186 // Print FPUBitmask 187 O << "\t.fmask\t"; printHex32(FPUBitmask, O); 188 O << "," << FPUTopSavedRegOff << '\n'; 189} 190 191// Print a 32 bit hex number with all numbers. 192void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) { 193 O << "0x"; 194 for (int i = 7; i >= 0; i--) 195 O.write_hex((Value & (0xF << (i*4))) >> (i*4)); 196} 197 198//===----------------------------------------------------------------------===// 199// Frame and Set directives 200//===----------------------------------------------------------------------===// 201 202/// Frame Directive 203void MipsAsmPrinter::emitFrameDirective() { 204 const TargetRegisterInfo &RI = *TM.getRegisterInfo(); 205 206 unsigned stackReg = RI.getFrameRegister(*MF); 207 unsigned returnReg = RI.getRARegister(); 208 unsigned stackSize = MF->getFrameInfo()->getStackSize(); 209 210 if (OutStreamer.hasRawTextSupport()) 211 OutStreamer.EmitRawText("\t.frame\t$" + 212 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() + 213 "," + Twine(stackSize) + ",$" + 214 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower()); 215} 216 217/// Emit Set directives. 218const char *MipsAsmPrinter::getCurrentABIString() const { 219 switch (Subtarget->getTargetABI()) { 220 case MipsSubtarget::O32: return "abi32"; 221 case MipsSubtarget::N32: return "abiN32"; 222 case MipsSubtarget::N64: return "abi64"; 223 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 224 default: llvm_unreachable("Unknown Mips ABI"); 225 } 226} 227 228void MipsAsmPrinter::EmitFunctionEntryLabel() { 229 if (OutStreamer.hasRawTextSupport()) { 230 if (Subtarget->inMips16Mode()) 231 OutStreamer.EmitRawText(StringRef("\t.set\tmips16")); 232 else 233 OutStreamer.EmitRawText(StringRef("\t.set\tnomips16")); 234 // leave out until FSF available gas has micromips changes 235 // OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips")); 236 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); 237 } 238 239 if (Subtarget->inMicroMipsMode()) 240 OutStreamer.emitMipsHackSTOCG(CurrentFnSym, 241 (unsigned)ELF::STO_MIPS_MICROMIPS); 242 OutStreamer.EmitLabel(CurrentFnSym); 243} 244 245/// EmitFunctionBodyStart - Targets can override this to emit stuff before 246/// the first basic block in the function. 247void MipsAsmPrinter::EmitFunctionBodyStart() { 248 MCInstLowering.Initialize(Mang, &MF->getContext()); 249 250 bool IsNakedFunction = 251 MF->getFunction()-> 252 getAttributes().hasAttribute(AttributeSet::FunctionIndex, 253 Attribute::Naked); 254 if (!IsNakedFunction) 255 emitFrameDirective(); 256 257 if (OutStreamer.hasRawTextSupport()) { 258 SmallString<128> Str; 259 raw_svector_ostream OS(Str); 260 if (!IsNakedFunction) 261 printSavedRegsBitmask(OS); 262 OutStreamer.EmitRawText(OS.str()); 263 if (!Subtarget->inMips16Mode()) { 264 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder")); 265 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro")); 266 OutStreamer.EmitRawText(StringRef("\t.set\tnoat")); 267 } 268 } 269} 270 271/// EmitFunctionBodyEnd - Targets can override this to emit stuff after 272/// the last basic block in the function. 273void MipsAsmPrinter::EmitFunctionBodyEnd() { 274 // There are instruction for this macros, but they must 275 // always be at the function end, and we can't emit and 276 // break with BB logic. 277 if (OutStreamer.hasRawTextSupport()) { 278 if (!Subtarget->inMips16Mode()) { 279 OutStreamer.EmitRawText(StringRef("\t.set\tat")); 280 OutStreamer.EmitRawText(StringRef("\t.set\tmacro")); 281 OutStreamer.EmitRawText(StringRef("\t.set\treorder")); 282 } 283 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); 284 } 285} 286 287/// isBlockOnlyReachableByFallthough - Return true if the basic block has 288/// exactly one predecessor and the control transfer mechanism between 289/// the predecessor and this block is a fall-through. 290bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* 291 MBB) const { 292 // The predecessor has to be immediately before this block. 293 const MachineBasicBlock *Pred = *MBB->pred_begin(); 294 295 // If the predecessor is a switch statement, assume a jump table 296 // implementation, so it is not a fall through. 297 if (const BasicBlock *bb = Pred->getBasicBlock()) 298 if (isa<SwitchInst>(bb->getTerminator())) 299 return false; 300 301 // If this is a landing pad, it isn't a fall through. If it has no preds, 302 // then nothing falls through to it. 303 if (MBB->isLandingPad() || MBB->pred_empty()) 304 return false; 305 306 // If there isn't exactly one predecessor, it can't be a fall through. 307 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI; 308 ++PI2; 309 310 if (PI2 != MBB->pred_end()) 311 return false; 312 313 // The predecessor has to be immediately before this block. 314 if (!Pred->isLayoutSuccessor(MBB)) 315 return false; 316 317 // If the block is completely empty, then it definitely does fall through. 318 if (Pred->empty()) 319 return true; 320 321 // Otherwise, check the last instruction. 322 // Check if the last terminator is an unconditional branch. 323 MachineBasicBlock::const_iterator I = Pred->end(); 324 while (I != Pred->begin() && !(--I)->isTerminator()) ; 325 326 return !I->isBarrier(); 327} 328 329// Print out an operand for an inline asm expression. 330bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 331 unsigned AsmVariant,const char *ExtraCode, 332 raw_ostream &O) { 333 // Does this asm operand have a single letter operand modifier? 334 if (ExtraCode && ExtraCode[0]) { 335 if (ExtraCode[1] != 0) return true; // Unknown modifier. 336 337 const MachineOperand &MO = MI->getOperand(OpNum); 338 switch (ExtraCode[0]) { 339 default: 340 // See if this is a generic print operand 341 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O); 342 case 'X': // hex const int 343 if ((MO.getType()) != MachineOperand::MO_Immediate) 344 return true; 345 O << "0x" << StringRef(utohexstr(MO.getImm())).lower(); 346 return false; 347 case 'x': // hex const int (low 16 bits) 348 if ((MO.getType()) != MachineOperand::MO_Immediate) 349 return true; 350 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower(); 351 return false; 352 case 'd': // decimal const int 353 if ((MO.getType()) != MachineOperand::MO_Immediate) 354 return true; 355 O << MO.getImm(); 356 return false; 357 case 'm': // decimal const int minus 1 358 if ((MO.getType()) != MachineOperand::MO_Immediate) 359 return true; 360 O << MO.getImm() - 1; 361 return false; 362 case 'z': { 363 // $0 if zero, regular printing otherwise 364 if (MO.getType() != MachineOperand::MO_Immediate) 365 return true; 366 int64_t Val = MO.getImm(); 367 if (Val) 368 O << Val; 369 else 370 O << "$0"; 371 return false; 372 } 373 case 'D': // Second part of a double word register operand 374 case 'L': // Low order register of a double word register operand 375 case 'M': // High order register of a double word register operand 376 { 377 if (OpNum == 0) 378 return true; 379 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); 380 if (!FlagsOP.isImm()) 381 return true; 382 unsigned Flags = FlagsOP.getImm(); 383 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 384 // Number of registers represented by this operand. We are looking 385 // for 2 for 32 bit mode and 1 for 64 bit mode. 386 if (NumVals != 2) { 387 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { 388 unsigned Reg = MO.getReg(); 389 O << '$' << MipsInstPrinter::getRegisterName(Reg); 390 return false; 391 } 392 return true; 393 } 394 395 unsigned RegOp = OpNum; 396 if (!Subtarget->isGP64bit()){ 397 // Endianess reverses which register holds the high or low value 398 // between M and L. 399 switch(ExtraCode[0]) { 400 case 'M': 401 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; 402 break; 403 case 'L': 404 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; 405 break; 406 case 'D': // Always the second part 407 RegOp = OpNum + 1; 408 } 409 if (RegOp >= MI->getNumOperands()) 410 return true; 411 const MachineOperand &MO = MI->getOperand(RegOp); 412 if (!MO.isReg()) 413 return true; 414 unsigned Reg = MO.getReg(); 415 O << '$' << MipsInstPrinter::getRegisterName(Reg); 416 return false; 417 } 418 } 419 } 420 } 421 422 printOperand(MI, OpNum, O); 423 return false; 424} 425 426bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 427 unsigned OpNum, unsigned AsmVariant, 428 const char *ExtraCode, 429 raw_ostream &O) { 430 int Offset = 0; 431 // Currently we are expecting either no ExtraCode or 'D' 432 if (ExtraCode) { 433 if (ExtraCode[0] == 'D') 434 Offset = 4; 435 else 436 return true; // Unknown modifier. 437 } 438 439 const MachineOperand &MO = MI->getOperand(OpNum); 440 assert(MO.isReg() && "unexpected inline asm memory operand"); 441 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")"; 442 443 return false; 444} 445 446void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, 447 raw_ostream &O) { 448 const MachineOperand &MO = MI->getOperand(opNum); 449 bool closeP = false; 450 451 if (MO.getTargetFlags()) 452 closeP = true; 453 454 switch(MO.getTargetFlags()) { 455 case MipsII::MO_GPREL: O << "%gp_rel("; break; 456 case MipsII::MO_GOT_CALL: O << "%call16("; break; 457 case MipsII::MO_GOT: O << "%got("; break; 458 case MipsII::MO_ABS_HI: O << "%hi("; break; 459 case MipsII::MO_ABS_LO: O << "%lo("; break; 460 case MipsII::MO_TLSGD: O << "%tlsgd("; break; 461 case MipsII::MO_GOTTPREL: O << "%gottprel("; break; 462 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break; 463 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break; 464 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break; 465 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break; 466 case MipsII::MO_GOT_DISP: O << "%got_disp("; break; 467 case MipsII::MO_GOT_PAGE: O << "%got_page("; break; 468 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break; 469 } 470 471 switch (MO.getType()) { 472 case MachineOperand::MO_Register: 473 O << '$' 474 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower(); 475 break; 476 477 case MachineOperand::MO_Immediate: 478 O << MO.getImm(); 479 break; 480 481 case MachineOperand::MO_MachineBasicBlock: 482 O << *MO.getMBB()->getSymbol(); 483 return; 484 485 case MachineOperand::MO_GlobalAddress: 486 O << *Mang->getSymbol(MO.getGlobal()); 487 break; 488 489 case MachineOperand::MO_BlockAddress: { 490 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); 491 O << BA->getName(); 492 break; 493 } 494 495 case MachineOperand::MO_ExternalSymbol: 496 O << *GetExternalSymbolSymbol(MO.getSymbolName()); 497 break; 498 499 case MachineOperand::MO_JumpTableIndex: 500 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() 501 << '_' << MO.getIndex(); 502 break; 503 504 case MachineOperand::MO_ConstantPoolIndex: 505 O << MAI->getPrivateGlobalPrefix() << "CPI" 506 << getFunctionNumber() << "_" << MO.getIndex(); 507 if (MO.getOffset()) 508 O << "+" << MO.getOffset(); 509 break; 510 511 default: 512 llvm_unreachable("<unknown operand type>"); 513 } 514 515 if (closeP) O << ")"; 516} 517 518void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, 519 raw_ostream &O) { 520 const MachineOperand &MO = MI->getOperand(opNum); 521 if (MO.isImm()) 522 O << (unsigned short int)MO.getImm(); 523 else 524 printOperand(MI, opNum, O); 525} 526 527void MipsAsmPrinter:: 528printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { 529 // Load/Store memory operands -- imm($reg) 530 // If PIC target the target is loaded as the 531 // pattern lw $25,%call16($28) 532 printOperand(MI, opNum+1, O); 533 O << "("; 534 printOperand(MI, opNum, O); 535 O << ")"; 536} 537 538void MipsAsmPrinter:: 539printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) { 540 // when using stack locations for not load/store instructions 541 // print the same way as all normal 3 operand instructions. 542 printOperand(MI, opNum, O); 543 O << ", "; 544 printOperand(MI, opNum+1, O); 545 return; 546} 547 548void MipsAsmPrinter:: 549printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, 550 const char *Modifier) { 551 const MachineOperand &MO = MI->getOperand(opNum); 552 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); 553} 554 555void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { 556 // FIXME: Use SwitchSection. 557 558 // TODO: Need to add -mabicalls and -mno-abicalls flags. 559 // Currently we assume that -mabicalls is the default. 560 if (OutStreamer.hasRawTextSupport()) { 561 OutStreamer.EmitRawText(StringRef("\t.abicalls")); 562 Reloc::Model RM = Subtarget->getRelocationModel(); 563 if (RM == Reloc::Static && !Subtarget->hasMips64()) 564 OutStreamer.EmitRawText(StringRef("\t.option\tpic0")); 565 } 566 567 // Tell the assembler which ABI we are using 568 if (OutStreamer.hasRawTextSupport()) 569 OutStreamer.EmitRawText("\t.section .mdebug." + 570 Twine(getCurrentABIString())); 571 572 // TODO: handle O64 ABI 573 if (OutStreamer.hasRawTextSupport()) { 574 if (Subtarget->isABI_EABI()) { 575 if (Subtarget->isGP32bit()) 576 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32")); 577 else 578 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64")); 579 } 580 } 581 582 // return to previous section 583 if (OutStreamer.hasRawTextSupport()) 584 OutStreamer.EmitRawText(StringRef("\t.previous")); 585 586} 587 588static void 589emitELFHeaderFlagsCG(MCStreamer &Streamer, const MipsSubtarget &Subtarget) { 590 // Update e_header flags 591 unsigned EFlags = 0; 592 593 // TODO: Need to add -mabicalls and -mno-abicalls flags. 594 // Currently we assume that -mabicalls is the default. 595 EFlags |= ELF::EF_MIPS_CPIC; 596 597 if (Subtarget.inMips16Mode()) 598 EFlags |= ELF::EF_MIPS_ARCH_ASE_M16; 599 else 600 EFlags |= ELF::EF_MIPS_NOREORDER; 601 602 // Architecture 603 if (Subtarget.hasMips64r2()) 604 EFlags |= ELF::EF_MIPS_ARCH_64R2; 605 else if (Subtarget.hasMips64()) 606 EFlags |= ELF::EF_MIPS_ARCH_64; 607 else if (Subtarget.hasMips32r2()) 608 EFlags |= ELF::EF_MIPS_ARCH_32R2; 609 else 610 EFlags |= ELF::EF_MIPS_ARCH_32; 611 612 if (Subtarget.inMicroMipsMode()) 613 EFlags |= ELF::EF_MIPS_MICROMIPS; 614 615 // ABI 616 if (Subtarget.isABI_O32()) 617 EFlags |= ELF::EF_MIPS_ABI_O32; 618 619 // Relocation Model 620 Reloc::Model RM = Subtarget.getRelocationModel(); 621 if (RM == Reloc::PIC_ || RM == Reloc::Default) 622 EFlags |= ELF::EF_MIPS_PIC; 623 else if (RM == Reloc::Static) 624 ; // Do nothing for Reloc::Static 625 else 626 llvm_unreachable("Unsupported relocation model for e_flags"); 627 628 Streamer.emitMipsHackELFFlags(EFlags); 629} 630 631void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) { 632 // Emit Mips ELF register info 633 Subtarget->getMReginfo().emitMipsReginfoSectionCG( 634 OutStreamer, getObjFileLowering(), *Subtarget); 635 emitELFHeaderFlagsCG(OutStreamer, *Subtarget); 636} 637 638void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 639 raw_ostream &OS) { 640 // TODO: implement 641} 642 643// Force static initialization. 644extern "C" void LLVMInitializeMipsAsmPrinter() { 645 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget); 646 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget); 647 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target); 648 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget); 649} 650