MipsAsmPrinter.cpp revision a87a147ee7bb9adb4caea631ff0ba7e66bb9b0b5
1//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to GAS-format MIPS assembly language. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "mips-asm-printer" 16#include "InstPrinter/MipsInstPrinter.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "Mips.h" 19#include "MipsAsmPrinter.h" 20#include "MipsInstrInfo.h" 21#include "MipsMCInstLower.h" 22#include "MipsTargetStreamer.h" 23#include "llvm/ADT/SmallString.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/Twine.h" 26#include "llvm/CodeGen/MachineConstantPool.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineInstr.h" 30#include "llvm/CodeGen/MachineMemOperand.h" 31#include "llvm/IR/BasicBlock.h" 32#include "llvm/IR/DataLayout.h" 33#include "llvm/IR/InlineAsm.h" 34#include "llvm/IR/Instructions.h" 35#include "llvm/MC/MCAsmInfo.h" 36#include "llvm/MC/MCELFStreamer.h" 37#include "llvm/MC/MCInst.h" 38#include "llvm/MC/MCSymbol.h" 39#include "llvm/Support/ELF.h" 40#include "llvm/Support/TargetRegistry.h" 41#include "llvm/Support/raw_ostream.h" 42#include "llvm/Target/Mangler.h" 43#include "llvm/Target/TargetLoweringObjectFile.h" 44#include "llvm/Target/TargetOptions.h" 45 46using namespace llvm; 47 48MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() { 49 return static_cast<MipsTargetStreamer &>(OutStreamer.getTargetStreamer()); 50} 51 52bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { 53 // Initialize TargetLoweringObjectFile. 54 if (Subtarget->allowMixed16_32()) 55 const_cast<TargetLoweringObjectFile&>(getObjFileLowering()) 56 .Initialize(OutContext, TM); 57 MipsFI = MF.getInfo<MipsFunctionInfo>(); 58 MCP = MF.getConstantPool(); 59 AsmPrinter::runOnMachineFunction(MF); 60 return true; 61} 62 63bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { 64 MCOp = MCInstLowering.LowerOperand(MO); 65 return MCOp.isValid(); 66} 67 68#include "MipsGenMCPseudoLowering.inc" 69 70void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { 71 if (MI->isDebugValue()) { 72 SmallString<128> Str; 73 raw_svector_ostream OS(Str); 74 75 PrintDebugValueComment(MI, OS); 76 return; 77 } 78 79 // If we just ended a constant pool, mark it as such. 80 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) { 81 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 82 InConstantPool = false; 83 } 84 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) { 85 // CONSTPOOL_ENTRY - This instruction represents a floating 86 //constant pool in the function. The first operand is the ID# 87 // for this instruction, the second is the index into the 88 // MachineConstantPool that this is, the third is the size in 89 // bytes of this constant pool entry. 90 // The required alignment is specified on the basic block holding this MI. 91 // 92 unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); 93 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); 94 95 // If this is the first entry of the pool, mark it. 96 if (!InConstantPool) { 97 OutStreamer.EmitDataRegion(MCDR_DataRegion); 98 InConstantPool = true; 99 } 100 101 OutStreamer.EmitLabel(GetCPISymbol(LabelId)); 102 103 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; 104 if (MCPE.isMachineConstantPoolEntry()) 105 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); 106 else 107 EmitGlobalConstant(MCPE.Val.ConstVal); 108 return; 109 } 110 111 112 MachineBasicBlock::const_instr_iterator I = MI; 113 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); 114 115 do { 116 // Do any auto-generated pseudo lowerings. 117 if (emitPseudoExpansionLowering(OutStreamer, &*I)) 118 continue; 119 120 // The inMips16Mode() test is not permanent. 121 // Some instructions are marked as pseudo right now which 122 // would make the test fail for the wrong reason but 123 // that will be fixed soon. We need this here because we are 124 // removing another test for this situation downstream in the 125 // callchain. 126 // 127 if (I->isPseudo() && !Subtarget->inMips16Mode()) 128 llvm_unreachable("Pseudo opcode found in EmitInstruction()"); 129 130 MCInst TmpInst0; 131 MCInstLowering.Lower(I, TmpInst0); 132 OutStreamer.EmitInstruction(TmpInst0); 133 } while ((++I != E) && I->isInsideBundle()); // Delay slot check 134} 135 136//===----------------------------------------------------------------------===// 137// 138// Mips Asm Directives 139// 140// -- Frame directive "frame Stackpointer, Stacksize, RARegister" 141// Describe the stack frame. 142// 143// -- Mask directives "(f)mask bitmask, offset" 144// Tells the assembler which registers are saved and where. 145// bitmask - contain a little endian bitset indicating which registers are 146// saved on function prologue (e.g. with a 0x80000000 mask, the 147// assembler knows the register 31 (RA) is saved at prologue. 148// offset - the position before stack pointer subtraction indicating where 149// the first saved register on prologue is located. (e.g. with a 150// 151// Consider the following function prologue: 152// 153// .frame $fp,48,$ra 154// .mask 0xc0000000,-8 155// addiu $sp, $sp, -48 156// sw $ra, 40($sp) 157// sw $fp, 36($sp) 158// 159// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and 160// 30 (FP) are saved at prologue. As the save order on prologue is from 161// left to right, RA is saved first. A -8 offset means that after the 162// stack pointer subtration, the first register in the mask (RA) will be 163// saved at address 48-8=40. 164// 165//===----------------------------------------------------------------------===// 166 167//===----------------------------------------------------------------------===// 168// Mask directives 169//===----------------------------------------------------------------------===// 170 171// Create a bitmask with all callee saved registers for CPU or Floating Point 172// registers. For CPU registers consider RA, GP and FP for saving if necessary. 173void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { 174 // CPU and FPU Saved Registers Bitmasks 175 unsigned CPUBitmask = 0, FPUBitmask = 0; 176 int CPUTopSavedRegOff, FPUTopSavedRegOff; 177 178 // Set the CPU and FPU Bitmasks 179 const MachineFrameInfo *MFI = MF->getFrameInfo(); 180 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 181 // size of stack area to which FP callee-saved regs are saved. 182 unsigned CPURegSize = Mips::GPR32RegClass.getSize(); 183 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize(); 184 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize(); 185 bool HasAFGR64Reg = false; 186 unsigned CSFPRegsSize = 0; 187 unsigned i, e = CSI.size(); 188 189 // Set FPU Bitmask. 190 for (i = 0; i != e; ++i) { 191 unsigned Reg = CSI[i].getReg(); 192 if (Mips::GPR32RegClass.contains(Reg)) 193 break; 194 195 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); 196 if (Mips::AFGR64RegClass.contains(Reg)) { 197 FPUBitmask |= (3 << RegNum); 198 CSFPRegsSize += AFGR64RegSize; 199 HasAFGR64Reg = true; 200 continue; 201 } 202 203 FPUBitmask |= (1 << RegNum); 204 CSFPRegsSize += FGR32RegSize; 205 } 206 207 // Set CPU Bitmask. 208 for (; i != e; ++i) { 209 unsigned Reg = CSI[i].getReg(); 210 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); 211 CPUBitmask |= (1 << RegNum); 212 } 213 214 // FP Regs are saved right below where the virtual frame pointer points to. 215 FPUTopSavedRegOff = FPUBitmask ? 216 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0; 217 218 // CPU Regs are saved below FP Regs. 219 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0; 220 221 // Print CPUBitmask 222 O << "\t.mask \t"; printHex32(CPUBitmask, O); 223 O << ',' << CPUTopSavedRegOff << '\n'; 224 225 // Print FPUBitmask 226 O << "\t.fmask\t"; printHex32(FPUBitmask, O); 227 O << "," << FPUTopSavedRegOff << '\n'; 228} 229 230// Print a 32 bit hex number with all numbers. 231void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) { 232 O << "0x"; 233 for (int i = 7; i >= 0; i--) 234 O.write_hex((Value & (0xF << (i*4))) >> (i*4)); 235} 236 237//===----------------------------------------------------------------------===// 238// Frame and Set directives 239//===----------------------------------------------------------------------===// 240 241/// Frame Directive 242void MipsAsmPrinter::emitFrameDirective() { 243 const TargetRegisterInfo &RI = *TM.getRegisterInfo(); 244 245 unsigned stackReg = RI.getFrameRegister(*MF); 246 unsigned returnReg = RI.getRARegister(); 247 unsigned stackSize = MF->getFrameInfo()->getStackSize(); 248 249 if (OutStreamer.hasRawTextSupport()) 250 OutStreamer.EmitRawText("\t.frame\t$" + 251 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() + 252 "," + Twine(stackSize) + ",$" + 253 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower()); 254} 255 256/// Emit Set directives. 257const char *MipsAsmPrinter::getCurrentABIString() const { 258 switch (Subtarget->getTargetABI()) { 259 case MipsSubtarget::O32: return "abi32"; 260 case MipsSubtarget::N32: return "abiN32"; 261 case MipsSubtarget::N64: return "abi64"; 262 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 263 default: llvm_unreachable("Unknown Mips ABI"); 264 } 265} 266 267void MipsAsmPrinter::EmitFunctionEntryLabel() { 268 if (OutStreamer.hasRawTextSupport()) { 269 if (Subtarget->inMips16Mode()) 270 OutStreamer.EmitRawText(StringRef("\t.set\tmips16")); 271 else 272 OutStreamer.EmitRawText(StringRef("\t.set\tnomips16")); 273 // leave out until FSF available gas has micromips changes 274 // OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips")); 275 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); 276 } 277 278 if (Subtarget->inMicroMipsMode()) 279 getTargetStreamer().emitMipsHackSTOCG(CurrentFnSym, 280 (unsigned)ELF::STO_MIPS_MICROMIPS); 281 OutStreamer.EmitLabel(CurrentFnSym); 282} 283 284/// EmitFunctionBodyStart - Targets can override this to emit stuff before 285/// the first basic block in the function. 286void MipsAsmPrinter::EmitFunctionBodyStart() { 287 MCInstLowering.Initialize(&MF->getContext()); 288 289 bool IsNakedFunction = 290 MF->getFunction()-> 291 getAttributes().hasAttribute(AttributeSet::FunctionIndex, 292 Attribute::Naked); 293 if (!IsNakedFunction) 294 emitFrameDirective(); 295 296 if (OutStreamer.hasRawTextSupport()) { 297 SmallString<128> Str; 298 raw_svector_ostream OS(Str); 299 if (!IsNakedFunction) 300 printSavedRegsBitmask(OS); 301 OutStreamer.EmitRawText(OS.str()); 302 if (!Subtarget->inMips16Mode()) { 303 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder")); 304 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro")); 305 OutStreamer.EmitRawText(StringRef("\t.set\tnoat")); 306 } 307 } 308} 309 310/// EmitFunctionBodyEnd - Targets can override this to emit stuff after 311/// the last basic block in the function. 312void MipsAsmPrinter::EmitFunctionBodyEnd() { 313 // There are instruction for this macros, but they must 314 // always be at the function end, and we can't emit and 315 // break with BB logic. 316 if (OutStreamer.hasRawTextSupport()) { 317 if (!Subtarget->inMips16Mode()) { 318 OutStreamer.EmitRawText(StringRef("\t.set\tat")); 319 OutStreamer.EmitRawText(StringRef("\t.set\tmacro")); 320 OutStreamer.EmitRawText(StringRef("\t.set\treorder")); 321 } 322 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); 323 } 324 // Make sure to terminate any constant pools that were at the end 325 // of the function. 326 if (!InConstantPool) 327 return; 328 InConstantPool = false; 329 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd); 330} 331 332/// isBlockOnlyReachableByFallthough - Return true if the basic block has 333/// exactly one predecessor and the control transfer mechanism between 334/// the predecessor and this block is a fall-through. 335bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* 336 MBB) const { 337 // The predecessor has to be immediately before this block. 338 const MachineBasicBlock *Pred = *MBB->pred_begin(); 339 340 // If the predecessor is a switch statement, assume a jump table 341 // implementation, so it is not a fall through. 342 if (const BasicBlock *bb = Pred->getBasicBlock()) 343 if (isa<SwitchInst>(bb->getTerminator())) 344 return false; 345 346 // If this is a landing pad, it isn't a fall through. If it has no preds, 347 // then nothing falls through to it. 348 if (MBB->isLandingPad() || MBB->pred_empty()) 349 return false; 350 351 // If there isn't exactly one predecessor, it can't be a fall through. 352 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI; 353 ++PI2; 354 355 if (PI2 != MBB->pred_end()) 356 return false; 357 358 // The predecessor has to be immediately before this block. 359 if (!Pred->isLayoutSuccessor(MBB)) 360 return false; 361 362 // If the block is completely empty, then it definitely does fall through. 363 if (Pred->empty()) 364 return true; 365 366 // Otherwise, check the last instruction. 367 // Check if the last terminator is an unconditional branch. 368 MachineBasicBlock::const_iterator I = Pred->end(); 369 while (I != Pred->begin() && !(--I)->isTerminator()) ; 370 371 return !I->isBarrier(); 372} 373 374// Print out an operand for an inline asm expression. 375bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, 376 unsigned AsmVariant,const char *ExtraCode, 377 raw_ostream &O) { 378 // Does this asm operand have a single letter operand modifier? 379 if (ExtraCode && ExtraCode[0]) { 380 if (ExtraCode[1] != 0) return true; // Unknown modifier. 381 382 const MachineOperand &MO = MI->getOperand(OpNum); 383 switch (ExtraCode[0]) { 384 default: 385 // See if this is a generic print operand 386 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O); 387 case 'X': // hex const int 388 if ((MO.getType()) != MachineOperand::MO_Immediate) 389 return true; 390 O << "0x" << StringRef(utohexstr(MO.getImm())).lower(); 391 return false; 392 case 'x': // hex const int (low 16 bits) 393 if ((MO.getType()) != MachineOperand::MO_Immediate) 394 return true; 395 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower(); 396 return false; 397 case 'd': // decimal const int 398 if ((MO.getType()) != MachineOperand::MO_Immediate) 399 return true; 400 O << MO.getImm(); 401 return false; 402 case 'm': // decimal const int minus 1 403 if ((MO.getType()) != MachineOperand::MO_Immediate) 404 return true; 405 O << MO.getImm() - 1; 406 return false; 407 case 'z': { 408 // $0 if zero, regular printing otherwise 409 if (MO.getType() != MachineOperand::MO_Immediate) 410 return true; 411 int64_t Val = MO.getImm(); 412 if (Val) 413 O << Val; 414 else 415 O << "$0"; 416 return false; 417 } 418 case 'D': // Second part of a double word register operand 419 case 'L': // Low order register of a double word register operand 420 case 'M': // High order register of a double word register operand 421 { 422 if (OpNum == 0) 423 return true; 424 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); 425 if (!FlagsOP.isImm()) 426 return true; 427 unsigned Flags = FlagsOP.getImm(); 428 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 429 // Number of registers represented by this operand. We are looking 430 // for 2 for 32 bit mode and 1 for 64 bit mode. 431 if (NumVals != 2) { 432 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { 433 unsigned Reg = MO.getReg(); 434 O << '$' << MipsInstPrinter::getRegisterName(Reg); 435 return false; 436 } 437 return true; 438 } 439 440 unsigned RegOp = OpNum; 441 if (!Subtarget->isGP64bit()){ 442 // Endianess reverses which register holds the high or low value 443 // between M and L. 444 switch(ExtraCode[0]) { 445 case 'M': 446 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; 447 break; 448 case 'L': 449 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; 450 break; 451 case 'D': // Always the second part 452 RegOp = OpNum + 1; 453 } 454 if (RegOp >= MI->getNumOperands()) 455 return true; 456 const MachineOperand &MO = MI->getOperand(RegOp); 457 if (!MO.isReg()) 458 return true; 459 unsigned Reg = MO.getReg(); 460 O << '$' << MipsInstPrinter::getRegisterName(Reg); 461 return false; 462 } 463 } 464 case 'w': 465 // Print MSA registers for the 'f' constraint 466 // In LLVM, the 'w' modifier doesn't need to do anything. 467 // We can just call printOperand as normal. 468 break; 469 } 470 } 471 472 printOperand(MI, OpNum, O); 473 return false; 474} 475 476bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 477 unsigned OpNum, unsigned AsmVariant, 478 const char *ExtraCode, 479 raw_ostream &O) { 480 int Offset = 0; 481 // Currently we are expecting either no ExtraCode or 'D' 482 if (ExtraCode) { 483 if (ExtraCode[0] == 'D') 484 Offset = 4; 485 else 486 return true; // Unknown modifier. 487 } 488 489 const MachineOperand &MO = MI->getOperand(OpNum); 490 assert(MO.isReg() && "unexpected inline asm memory operand"); 491 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")"; 492 493 return false; 494} 495 496void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, 497 raw_ostream &O) { 498 const MachineOperand &MO = MI->getOperand(opNum); 499 bool closeP = false; 500 501 if (MO.getTargetFlags()) 502 closeP = true; 503 504 switch(MO.getTargetFlags()) { 505 case MipsII::MO_GPREL: O << "%gp_rel("; break; 506 case MipsII::MO_GOT_CALL: O << "%call16("; break; 507 case MipsII::MO_GOT: O << "%got("; break; 508 case MipsII::MO_ABS_HI: O << "%hi("; break; 509 case MipsII::MO_ABS_LO: O << "%lo("; break; 510 case MipsII::MO_TLSGD: O << "%tlsgd("; break; 511 case MipsII::MO_GOTTPREL: O << "%gottprel("; break; 512 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break; 513 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break; 514 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break; 515 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break; 516 case MipsII::MO_GOT_DISP: O << "%got_disp("; break; 517 case MipsII::MO_GOT_PAGE: O << "%got_page("; break; 518 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break; 519 } 520 521 switch (MO.getType()) { 522 case MachineOperand::MO_Register: 523 O << '$' 524 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower(); 525 break; 526 527 case MachineOperand::MO_Immediate: 528 O << MO.getImm(); 529 break; 530 531 case MachineOperand::MO_MachineBasicBlock: 532 O << *MO.getMBB()->getSymbol(); 533 return; 534 535 case MachineOperand::MO_GlobalAddress: 536 O << *getSymbol(MO.getGlobal()); 537 break; 538 539 case MachineOperand::MO_BlockAddress: { 540 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress()); 541 O << BA->getName(); 542 break; 543 } 544 545 case MachineOperand::MO_ExternalSymbol: 546 O << *GetExternalSymbolSymbol(MO.getSymbolName()); 547 break; 548 549 case MachineOperand::MO_JumpTableIndex: 550 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() 551 << '_' << MO.getIndex(); 552 break; 553 554 case MachineOperand::MO_ConstantPoolIndex: 555 O << MAI->getPrivateGlobalPrefix() << "CPI" 556 << getFunctionNumber() << "_" << MO.getIndex(); 557 if (MO.getOffset()) 558 O << "+" << MO.getOffset(); 559 break; 560 561 default: 562 llvm_unreachable("<unknown operand type>"); 563 } 564 565 if (closeP) O << ")"; 566} 567 568void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, 569 raw_ostream &O) { 570 const MachineOperand &MO = MI->getOperand(opNum); 571 if (MO.isImm()) 572 O << (unsigned short int)MO.getImm(); 573 else 574 printOperand(MI, opNum, O); 575} 576 577void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum, 578 raw_ostream &O) { 579 const MachineOperand &MO = MI->getOperand(opNum); 580 if (MO.isImm()) 581 O << (unsigned short int)(unsigned char)MO.getImm(); 582 else 583 printOperand(MI, opNum, O); 584} 585 586void MipsAsmPrinter:: 587printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { 588 // Load/Store memory operands -- imm($reg) 589 // If PIC target the target is loaded as the 590 // pattern lw $25,%call16($28) 591 printOperand(MI, opNum+1, O); 592 O << "("; 593 printOperand(MI, opNum, O); 594 O << ")"; 595} 596 597void MipsAsmPrinter:: 598printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) { 599 // when using stack locations for not load/store instructions 600 // print the same way as all normal 3 operand instructions. 601 printOperand(MI, opNum, O); 602 O << ", "; 603 printOperand(MI, opNum+1, O); 604 return; 605} 606 607void MipsAsmPrinter:: 608printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, 609 const char *Modifier) { 610 const MachineOperand &MO = MI->getOperand(opNum); 611 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); 612} 613 614void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { 615 // FIXME: Use SwitchSection. 616 617 // TODO: Need to add -mabicalls and -mno-abicalls flags. 618 // Currently we assume that -mabicalls is the default. 619 if (OutStreamer.hasRawTextSupport()) { 620 OutStreamer.EmitRawText(StringRef("\t.abicalls")); 621 Reloc::Model RM = Subtarget->getRelocationModel(); 622 if (RM == Reloc::Static && !Subtarget->hasMips64()) 623 OutStreamer.EmitRawText(StringRef("\t.option\tpic0")); 624 } 625 626 // Tell the assembler which ABI we are using 627 if (OutStreamer.hasRawTextSupport()) 628 OutStreamer.EmitRawText("\t.section .mdebug." + 629 Twine(getCurrentABIString())); 630 631 // TODO: handle O64 ABI 632 if (OutStreamer.hasRawTextSupport()) { 633 if (Subtarget->isABI_EABI()) { 634 if (Subtarget->isGP32bit()) 635 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32")); 636 else 637 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64")); 638 } 639 } 640 641 // return to previous section 642 if (OutStreamer.hasRawTextSupport()) 643 OutStreamer.EmitRawText(StringRef("\t.previous")); 644 645} 646 647static void emitELFHeaderFlagsCG(MipsTargetStreamer &TargetStreamer, 648 const MipsSubtarget &Subtarget) { 649 // Update e_header flags 650 unsigned EFlags = 0; 651 652 // TODO: Need to add -mabicalls and -mno-abicalls flags. 653 // Currently we assume that -mabicalls is the default. 654 EFlags |= ELF::EF_MIPS_CPIC; 655 656 if (Subtarget.inMips16Mode()) 657 EFlags |= ELF::EF_MIPS_ARCH_ASE_M16; 658 else 659 EFlags |= ELF::EF_MIPS_NOREORDER; 660 661 // Architecture 662 if (Subtarget.hasMips64r2()) 663 EFlags |= ELF::EF_MIPS_ARCH_64R2; 664 else if (Subtarget.hasMips64()) 665 EFlags |= ELF::EF_MIPS_ARCH_64; 666 else if (Subtarget.hasMips32r2()) 667 EFlags |= ELF::EF_MIPS_ARCH_32R2; 668 else 669 EFlags |= ELF::EF_MIPS_ARCH_32; 670 671 if (Subtarget.inMicroMipsMode()) 672 EFlags |= ELF::EF_MIPS_MICROMIPS; 673 674 // ABI 675 if (Subtarget.isABI_O32()) 676 EFlags |= ELF::EF_MIPS_ABI_O32; 677 678 // Relocation Model 679 Reloc::Model RM = Subtarget.getRelocationModel(); 680 if (RM == Reloc::PIC_ || RM == Reloc::Default) 681 EFlags |= ELF::EF_MIPS_PIC; 682 else if (RM == Reloc::Static) 683 ; // Do nothing for Reloc::Static 684 else 685 llvm_unreachable("Unsupported relocation model for e_flags"); 686 687 TargetStreamer.emitMipsHackELFFlags(EFlags); 688} 689 690void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) { 691 // Emit Mips ELF register info 692 Subtarget->getMReginfo().emitMipsReginfoSectionCG( 693 OutStreamer, getObjFileLowering(), *Subtarget); 694 emitELFHeaderFlagsCG(getTargetStreamer(), *Subtarget); 695} 696 697void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, 698 raw_ostream &OS) { 699 // TODO: implement 700} 701 702// Force static initialization. 703extern "C" void LLVMInitializeMipsAsmPrinter() { 704 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget); 705 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget); 706 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target); 707 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget); 708} 709