MipsCallingConv.td revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This describes the calling conventions for Mips architecture.
10//===----------------------------------------------------------------------===//
11
12/// CCIfSubtarget - Match if the current subtarget has a feature F.
13class CCIfSubtarget<string F, CCAction A>:
14  CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
15
16//===----------------------------------------------------------------------===//
17// Mips O32 Calling Convention
18//===----------------------------------------------------------------------===//
19
20// Only the return rules are defined here for O32. The rules for argument
21// passing are defined in MipsISelLowering.cpp.
22def RetCC_MipsO32 : CallingConv<[
23  // i32 are returned in registers V0, V1, A0, A1
24  CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
25
26  // f32 are returned in registers F0, F2
27  CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
28
29  // f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or
30  // in D0 and D1 in FP32bit mode.
31  CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>,
32  CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>>
33]>;
34
35//===----------------------------------------------------------------------===//
36// Mips N32/64 Calling Convention
37//===----------------------------------------------------------------------===//
38
39def CC_MipsN : CallingConv<[
40  // Promote i8/i16 arguments to i32.
41  CCIfType<[i8, i16], CCPromoteToType<i32>>,
42
43  // Integer arguments are passed in integer registers.
44  CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
45                                           T0, T1, T2, T3],
46                                          [F12, F13, F14, F15,
47                                           F16, F17, F18, F19]>>,
48
49  CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
50                                           T0_64, T1_64, T2_64, T3_64],
51                                          [D12_64, D13_64, D14_64, D15_64,
52                                           D16_64, D17_64, D18_64, D19_64]>>,
53
54  // f32 arguments are passed in single precision FP registers.
55  CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
56                                           F16, F17, F18, F19],
57                                          [A0_64, A1_64, A2_64, A3_64,
58                                           T0_64, T1_64, T2_64, T3_64]>>,
59
60  // f64 arguments are passed in double precision FP registers.
61  CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
62                                           D16_64, D17_64, D18_64, D19_64],
63                                          [A0_64, A1_64, A2_64, A3_64,
64                                           T0_64, T1_64, T2_64, T3_64]>>,
65
66  // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
67  CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
68  CCIfType<[i64, f64], CCAssignToStack<8, 8>>
69]>;
70
71// N32/64 variable arguments.
72// All arguments are passed in integer registers.
73def CC_MipsN_VarArg : CallingConv<[
74  // Promote i8/i16 arguments to i32.
75  CCIfType<[i8, i16], CCPromoteToType<i32>>,
76
77  CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
78
79  CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
80                                      T0_64, T1_64, T2_64, T3_64]>>,
81
82  // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
83  CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
84  CCIfType<[i64, f64], CCAssignToStack<8, 8>>
85]>;
86
87def RetCC_MipsN : CallingConv<[
88  // i32 are returned in registers V0, V1
89  CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
90
91  // i64 are returned in registers V0_64, V1_64
92  CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
93
94  // f32 are returned in registers F0, F2
95  CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
96
97  // f64 are returned in registers D0, D2
98  CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
99]>;
100
101// In soft-mode, register A0_64, instead of V1_64, is used to return a long
102// double value.
103def RetCC_F128Soft : CallingConv<[
104  CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>>
105]>;
106
107//===----------------------------------------------------------------------===//
108// Mips EABI Calling Convention
109//===----------------------------------------------------------------------===//
110
111def CC_MipsEABI : CallingConv<[
112  // Promote i8/i16 arguments to i32.
113  CCIfType<[i8, i16], CCPromoteToType<i32>>,
114
115  // Integer arguments are passed in integer registers.
116  CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
117
118  // Single fp arguments are passed in pairs within 32-bit mode
119  CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
120                  CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
121
122  CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
123                  CCAssignToReg<[F12, F14, F16, F18]>>>,
124
125  // The first 4 double fp arguments are passed in single fp registers.
126  CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
127                  CCAssignToReg<[D6, D7, D8, D9]>>>,
128
129  // Integer values get stored in stack slots that are 4 bytes in
130  // size and 4-byte aligned.
131  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
132
133  // Integer values get stored in stack slots that are 8 bytes in
134  // size and 8-byte aligned.
135  CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>>
136]>;
137
138def RetCC_MipsEABI : CallingConv<[
139  // i32 are returned in registers V0, V1
140  CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
141
142  // f32 are returned in registers F0, F1
143  CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
144
145  // f64 are returned in register D0
146  CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
147]>;
148
149//===----------------------------------------------------------------------===//
150// Mips FastCC Calling Convention
151//===----------------------------------------------------------------------===//
152def CC_MipsO32_FastCC : CallingConv<[
153  // f64 arguments are passed in double-precision floating pointer registers.
154  CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()",
155                                CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7,
156                                               D8, D9]>>>,
157  CCIfType<[f64], CCIfSubtarget<"isFP64bit()",
158                                CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
159                                               D4_64, D5_64, D6_64, D7_64,
160                                               D8_64, D9_64, D10_64, D11_64,
161                                               D12_64, D13_64, D14_64, D15_64,
162                                               D16_64, D17_64, D18_64,
163                                               D19_64]>>>,
164
165  // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
166  CCIfType<[f64], CCAssignToStack<8, 8>>
167]>;
168
169def CC_MipsN_FastCC : CallingConv<[
170  // Integer arguments are passed in integer registers.
171  CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
172                                 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
173                                 T8_64, V1_64]>>,
174
175  // f64 arguments are passed in double-precision floating pointer registers.
176  CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
177                                 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
178                                 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
179                                 D18_64, D19_64]>>,
180
181  // Stack parameter slots for i64 and f64 are 64-bit doublewords and
182  // 8-byte aligned.
183  CCIfType<[i64, f64], CCAssignToStack<8, 8>>
184]>;
185
186def CC_Mips_FastCC : CallingConv<[
187  // Handles byval parameters.
188  CCIfByVal<CCPassByVal<4, 4>>,
189
190  // Promote i8/i16 arguments to i32.
191  CCIfType<[i8, i16], CCPromoteToType<i32>>,
192
193  // Integer arguments are passed in integer registers. All scratch registers,
194  // except for AT, V0 and T9, are available to be used as argument registers.
195  CCIfType<[i32], CCIfSubtarget<"isNotTargetNaCl()",
196      CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
197
198  // In NaCl, T6, T7 and T8 are reserved and not available as argument
199  // registers for fastcc.  T6 contains the mask for sandboxing control flow
200  // (indirect jumps and calls).  T7 contains the mask for sandboxing memory
201  // accesses (loads and stores).  T8 contains the thread pointer.
202  CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
203      CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
204
205  // f32 arguments are passed in single-precision floating pointer registers.
206  CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
207                                 F11, F12, F13, F14, F15, F16, F17, F18, F19]>>,
208
209  // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
210  CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
211
212  CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
213  CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
214  CCDelegateTo<CC_MipsN_FastCC>
215]>;
216
217//==
218
219def CC_Mips16RetHelper : CallingConv<[
220  // Integer arguments are passed in integer registers.
221  CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
222]>;
223
224//===----------------------------------------------------------------------===//
225// Mips Calling Convention Dispatch
226//===----------------------------------------------------------------------===//
227
228def RetCC_Mips : CallingConv<[
229  CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
230  CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
231  CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
232  CCDelegateTo<RetCC_MipsO32>
233]>;
234
235//===----------------------------------------------------------------------===//
236// Callee-saved register lists.
237//===----------------------------------------------------------------------===//
238
239def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
240                                               (sequence "S%u", 7, 0))>;
241
242def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
243                                   (sequence "S%u", 7, 0))>;
244
245def CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP,
246                                        (sequence "S%u", 7, 0))>;
247
248def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
249                                   D30_64, RA_64, FP_64, GP_64,
250                                   (sequence "S%u_64", 7, 0))>;
251
252def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
253                                   GP_64, (sequence "S%u_64", 7, 0))>;
254
255def CSR_Mips16RetHelper :
256  CalleeSavedRegs<(add V0, V1, FP,
257                   (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
258                   (sequence "D%u", 15, 10))>;
259