MipsCondMov.td revision 5c3739927900af1bf5f5cdcbb3ebead2d89cd943 
1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the Conditional Moves implementation.
11//
12//===----------------------------------------------------------------------===//
13
14// Conditional moves:
15// These instructions are expanded in
16// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17// conditional move instructions.
18// cond:int, data:int
19class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
20                    string instr_asm> :
21  FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22     !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
23  let shamt = 0;
24  let Constraints = "$F = $rd";
25}
26
27// cond:int, data:float
28class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
29                   bits<6> func, string instr_asm> :
30  FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
31      !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
32  bits<5> rt;
33  let ft = rt;
34  let Constraints = "$F = $fd";
35}
36
37// cond:float, data:int
38class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
39                   string instr_asm> :
40  FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
41        !strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
42        [(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
43  let cc = 0;
44  let Uses = [FCR31];
45  let Constraints = "$F = $rd";
46}
47
48// cond:float, data:float
49class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
50                  string instr_asm> :
51  FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
52         !strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
53         [(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
54  let cc = 0;
55  let Uses = [FCR31];
56  let Constraints = "$F = $fd";
57}
58
59class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
60                  InstrItinClass Itin> :
61  InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
62         !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
63  let Constraints = "$F = $fd";
64}
65
66class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
67                  SDPatternOperator OpNode = null_frag> :
68  InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
69         !strconcat(opstr, "\t$rd, $rs, $$fcc0"),
70         [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
71  let Uses = [FCR31];
72  let Constraints = "$F = $rd";
73}
74
75class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
76                  SDPatternOperator OpNode = null_frag> :
77  InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
78         !strconcat(opstr, "\t$fd, $fs, $$fcc0"),
79         [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
80  let Uses = [FCR31];
81  let Constraints = "$F = $fd";
82}
83
84// select patterns
85multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
86                     Instruction MOVZInst, Instruction SLTOp,
87                     Instruction SLTuOp, Instruction SLTiOp,
88                     Instruction SLTiuOp> {
89  def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
90                (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
91  def : MipsPat<
92          (select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
93          (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
94  def : MipsPat<
95          (select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
96          (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
97  def : MipsPat<
98          (select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
99          (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
100  def : MipsPat<
101          (select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
102          (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
103  def : MipsPat<
104          (select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
105          (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
106}
107
108multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
109                     Instruction MOVZInst, Instruction XOROp> {
110  def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
111                (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
112  def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
113                (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
114}
115
116multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
117                     Instruction MOVZInst, Instruction XORiOp> {
118  def : MipsPat<
119            (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
120            (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
121}
122
123multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
124                    Instruction XOROp> {
125  def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
126                (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
127  def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
128                (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
129  def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
130                (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
131}
132
133// Instantiation of instructions.
134def MOVZ_I_I     : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
135let Predicates = [HasStdEnc],
136                  DecoderNamespace = "Mips64" in {
137  def MOVZ_I_I64   : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
138  def MOVZ_I64_I   : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
139    let isCodeGenOnly = 1;
140  }
141  def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz"> {
142    let isCodeGenOnly = 1;
143  }
144}
145
146def MOVN_I_I     : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
147let Predicates = [HasStdEnc],
148                  DecoderNamespace = "Mips64" in {
149  def MOVN_I_I64   : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
150  def MOVN_I64_I   : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {
151    let isCodeGenOnly = 1;
152  }
153  def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn"> {
154    let isCodeGenOnly = 1;
155  }
156}
157
158def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
159               CMov_I_F_FM<18, 16>;
160def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
161                 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
162  let DecoderNamespace = "Mips64";
163}
164
165def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>,
166               CMov_I_F_FM<19, 16>;
167def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>,
168                 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
169  let DecoderNamespace = "Mips64";
170}
171
172let Predicates = [NotFP64bit, HasStdEnc] in {
173  def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
174                   CMov_I_F_FM<18, 17>;
175  def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>,
176                   CMov_I_F_FM<19, 17>;
177}
178let Predicates = [IsFP64bit, HasStdEnc],
179                  DecoderNamespace = "Mips64" in {
180  def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
181                   CMov_I_F_FM<18, 17>;
182  def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
183                     CMov_I_F_FM<18, 17> {
184    let isCodeGenOnly = 1;
185  }
186  def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>,
187                   CMov_I_F_FM<19, 17>;
188  def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>,
189                     CMov_I_F_FM<19, 17> {
190    let isCodeGenOnly = 1;
191  }
192}
193
194def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>;
195def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>,
196               CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
197  let DecoderNamespace = "Mips64";
198}
199
200def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>;
201def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>,
202               CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
203  let DecoderNamespace = "Mips64";
204}
205
206def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>,
207             CMov_F_F_FM<16, 1>;
208def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>,
209             CMov_F_F_FM<16, 0>;
210
211let Predicates = [NotFP64bit, HasStdEnc] in {
212  def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>,
213                 CMov_F_F_FM<17, 1>;
214  def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>,
215                 CMov_F_F_FM<17, 0>;
216}
217let Predicates = [IsFP64bit, HasStdEnc],
218    DecoderNamespace = "Mips64" in {
219  def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>,
220                 CMov_F_F_FM<17, 1>;
221  def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>,
222                 CMov_F_F_FM<17, 0>;
223}
224
225// Instantiation of conditional move patterns.
226defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
227defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
228defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
229let Predicates = [HasMips64, HasStdEnc] in {
230  defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
231  defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
232                   SLTiu64>;
233  defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
234                   SLTiu64>;
235  defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
236  defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
237  defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
238  defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
239  defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
240  defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
241}
242
243defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
244let Predicates = [HasMips64, HasStdEnc] in {
245  defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
246  defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
247  defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
248}
249
250defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
251defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
252defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
253let Predicates = [HasMips64, HasStdEnc] in {
254  defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
255                   SLTiu64>;
256  defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
257  defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
258}
259
260let Predicates = [NotFP64bit, HasStdEnc] in {
261  defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
262  defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
263  defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
264}
265let Predicates = [IsFP64bit, HasStdEnc] in {
266  defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
267  defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
268                   SLTiu64>;
269  defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
270  defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
271  defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
272  defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;
273}
274