MipsCondMov.td revision 63723e5bf8bc1e5b699733cb79992b720b20f0d5 
1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the Conditional Moves implementation.
11//
12//===----------------------------------------------------------------------===//
13
14// Conditional moves:
15// These instructions are expanded in
16// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17// conditional move instructions.
18// cond:int, data:int
19class CMov_I_I_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
20                  InstrItinClass Itin> :
21  InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22         !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
23  let Constraints = "$F = $rd";
24}
25
26// cond:int, data:float
27class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
28                  InstrItinClass Itin> :
29  InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
30         !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
31  let Constraints = "$F = $fd";
32}
33
34// cond:float, data:int
35class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
36                  SDPatternOperator OpNode = null_frag> :
37  InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
38         !strconcat(opstr, "\t$rd, $rs, $$fcc0"),
39         [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
40  let Uses = [FCR31];
41  let Constraints = "$F = $rd";
42}
43
44// cond:float, data:float
45class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
46                  SDPatternOperator OpNode = null_frag> :
47  InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
48         !strconcat(opstr, "\t$fd, $fs, $$fcc0"),
49         [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
50  let Uses = [FCR31];
51  let Constraints = "$F = $fd";
52}
53
54// select patterns
55multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
56                     Instruction MOVZInst, Instruction SLTOp,
57                     Instruction SLTuOp, Instruction SLTiOp,
58                     Instruction SLTiuOp> {
59  def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60                (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61  def : MipsPat<
62          (select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
63          (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
64  def : MipsPat<
65          (select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
66          (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
67  def : MipsPat<
68          (select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
69          (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
70  def : MipsPat<
71          (select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
72          (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
73  def : MipsPat<
74          (select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
75          (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
76}
77
78multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
79                     Instruction MOVZInst, Instruction XOROp> {
80  def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
81                (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
82  def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
83                (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
84}
85
86multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
87                     Instruction MOVZInst, Instruction XORiOp> {
88  def : MipsPat<
89            (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
90            (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
91}
92
93multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
94                    Instruction XOROp> {
95  def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
96                (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
97  def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
98                (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
99  def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
100                (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
101}
102
103// Instantiation of instructions.
104def MOVZ_I_I : CMov_I_I_FT<"movz", CPURegs, CPURegs, NoItinerary>,
105               ADD_FM<0, 0xa>;
106let Predicates = [HasStdEnc],
107                  DecoderNamespace = "Mips64" in {
108  def MOVZ_I_I64   : CMov_I_I_FT<"movz", CPURegs, CPU64Regs, NoItinerary>,
109                     ADD_FM<0, 0xa>;
110  def MOVZ_I64_I   : CMov_I_I_FT<"movz", CPU64Regs, CPURegs, NoItinerary>,
111                     ADD_FM<0, 0xa> {
112    let isCodeGenOnly = 1;
113  }
114  def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64Regs, CPU64Regs, NoItinerary>,
115                     ADD_FM<0, 0xa> {
116    let isCodeGenOnly = 1;
117  }
118}
119
120def MOVN_I_I       : CMov_I_I_FT<"movn", CPURegs, CPURegs, NoItinerary>,
121                     ADD_FM<0, 0xb>;
122let Predicates = [HasStdEnc],
123                  DecoderNamespace = "Mips64" in {
124  def MOVN_I_I64   : CMov_I_I_FT<"movn", CPURegs, CPU64Regs, NoItinerary>,
125                     ADD_FM<0, 0xb>;
126  def MOVN_I64_I   : CMov_I_I_FT<"movn", CPU64Regs, CPURegs, NoItinerary>,
127                     ADD_FM<0, 0xb> {
128    let isCodeGenOnly = 1;
129  }
130  def MOVN_I64_I64 : CMov_I_I_FT<"movn", CPU64Regs, CPU64Regs, NoItinerary>,
131                     ADD_FM<0, 0xb> {
132    let isCodeGenOnly = 1;
133  }
134}
135
136def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
137               CMov_I_F_FM<18, 16>;
138def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
139                 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
140  let DecoderNamespace = "Mips64";
141}
142
143def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>,
144               CMov_I_F_FM<19, 16>;
145def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>,
146                 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
147  let DecoderNamespace = "Mips64";
148}
149
150let Predicates = [NotFP64bit, HasStdEnc] in {
151  def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
152                   CMov_I_F_FM<18, 17>;
153  def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>,
154                   CMov_I_F_FM<19, 17>;
155}
156let Predicates = [IsFP64bit, HasStdEnc],
157                  DecoderNamespace = "Mips64" in {
158  def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
159                   CMov_I_F_FM<18, 17>;
160  def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
161                     CMov_I_F_FM<18, 17> {
162    let isCodeGenOnly = 1;
163  }
164  def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>,
165                   CMov_I_F_FM<19, 17>;
166  def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>,
167                     CMov_I_F_FM<19, 17> {
168    let isCodeGenOnly = 1;
169  }
170}
171
172def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>;
173def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>,
174               CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
175  let DecoderNamespace = "Mips64";
176}
177
178def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>;
179def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>,
180               CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
181  let DecoderNamespace = "Mips64";
182}
183
184def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>,
185             CMov_F_F_FM<16, 1>;
186def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>,
187             CMov_F_F_FM<16, 0>;
188
189let Predicates = [NotFP64bit, HasStdEnc] in {
190  def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>,
191                 CMov_F_F_FM<17, 1>;
192  def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>,
193                 CMov_F_F_FM<17, 0>;
194}
195let Predicates = [IsFP64bit, HasStdEnc],
196    DecoderNamespace = "Mips64" in {
197  def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>,
198                 CMov_F_F_FM<17, 1>;
199  def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>,
200                 CMov_F_F_FM<17, 0>;
201}
202
203// Instantiation of conditional move patterns.
204defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
205defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
206defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
207let Predicates = [HasMips64, HasStdEnc] in {
208  defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
209  defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
210                   SLTiu64>;
211  defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
212                   SLTiu64>;
213  defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
214  defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
215  defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
216  defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
217  defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
218  defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
219}
220
221defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
222let Predicates = [HasMips64, HasStdEnc] in {
223  defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
224  defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
225  defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
226}
227
228defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
229defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
230defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
231let Predicates = [HasMips64, HasStdEnc] in {
232  defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
233                   SLTiu64>;
234  defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
235  defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
236}
237
238let Predicates = [NotFP64bit, HasStdEnc] in {
239  defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
240  defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
241  defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
242}
243let Predicates = [IsFP64bit, HasStdEnc] in {
244  defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
245  defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
246                   SLTiu64>;
247  defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
248  defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
249  defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
250  defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;
251}
252