MipsCondMov.td revision b67775df0cc702cd94408200ff2d58cf83f1334a 
1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the Conditional Moves implementation.
11//
12//===----------------------------------------------------------------------===//
13
14// Conditional moves:
15// These instructions are expanded in
16// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17// conditional move instructions.
18// cond:int, data:int
19class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
20                  InstrItinClass Itin> :
21  InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22         !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
23  let Constraints = "$F = $rd";
24}
25
26// cond:int, data:float
27class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
28                  InstrItinClass Itin> :
29  InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
30         !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
31  let Constraints = "$F = $fd";
32}
33
34// cond:float, data:int
35class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
36                  SDPatternOperator OpNode = null_frag> :
37  InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
38         !strconcat(opstr, "\t$rd, $rs, $fcc"),
39         [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
40         Itin, FrmFR> {
41  let Constraints = "$F = $rd";
42}
43
44// cond:float, data:float
45class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
46                  SDPatternOperator OpNode = null_frag> :
47  InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
48         !strconcat(opstr, "\t$fd, $fs, $fcc"),
49         [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
50         Itin, FrmFR> {
51  let Constraints = "$F = $fd";
52}
53
54// select patterns
55multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
56                     Instruction MOVZInst, Instruction SLTOp,
57                     Instruction SLTuOp, Instruction SLTiOp,
58                     Instruction SLTiuOp> {
59  def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60                (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61  def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62                (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63  def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
64                (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
65  def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
66                (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
67  def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
68                (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
69  def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
70                (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
71  def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
72                        DRC:$T, DRC:$F),
73                (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
74  def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
75                        DRC:$T, DRC:$F),
76                (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
77                          DRC:$F)>;
78}
79
80multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
81                     Instruction MOVZInst, Instruction XOROp> {
82  def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
83                (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
84  def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
85                (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
86}
87
88multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
89                     Instruction MOVZInst, Instruction XORiOp> {
90  def : MipsPat<
91            (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
92            (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
93}
94
95multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
96                    Instruction XOROp> {
97  def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
98                (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
99  def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
100                (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
101  def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
102                (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
103}
104
105// Instantiation of instructions.
106def MOVZ_I_I : CMov_I_I_FT<"movz", CPURegsOpnd, CPURegsOpnd, NoItinerary>,
107               ADD_FM<0, 0xa>;
108let Predicates = [HasStdEnc],
109                  DecoderNamespace = "Mips64" in {
110  def MOVZ_I_I64   : CMov_I_I_FT<"movz", CPURegsOpnd, CPU64RegsOpnd,
111                                  NoItinerary>, ADD_FM<0, 0xa>;
112  def MOVZ_I64_I   : CMov_I_I_FT<"movz", CPU64RegsOpnd, CPURegsOpnd,
113                                  NoItinerary>, ADD_FM<0, 0xa> {
114    let isCodeGenOnly = 1;
115  }
116  def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64RegsOpnd, CPU64RegsOpnd,
117                                  NoItinerary>, ADD_FM<0, 0xa> {
118    let isCodeGenOnly = 1;
119  }
120}
121
122def MOVN_I_I       : CMov_I_I_FT<"movn", CPURegsOpnd, CPURegsOpnd,
123                                  NoItinerary>, ADD_FM<0, 0xb>;
124let Predicates = [HasStdEnc],
125                  DecoderNamespace = "Mips64" in {
126  def MOVN_I_I64   : CMov_I_I_FT<"movn", CPURegsOpnd, CPU64RegsOpnd,
127                                  NoItinerary>, ADD_FM<0, 0xb>;
128  def MOVN_I64_I   : CMov_I_I_FT<"movn", CPU64RegsOpnd, CPURegsOpnd,
129                                  NoItinerary>, ADD_FM<0, 0xb> {
130    let isCodeGenOnly = 1;
131  }
132  def MOVN_I64_I64 : CMov_I_I_FT<"movn", CPU64RegsOpnd, CPU64RegsOpnd,
133                                  NoItinerary>, ADD_FM<0, 0xb> {
134    let isCodeGenOnly = 1;
135  }
136}
137
138def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegsOpnd, FGR32RegsOpnd, IIFmove>,
139               CMov_I_F_FM<18, 16>;
140def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64RegsOpnd, FGR32RegsOpnd, IIFmove>,
141                 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
142  let DecoderNamespace = "Mips64";
143}
144
145def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegsOpnd, FGR32RegsOpnd, IIFmove>,
146               CMov_I_F_FM<19, 16>;
147def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64RegsOpnd, FGR32RegsOpnd, IIFmove>,
148                 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
149  let DecoderNamespace = "Mips64";
150}
151
152let Predicates = [NotFP64bit, HasStdEnc] in {
153  def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegsOpnd, AFGR64RegsOpnd, IIFmove>,
154                   CMov_I_F_FM<18, 17>;
155  def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegsOpnd, AFGR64RegsOpnd, IIFmove>,
156                   CMov_I_F_FM<19, 17>;
157}
158let Predicates = [IsFP64bit, HasStdEnc],
159                  DecoderNamespace = "Mips64" in {
160  def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegsOpnd, FGR64RegsOpnd, IIFmove>,
161                   CMov_I_F_FM<18, 17>;
162  def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64RegsOpnd, FGR64RegsOpnd,
163                                  IIFmove>, CMov_I_F_FM<18, 17> {
164    let isCodeGenOnly = 1;
165  }
166  def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegsOpnd, FGR64RegsOpnd, IIFmove>,
167                   CMov_I_F_FM<19, 17>;
168  def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64RegsOpnd, FGR64RegsOpnd,
169                                  IIFmove>, CMov_I_F_FM<19, 17> {
170    let isCodeGenOnly = 1;
171  }
172}
173
174def MOVT_I : CMov_F_I_FT<"movt", CPURegsOpnd, IIAlu, MipsCMovFP_T>,
175             CMov_F_I_FM<1>;
176def MOVT_I64 : CMov_F_I_FT<"movt", CPU64RegsOpnd, IIAlu, MipsCMovFP_T>,
177               CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
178  let DecoderNamespace = "Mips64";
179}
180
181def MOVF_I : CMov_F_I_FT<"movf", CPURegsOpnd, IIAlu, MipsCMovFP_F>,
182             CMov_F_I_FM<0>;
183def MOVF_I64 : CMov_F_I_FT<"movf", CPU64RegsOpnd, IIAlu, MipsCMovFP_F>,
184               CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
185  let DecoderNamespace = "Mips64";
186}
187
188def MOVT_S : CMov_F_F_FT<"movt.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_T>,
189             CMov_F_F_FM<16, 1>;
190def MOVF_S : CMov_F_F_FT<"movf.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_F>,
191             CMov_F_F_FM<16, 0>;
192
193let Predicates = [NotFP64bit, HasStdEnc] in {
194  def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_T>,
195                 CMov_F_F_FM<17, 1>;
196  def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_F>,
197                 CMov_F_F_FM<17, 0>;
198}
199let Predicates = [IsFP64bit, HasStdEnc],
200    DecoderNamespace = "Mips64" in {
201  def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_T>,
202                 CMov_F_F_FM<17, 1>;
203  def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_F>,
204                 CMov_F_F_FM<17, 0>;
205}
206
207// Instantiation of conditional move patterns.
208defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
209defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
210defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
211let Predicates = [HasMips64, HasStdEnc] in {
212  defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
213  defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
214                   SLTiu64>;
215  defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
216                   SLTiu64>;
217  defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
218  defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
219  defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
220  defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
221  defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
222  defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
223}
224
225defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
226let Predicates = [HasMips64, HasStdEnc] in {
227  defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
228  defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
229  defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
230}
231
232defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
233defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
234defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
235let Predicates = [HasMips64, HasStdEnc] in {
236  defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
237                   SLTiu64>;
238  defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
239  defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
240}
241
242let Predicates = [NotFP64bit, HasStdEnc] in {
243  defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
244  defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
245  defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
246}
247let Predicates = [IsFP64bit, HasStdEnc] in {
248  defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
249  defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
250                   SLTiu64>;
251  defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
252  defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
253  defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
254  defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;
255}
256