MipsCondMov.td revision bf7f7b5e0eae40bb47a410c90f9f0885c0f38b2c
1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the Conditional Moves implementation. 11// 12//===----------------------------------------------------------------------===// 13 14// Conditional moves: 15// These instructions are expanded in 16// MipsISelLowering::EmitInstrWithCustomInserter if target does not have 17// conditional move instructions. 18// cond:int, data:int 19class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 20 InstrItinClass Itin> : 21 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), 22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> { 23 let Constraints = "$F = $rd"; 24} 25 26// cond:int, data:float 27class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 28 InstrItinClass Itin> : 29 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), 30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> { 31 let Constraints = "$F = $fd"; 32} 33 34// cond:float, data:int 35class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 36 SDPatternOperator OpNode = null_frag> : 37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F), 38 !strconcat(opstr, "\t$rd, $rs, $fcc"), 39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))], 40 Itin, FrmFR, opstr> { 41 let Constraints = "$F = $rd"; 42} 43 44// cond:float, data:float 45class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 46 SDPatternOperator OpNode = null_frag> : 47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F), 48 !strconcat(opstr, "\t$fd, $fs, $fcc"), 49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))], 50 Itin, FrmFR> { 51 let Constraints = "$F = $fd"; 52} 53 54// select patterns 55multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC, 56 Instruction MOVZInst, Instruction SLTOp, 57 Instruction SLTuOp, Instruction SLTiOp, 58 Instruction SLTiuOp> { 59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F), 64 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>; 65 def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F), 66 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>; 67 def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 68 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 69 def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 70 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 71 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)), 72 DRC:$T, DRC:$F), 73 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; 74 def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)), 75 DRC:$T, DRC:$F), 76 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), 77 DRC:$F)>; 78} 79 80multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC, 81 Instruction MOVZInst, Instruction XOROp> { 82 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 83 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F), 85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>; 86} 87 88multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC, 89 Instruction MOVZInst, Instruction XORiOp> { 90 def : MipsPat< 91 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F), 92 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>; 93} 94 95multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, 96 Instruction XOROp> { 97 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 98 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F), 100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>; 101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F), 102 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>; 103} 104 105// Instantiation of instructions. 106def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>, 107 ADD_FM<0, 0xa>; 108 109let Predicates = [HasStdEnc], isCodeGenOnly = 1 in { 110 def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, 111 NoItinerary>, ADD_FM<0, 0xa>; 112 def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, 113 NoItinerary>, ADD_FM<0, 0xa>; 114 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, 115 NoItinerary>, ADD_FM<0, 0xa>; 116} 117 118def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, 119 NoItinerary>, ADD_FM<0, 0xb>; 120 121let Predicates = [HasStdEnc], isCodeGenOnly = 1 in { 122 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, 123 NoItinerary>, ADD_FM<0, 0xb>; 124 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, 125 NoItinerary>, ADD_FM<0, 0xb>; 126 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, 127 NoItinerary>, ADD_FM<0, 0xb>; 128} 129 130def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>, 131 CMov_I_F_FM<18, 16>; 132 133let isCodeGenOnly = 1 in 134def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, IIFmove>, 135 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>; 136 137def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>, 138 CMov_I_F_FM<19, 16>; 139 140let isCodeGenOnly = 1 in 141def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, IIFmove>, 142 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>; 143 144let Predicates = [NotFP64bit, HasStdEnc] in { 145 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, IIFmove>, 146 CMov_I_F_FM<18, 17>; 147 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, IIFmove>, 148 CMov_I_F_FM<19, 17>; 149} 150 151let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 152 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, IIFmove>, 153 CMov_I_F_FM<18, 17>; 154 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, IIFmove>, 155 CMov_I_F_FM<19, 17>; 156 let isCodeGenOnly = 1 in { 157 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, 158 IIFmove>, CMov_I_F_FM<18, 17>; 159 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, 160 IIFmove>, CMov_I_F_FM<19, 17>; 161 } 162} 163 164def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>, 165 CMov_F_I_FM<1>; 166 167let isCodeGenOnly = 1 in 168def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, IIArith, MipsCMovFP_T>, 169 CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>; 170 171def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>, 172 CMov_F_I_FM<0>; 173 174let isCodeGenOnly = 1 in 175def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, IIArith, MipsCMovFP_F>, 176 CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>; 177 178def MOVT_S : CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>, 179 CMov_F_F_FM<16, 1>; 180def MOVF_S : CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>, 181 CMov_F_F_FM<16, 0>; 182 183let Predicates = [NotFP64bit, HasStdEnc] in { 184 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64Opnd, IIFmove, MipsCMovFP_T>, 185 CMov_F_F_FM<17, 1>; 186 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove, MipsCMovFP_F>, 187 CMov_F_F_FM<17, 0>; 188} 189 190let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 191 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, IIFmove, MipsCMovFP_T>, 192 CMov_F_F_FM<17, 1>; 193 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, IIFmove, MipsCMovFP_F>, 194 CMov_F_F_FM<17, 0>; 195} 196 197// Instantiation of conditional move patterns. 198defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>; 199defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>; 200defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>; 201let Predicates = [HasMips64, HasStdEnc] in { 202 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>; 203 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, 204 SLTiu64>; 205 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, 206 SLTiu64>; 207 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>; 208 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>; 209 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>; 210 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>; 211 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>; 212 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>; 213} 214 215defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>; 216let Predicates = [HasMips64, HasStdEnc] in { 217 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>; 218 defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>; 219 defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>; 220} 221 222defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>; 223defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>; 224defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>; 225let Predicates = [HasMips64, HasStdEnc] in { 226 defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, 227 SLTiu64>; 228 defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>; 229 defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>; 230} 231 232let Predicates = [NotFP64bit, HasStdEnc] in { 233 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>; 234 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>; 235 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>; 236} 237let Predicates = [IsFP64bit, HasStdEnc] in { 238 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>; 239 defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, 240 SLTiu64>; 241 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>; 242 defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>; 243 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>; 244 defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>; 245} 246