1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10def HasDSP : Predicate<"Subtarget->hasDSP()">,
11             AssemblerPredicate<"FeatureDSP">;
12def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
13               AssemblerPredicate<"FeatureDSPR2">;
14
15// Fields.
16class Field6<bits<6> val> {
17  bits<6> V = val;
18}
19
20def SPECIAL3_OPCODE : Field6<0b011111>;
21def REGIMM_OPCODE : Field6<0b000001>;
22
23class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
24  let Predicates = [HasDSP];
25}
26
27class PseudoDSP<dag outs, dag ins, list<dag> pattern,
28                InstrItinClass itin = IIPseudo>:
29  MipsPseudo<outs, ins, pattern, itin> {
30  let Predicates = [HasDSP];
31}
32
33// ADDU.QB sub-class format.
34class ADDU_QB_FMT<bits<5> op> : DSPInst {
35  bits<5> rd;
36  bits<5> rs;
37  bits<5> rt;
38
39  let Opcode = SPECIAL3_OPCODE.V;
40
41  let Inst{25-21} = rs;
42  let Inst{20-16} = rt;
43  let Inst{15-11} = rd;
44  let Inst{10-6}  = op;
45  let Inst{5-0}   = 0b010000;
46}
47
48class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
49  bits<5> rd;
50  bits<5> rs;
51
52  let Opcode = SPECIAL3_OPCODE.V;
53
54  let Inst{25-21} = rs;
55  let Inst{20-16} = 0;
56  let Inst{15-11} = rd;
57  let Inst{10-6}  = op;
58  let Inst{5-0}   = 0b010000;
59}
60
61// CMPU.EQ.QB sub-class format.
62class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
63  bits<5> rs;
64  bits<5> rt;
65
66  let Opcode = SPECIAL3_OPCODE.V;
67
68  let Inst{25-21} = rs;
69  let Inst{20-16} = rt;
70  let Inst{15-11} = 0;
71  let Inst{10-6}  = op;
72  let Inst{5-0}   = 0b010001;
73}
74
75class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
76  bits<5> rs;
77  bits<5> rt;
78  bits<5> rd;
79
80  let Opcode = SPECIAL3_OPCODE.V;
81
82  let Inst{25-21} = rs;
83  let Inst{20-16} = rt;
84  let Inst{15-11} = rd;
85  let Inst{10-6}  = op;
86  let Inst{5-0}   = 0b010001;
87}
88
89class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
90  bits<5> rs;
91  bits<5> rt;
92  bits<5> sa;
93
94  let Opcode = SPECIAL3_OPCODE.V;
95
96  let Inst{25-21} = rs;
97  let Inst{20-16} = rt;
98  let Inst{15-11} = sa;
99  let Inst{10-6}  = op;
100  let Inst{5-0}   = 0b010001;
101}
102
103// ABSQ_S.PH sub-class format.
104class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
105  bits<5> rd;
106  bits<5> rt;
107
108  let Opcode = SPECIAL3_OPCODE.V;
109
110  let Inst{25-21} = 0;
111  let Inst{20-16} = rt;
112  let Inst{15-11} = rd;
113  let Inst{10-6}  = op;
114  let Inst{5-0}   = 0b010010;
115}
116
117
118class REPL_FMT<bits<5> op> : DSPInst {
119  bits<5> rd;
120  bits<10> imm;
121
122  let Opcode = SPECIAL3_OPCODE.V;
123
124  let Inst{25-16} = imm;
125  let Inst{15-11} = rd;
126  let Inst{10-6}  = op;
127  let Inst{5-0}   = 0b010010;
128}
129
130// SHLL.QB sub-class format.
131class SHLL_QB_FMT<bits<5> op> : DSPInst {
132  bits<5> rd;
133  bits<5> rt;
134  bits<5> rs_sa;
135
136  let Opcode = SPECIAL3_OPCODE.V;
137
138  let Inst{25-21} = rs_sa;
139  let Inst{20-16} = rt;
140  let Inst{15-11} = rd;
141  let Inst{10-6}  = op;
142  let Inst{5-0}   = 0b010011;
143}
144
145// LX sub-class format.
146class LX_FMT<bits<5> op> : DSPInst {
147  bits<5> rd;
148  bits<5> base;
149  bits<5> index;
150
151  let Opcode = SPECIAL3_OPCODE.V;
152
153  let Inst{25-21} = base;
154  let Inst{20-16} = index;
155  let Inst{15-11} = rd;
156  let Inst{10-6}  = op;
157  let Inst{5-0} = 0b001010;
158}
159
160// ADDUH.QB sub-class format.
161class ADDUH_QB_FMT<bits<5> op> : DSPInst {
162  bits<5> rd;
163  bits<5> rs;
164  bits<5> rt;
165
166  let Opcode = SPECIAL3_OPCODE.V;
167
168  let Inst{25-21} = rs;
169  let Inst{20-16} = rt;
170  let Inst{15-11} = rd;
171  let Inst{10-6} = op;
172  let Inst{5-0} = 0b011000;
173}
174
175// APPEND sub-class format.
176class APPEND_FMT<bits<5> op> : DSPInst {
177  bits<5> rt;
178  bits<5> rs;
179  bits<5> sa;
180
181  let Opcode = SPECIAL3_OPCODE.V;
182
183  let Inst{25-21} = rs;
184  let Inst{20-16} = rt;
185  let Inst{15-11} = sa;
186  let Inst{10-6} = op;
187  let Inst{5-0} = 0b110001;
188}
189
190// DPA.W.PH sub-class format.
191class DPA_W_PH_FMT<bits<5> op> : DSPInst {
192  bits<2> ac;
193  bits<5> rs;
194  bits<5> rt;
195
196  let Opcode = SPECIAL3_OPCODE.V;
197
198  let Inst{25-21} = rs;
199  let Inst{20-16} = rt;
200  let Inst{15-13} = 0;
201  let Inst{12-11} = ac;
202  let Inst{10-6}  = op;
203  let Inst{5-0} = 0b110000;
204}
205
206// MULT sub-class format.
207class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
208  bits<2> ac;
209  bits<5> rs;
210  bits<5> rt;
211
212  let Opcode = opcode;
213
214  let Inst{25-21} = rs;
215  let Inst{20-16} = rt;
216  let Inst{15-13} = 0;
217  let Inst{12-11} = ac;
218  let Inst{10-6}  = 0;
219  let Inst{5-0} = funct;
220}
221
222// MFHI sub-class format.
223class MFHI_FMT<bits<6> funct> : DSPInst {
224  bits<5> rd;
225  bits<2> ac;
226
227  let Inst{31-26} = 0;
228  let Inst{25-23} = 0;
229  let Inst{22-21} = ac;
230  let Inst{20-16} = 0;
231  let Inst{15-11} = rd;
232  let Inst{10-6} = 0;
233  let Inst{5-0} = funct;
234}
235
236// MTHI sub-class format.
237class MTHI_FMT<bits<6> funct> : DSPInst {
238  bits<5> rs;
239  bits<2> ac;
240
241  let Inst{31-26} = 0;
242  let Inst{25-21} = rs;
243  let Inst{20-13} = 0;
244  let Inst{12-11} = ac;
245  let Inst{10-6} = 0;
246  let Inst{5-0} = funct;
247}
248
249// EXTR.W sub-class format (type 1).
250class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
251  bits<5> rt;
252  bits<2> ac;
253  bits<5> shift_rs;
254
255  let Opcode = SPECIAL3_OPCODE.V;
256
257  let Inst{25-21} = shift_rs;
258  let Inst{20-16} = rt;
259  let Inst{15-13} = 0;
260  let Inst{12-11} = ac;
261  let Inst{10-6} = op;
262  let Inst{5-0} = 0b111000;
263}
264
265// SHILO sub-class format.
266class SHILO_R1_FMT<bits<5> op> : DSPInst {
267  bits<2> ac;
268  bits<6> shift;
269
270  let Opcode = SPECIAL3_OPCODE.V;
271
272  let Inst{25-20} = shift;
273  let Inst{19-13} = 0;
274  let Inst{12-11} = ac;
275  let Inst{10-6} = op;
276  let Inst{5-0} = 0b111000;
277}
278
279class SHILO_R2_FMT<bits<5> op> : DSPInst {
280  bits<2> ac;
281  bits<5> rs;
282
283  let Opcode = SPECIAL3_OPCODE.V;
284
285  let Inst{25-21} = rs;
286  let Inst{20-13} = 0;
287  let Inst{12-11} = ac;
288  let Inst{10-6} = op;
289  let Inst{5-0} = 0b111000;
290}
291
292class RDDSP_FMT<bits<5> op> : DSPInst {
293  bits<5> rd;
294  bits<10> mask;
295
296  let Opcode = SPECIAL3_OPCODE.V;
297
298  let Inst{25-16} = mask;
299  let Inst{15-11} = rd;
300  let Inst{10-6} = op;
301  let Inst{5-0} = 0b111000;
302}
303
304class WRDSP_FMT<bits<5> op> : DSPInst {
305  bits<5> rs;
306  bits<10> mask;
307
308  let Opcode = SPECIAL3_OPCODE.V;
309
310  let Inst{25-21} = rs;
311  let Inst{20-11} = mask;
312  let Inst{10-6} = op;
313  let Inst{5-0} = 0b111000;
314}
315
316class BPOSGE32_FMT<bits<5> op> : DSPInst {
317  bits<16> offset;
318
319  let Opcode = REGIMM_OPCODE.V;
320
321  let Inst{25-21} = 0;
322  let Inst{20-16} = op;
323  let Inst{15-0} = offset;
324}
325
326// INSV sub-class format.
327class INSV_FMT<bits<6> op> : DSPInst {
328  bits<5> rt;
329  bits<5> rs;
330
331  let Opcode = SPECIAL3_OPCODE.V;
332
333  let Inst{25-21} = rs;
334  let Inst{20-16} = rt;
335  let Inst{15-6} = 0;
336  let Inst{5-0} = op;
337}
338