MipsDSPInstrFormats.td revision 451b0e7b8a56457114d8989ac836163d82a1cf5e
1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10def HasDSP : Predicate<"Subtarget.hasDSP()">, 11 AssemblerPredicate<"FeatureDSP">; 12def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">, 13 AssemblerPredicate<"FeatureDSPR2">; 14 15// Fields. 16class Field6<bits<6> val> { 17 bits<6> V = val; 18} 19 20def SPECIAL3_OPCODE : Field6<0b011111>; 21def REGIMM_OPCODE : Field6<0b000001>; 22 23class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { 24 let Predicates = [HasDSP]; 25} 26 27class PseudoDSP<dag outs, dag ins, list<dag> pattern>: 28 MipsPseudo<outs, ins, "", pattern> { 29 let Predicates = [HasDSP]; 30} 31 32// ADDU.QB sub-class format. 33class ADDU_QB_FMT<bits<5> op> : DSPInst { 34 bits<5> rd; 35 bits<5> rs; 36 bits<5> rt; 37 38 let Opcode = SPECIAL3_OPCODE.V; 39 40 let Inst{25-21} = rs; 41 let Inst{20-16} = rt; 42 let Inst{15-11} = rd; 43 let Inst{10-6} = op; 44 let Inst{5-0} = 0b010000; 45} 46 47class RADDU_W_QB_FMT<bits<5> op> : DSPInst { 48 bits<5> rd; 49 bits<5> rs; 50 51 let Opcode = SPECIAL3_OPCODE.V; 52 53 let Inst{25-21} = rs; 54 let Inst{20-16} = 0; 55 let Inst{15-11} = rd; 56 let Inst{10-6} = op; 57 let Inst{5-0} = 0b010000; 58} 59 60// CMPU.EQ.QB sub-class format. 61class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst { 62 bits<5> rs; 63 bits<5> rt; 64 65 let Opcode = SPECIAL3_OPCODE.V; 66 67 let Inst{25-21} = rs; 68 let Inst{20-16} = rt; 69 let Inst{15-11} = 0; 70 let Inst{10-6} = op; 71 let Inst{5-0} = 0b010001; 72} 73 74class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst { 75 bits<5> rs; 76 bits<5> rt; 77 bits<5> rd; 78 79 let Opcode = SPECIAL3_OPCODE.V; 80 81 let Inst{25-21} = rs; 82 let Inst{20-16} = rt; 83 let Inst{15-11} = rd; 84 let Inst{10-6} = op; 85 let Inst{5-0} = 0b010001; 86} 87 88class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst { 89 bits<5> rs; 90 bits<5> rt; 91 bits<5> sa; 92 93 let Opcode = SPECIAL3_OPCODE.V; 94 95 let Inst{25-21} = rs; 96 let Inst{20-16} = rt; 97 let Inst{15-11} = sa; 98 let Inst{10-6} = op; 99 let Inst{5-0} = 0b010001; 100} 101 102// DPA.W.PH sub-class format. 103class DPA_W_PH_FMT<bits<5> op> : DSPInst { 104 bits<2> ac; 105 bits<5> rs; 106 bits<5> rt; 107 108 let Opcode = SPECIAL3_OPCODE.V; 109 110 let Inst{25-21} = rs; 111 let Inst{20-16} = rt; 112 let Inst{15-13} = 0; 113 let Inst{12-11} = ac; 114 let Inst{10-6} = op; 115 let Inst{5-0} = 0b110000; 116} 117 118// MULT sub-class format. 119class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { 120 bits<2> ac; 121 bits<5> rs; 122 bits<5> rt; 123 124 let Opcode = opcode; 125 126 let Inst{25-21} = rs; 127 let Inst{20-16} = rt; 128 let Inst{15-13} = 0; 129 let Inst{12-11} = ac; 130 let Inst{10-6} = 0; 131 let Inst{5-0} = funct; 132} 133 134// EXTR.W sub-class format (type 1). 135class EXTR_W_TY1_FMT<bits<5> op> : DSPInst { 136 bits<5> rt; 137 bits<2> ac; 138 bits<5> shift_rs; 139 140 let Opcode = SPECIAL3_OPCODE.V; 141 142 let Inst{25-21} = shift_rs; 143 let Inst{20-16} = rt; 144 let Inst{15-13} = 0; 145 let Inst{12-11} = ac; 146 let Inst{10-6} = op; 147 let Inst{5-0} = 0b111000; 148} 149 150// SHILO sub-class format. 151class SHILO_R1_FMT<bits<5> op> : DSPInst { 152 bits<2> ac; 153 bits<6> shift; 154 155 let Opcode = SPECIAL3_OPCODE.V; 156 157 let Inst{25-20} = shift; 158 let Inst{19-13} = 0; 159 let Inst{12-11} = ac; 160 let Inst{10-6} = op; 161 let Inst{5-0} = 0b111000; 162} 163 164class SHILO_R2_FMT<bits<5> op> : DSPInst { 165 bits<2> ac; 166 bits<5> rs; 167 168 let Opcode = SPECIAL3_OPCODE.V; 169 170 let Inst{25-21} = rs; 171 let Inst{20-13} = 0; 172 let Inst{12-11} = ac; 173 let Inst{10-6} = op; 174 let Inst{5-0} = 0b111000; 175} 176 177class BPOSGE32_FMT<bits<5> op> : DSPInst { 178 bits<16> offset; 179 180 let Opcode = REGIMM_OPCODE.V; 181 182 let Inst{25-21} = 0; 183 let Inst{20-16} = op; 184 let Inst{15-0} = offset; 185} 186