MipsDSPInstrFormats.td revision e91ff1d135fb6b03e8bd9c8a09a67570bae583ad
1//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10def HasDSP : Predicate<"Subtarget.hasDSP()">, 11 AssemblerPredicate<"FeatureDSP">; 12def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">, 13 AssemblerPredicate<"FeatureDSPR2">; 14 15// Fields. 16class Field6<bits<6> val> { 17 bits<6> V = val; 18} 19 20def SPECIAL3_OPCODE : Field6<0b011111>; 21def REGIMM_OPCODE : Field6<0b000001>; 22 23class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { 24 let Predicates = [HasDSP]; 25} 26 27class PseudoDSP<dag outs, dag ins, list<dag> pattern>: 28 MipsPseudo<outs, ins, "", pattern> { 29 let Predicates = [HasDSP]; 30} 31 32// ADDU.QB sub-class format. 33class ADDU_QB_FMT<bits<5> op> : DSPInst { 34 bits<5> rd; 35 bits<5> rs; 36 bits<5> rt; 37 38 let Opcode = SPECIAL3_OPCODE.V; 39 40 let Inst{25-21} = rs; 41 let Inst{20-16} = rt; 42 let Inst{15-11} = rd; 43 let Inst{10-6} = op; 44 let Inst{5-0} = 0b010000; 45} 46 47class RADDU_W_QB_FMT<bits<5> op> : DSPInst { 48 bits<5> rd; 49 bits<5> rs; 50 51 let Opcode = SPECIAL3_OPCODE.V; 52 53 let Inst{25-21} = rs; 54 let Inst{20-16} = 0; 55 let Inst{15-11} = rd; 56 let Inst{10-6} = op; 57 let Inst{5-0} = 0b010000; 58} 59 60// CMPU.EQ.QB sub-class format. 61class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst { 62 bits<5> rs; 63 bits<5> rt; 64 65 let Opcode = SPECIAL3_OPCODE.V; 66 67 let Inst{25-21} = rs; 68 let Inst{20-16} = rt; 69 let Inst{15-11} = 0; 70 let Inst{10-6} = op; 71 let Inst{5-0} = 0b010001; 72} 73 74class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst { 75 bits<5> rs; 76 bits<5> rt; 77 bits<5> rd; 78 79 let Opcode = SPECIAL3_OPCODE.V; 80 81 let Inst{25-21} = rs; 82 let Inst{20-16} = rt; 83 let Inst{15-11} = rd; 84 let Inst{10-6} = op; 85 let Inst{5-0} = 0b010001; 86} 87 88class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst { 89 bits<5> rs; 90 bits<5> rt; 91 bits<5> sa; 92 93 let Opcode = SPECIAL3_OPCODE.V; 94 95 let Inst{25-21} = rs; 96 let Inst{20-16} = rt; 97 let Inst{15-11} = sa; 98 let Inst{10-6} = op; 99 let Inst{5-0} = 0b010001; 100} 101 102// ABSQ_S.PH sub-class format. 103class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst { 104 bits<5> rd; 105 bits<5> rt; 106 107 let Opcode = SPECIAL3_OPCODE.V; 108 109 let Inst{25-21} = 0; 110 let Inst{20-16} = rt; 111 let Inst{15-11} = rd; 112 let Inst{10-6} = op; 113 let Inst{5-0} = 0b010010; 114} 115 116 117class REPL_FMT<bits<5> op> : DSPInst { 118 bits<5> rd; 119 bits<10> imm; 120 121 let Opcode = SPECIAL3_OPCODE.V; 122 123 let Inst{25-16} = imm; 124 let Inst{15-11} = rd; 125 let Inst{10-6} = op; 126 let Inst{5-0} = 0b010010; 127} 128 129// SHLL.QB sub-class format. 130class SHLL_QB_FMT<bits<5> op> : DSPInst { 131 bits<5> rd; 132 bits<5> rt; 133 bits<5> rs_sa; 134 135 let Opcode = SPECIAL3_OPCODE.V; 136 137 let Inst{25-21} = rs_sa; 138 let Inst{20-16} = rt; 139 let Inst{15-11} = rd; 140 let Inst{10-6} = op; 141 let Inst{5-0} = 0b010011; 142} 143 144// ADDUH.QB sub-class format. 145class ADDUH_QB_FMT<bits<5> op> : DSPInst { 146 bits<5> rd; 147 bits<5> rs; 148 bits<5> rt; 149 150 let Opcode = SPECIAL3_OPCODE.V; 151 152 let Inst{25-21} = rs; 153 let Inst{20-16} = rt; 154 let Inst{15-11} = rd; 155 let Inst{10-6} = op; 156 let Inst{5-0} = 0b011000; 157} 158 159// DPA.W.PH sub-class format. 160class DPA_W_PH_FMT<bits<5> op> : DSPInst { 161 bits<2> ac; 162 bits<5> rs; 163 bits<5> rt; 164 165 let Opcode = SPECIAL3_OPCODE.V; 166 167 let Inst{25-21} = rs; 168 let Inst{20-16} = rt; 169 let Inst{15-13} = 0; 170 let Inst{12-11} = ac; 171 let Inst{10-6} = op; 172 let Inst{5-0} = 0b110000; 173} 174 175// MULT sub-class format. 176class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { 177 bits<2> ac; 178 bits<5> rs; 179 bits<5> rt; 180 181 let Opcode = opcode; 182 183 let Inst{25-21} = rs; 184 let Inst{20-16} = rt; 185 let Inst{15-13} = 0; 186 let Inst{12-11} = ac; 187 let Inst{10-6} = 0; 188 let Inst{5-0} = funct; 189} 190 191// EXTR.W sub-class format (type 1). 192class EXTR_W_TY1_FMT<bits<5> op> : DSPInst { 193 bits<5> rt; 194 bits<2> ac; 195 bits<5> shift_rs; 196 197 let Opcode = SPECIAL3_OPCODE.V; 198 199 let Inst{25-21} = shift_rs; 200 let Inst{20-16} = rt; 201 let Inst{15-13} = 0; 202 let Inst{12-11} = ac; 203 let Inst{10-6} = op; 204 let Inst{5-0} = 0b111000; 205} 206 207// SHILO sub-class format. 208class SHILO_R1_FMT<bits<5> op> : DSPInst { 209 bits<2> ac; 210 bits<6> shift; 211 212 let Opcode = SPECIAL3_OPCODE.V; 213 214 let Inst{25-20} = shift; 215 let Inst{19-13} = 0; 216 let Inst{12-11} = ac; 217 let Inst{10-6} = op; 218 let Inst{5-0} = 0b111000; 219} 220 221class SHILO_R2_FMT<bits<5> op> : DSPInst { 222 bits<2> ac; 223 bits<5> rs; 224 225 let Opcode = SPECIAL3_OPCODE.V; 226 227 let Inst{25-21} = rs; 228 let Inst{20-13} = 0; 229 let Inst{12-11} = ac; 230 let Inst{10-6} = op; 231 let Inst{5-0} = 0b111000; 232} 233 234class RDDSP_FMT<bits<5> op> : DSPInst { 235 bits<5> rd; 236 bits<10> mask; 237 238 let Opcode = SPECIAL3_OPCODE.V; 239 240 let Inst{25-16} = mask; 241 let Inst{15-11} = rd; 242 let Inst{10-6} = op; 243 let Inst{5-0} = 0b111000; 244} 245 246class BPOSGE32_FMT<bits<5> op> : DSPInst { 247 bits<16> offset; 248 249 let Opcode = REGIMM_OPCODE.V; 250 251 let Inst{25-21} = 0; 252 let Inst{20-16} = op; 253 let Inst{15-0} = offset; 254} 255