MipsDSPInstrInfo.td revision 1e7739f6140da773b6e998525d7900fa82670f00
1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips DSP ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// ImmLeaf 15def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; 16def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; 17def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; 18def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; 19def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; 20def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; 21 22// Mips-specific dsp nodes 23def SDT_MipsExtr : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; 24def SDT_MipsShilo : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 25def SDT_MipsDPA : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; 26 27class MipsDSPBase<string Opc, SDTypeProfile Prof> : 28 SDNode<!strconcat("MipsISD::", Opc), Prof, 29 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 30 31class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : 32 SDNode<!strconcat("MipsISD::", Opc), Prof, 33 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPSideEffect]>; 34 35def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; 36def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; 37def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; 38def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; 39def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; 40def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; 41 42def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; 43def MipsMTHLIP : MipsDSPBase<"MTHLIP", SDT_MipsShilo>; 44 45def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; 46def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; 47def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; 48def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; 49def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; 50 51def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; 52def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; 53def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; 54def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; 55def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; 56def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; 57def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; 58def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; 59 60def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; 61def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; 62def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; 63def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; 64def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; 65def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; 66def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; 67def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; 68def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; 69 70def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; 71def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; 72def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; 73def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; 74def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; 75def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; 76 77// Flags. 78class UseAC { 79 list<Register> Uses = [AC0]; 80} 81 82class UseDSPCtrl { 83 list<Register> Uses = [DSPCtrl]; 84} 85 86class ClearDefs { 87 list<Register> Defs = []; 88} 89 90// Instruction encoding. 91class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; 92class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; 93class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; 94class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; 95class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; 96class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; 97class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; 98class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; 99class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; 100class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; 101class ADDSC_ENC : ADDU_QB_FMT<0b10000>; 102class ADDWC_ENC : ADDU_QB_FMT<0b10001>; 103class MODSUB_ENC : ADDU_QB_FMT<0b10010>; 104class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; 105class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>; 106class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>; 107class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; 108class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; 109class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; 110class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; 111class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>; 112class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>; 113class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>; 114class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>; 115class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>; 116class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>; 117class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>; 118class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>; 119class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>; 120class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; 121class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>; 122class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>; 123class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>; 124class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>; 125class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>; 126class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>; 127class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>; 128class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>; 129class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>; 130class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>; 131class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>; 132class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>; 133class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>; 134class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>; 135class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>; 136class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>; 137class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; 138class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; 139class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; 140class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; 141class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 142class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; 143class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; 144class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; 145class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; 146class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; 147class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; 148class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; 149class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; 150class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; 151class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; 152class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; 153class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; 154class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; 155class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; 156class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; 157class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; 158class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; 159class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; 160class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; 161class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; 162class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; 163class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; 164class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; 165class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; 166class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; 167class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; 168class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; 169class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; 170class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>; 171class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; 172class REPL_QB_ENC : REPL_FMT<0b00010>; 173class REPL_PH_ENC : REPL_FMT<0b01010>; 174class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>; 175class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>; 176class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; 177class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; 178class LWX_ENC : LX_FMT<0b00000>; 179class LHX_ENC : LX_FMT<0b00100>; 180class LBUX_ENC : LX_FMT<0b00110>; 181class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; 182class INSV_ENC : INSV_FMT<0b001100>; 183 184class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; 185class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; 186class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; 187class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; 188class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; 189class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; 190class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; 191class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; 192class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; 193class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; 194class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; 195class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; 196class SHILO_ENC : SHILO_R1_FMT<0b11010>; 197class SHILOV_ENC : SHILO_R2_FMT<0b11011>; 198class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 199 200class RDDSP_ENC : RDDSP_FMT<0b10010>; 201class WRDSP_ENC : WRDSP_FMT<0b10011>; 202class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; 203class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; 204class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; 205class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; 206class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; 207class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; 208class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; 209class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>; 210class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>; 211class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>; 212class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>; 213class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>; 214class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>; 215class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>; 216class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>; 217class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>; 218class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>; 219class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>; 220class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>; 221class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>; 222class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>; 223class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>; 224class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>; 225class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>; 226class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; 227class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; 228class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; 229class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; 230class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; 231class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; 232class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; 233class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; 234class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; 235class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; 236class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; 237class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; 238class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; 239class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>; 240class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>; 241class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>; 242class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>; 243class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>; 244class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>; 245class APPEND_ENC : APPEND_FMT<0b00000>; 246class BALIGN_ENC : APPEND_FMT<0b10000>; 247class PREPEND_ENC : APPEND_FMT<0b00001>; 248 249// Instruction desc. 250class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 251 InstrItinClass itin, RegisterClass RCD, 252 RegisterClass RCS, RegisterClass RCT = RCS> { 253 dag OutOperandList = (outs RCD:$rd); 254 dag InOperandList = (ins RCS:$rs, RCT:$rt); 255 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 256 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 257 InstrItinClass Itinerary = itin; 258 list<Register> Defs = [DSPCtrl]; 259} 260 261class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 262 InstrItinClass itin, RegisterClass RCD, 263 RegisterClass RCS = RCD> { 264 dag OutOperandList = (outs RCD:$rd); 265 dag InOperandList = (ins RCS:$rs); 266 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 267 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))]; 268 InstrItinClass Itinerary = itin; 269 list<Register> Defs = [DSPCtrl]; 270} 271 272class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 273 InstrItinClass itin, RegisterClass RCS, 274 RegisterClass RCT = RCS> { 275 dag OutOperandList = (outs); 276 dag InOperandList = (ins RCS:$rs, RCT:$rt); 277 string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); 278 list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)]; 279 InstrItinClass Itinerary = itin; 280 list<Register> Defs = [DSPCtrl]; 281} 282 283class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 284 InstrItinClass itin, RegisterClass RCD, 285 RegisterClass RCS, RegisterClass RCT = RCS> { 286 dag OutOperandList = (outs RCD:$rd); 287 dag InOperandList = (ins RCS:$rs, RCT:$rt); 288 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 289 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 290 InstrItinClass Itinerary = itin; 291 list<Register> Defs = [DSPCtrl]; 292} 293 294class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 295 InstrItinClass itin, RegisterClass RCT, 296 RegisterClass RCS = RCT> { 297 dag OutOperandList = (outs RCT:$rt); 298 dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src); 299 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 300 list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))]; 301 InstrItinClass Itinerary = itin; 302 list<Register> Defs = [DSPCtrl]; 303 string Constraints = "$src = $rt"; 304} 305 306class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 307 InstrItinClass itin, RegisterClass RCD, 308 RegisterClass RCT = RCD> { 309 dag OutOperandList = (outs RCD:$rd); 310 dag InOperandList = (ins RCT:$rt); 311 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 312 list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))]; 313 InstrItinClass Itinerary = itin; 314 list<Register> Defs = [DSPCtrl]; 315} 316 317class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 318 ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> { 319 dag OutOperandList = (outs RC:$rd); 320 dag InOperandList = (ins uimm16:$imm); 321 string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); 322 list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))]; 323 InstrItinClass Itinerary = itin; 324 list<Register> Defs = [DSPCtrl]; 325} 326 327class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 328 InstrItinClass itin, RegisterClass RC> { 329 dag OutOperandList = (outs RC:$rd); 330 dag InOperandList = (ins RC:$rt, CPURegs:$rs_sa); 331 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 332 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))]; 333 InstrItinClass Itinerary = itin; 334 list<Register> Defs = [DSPCtrl]; 335} 336 337class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 338 SDPatternOperator ImmPat, InstrItinClass itin, 339 RegisterClass RC> { 340 dag OutOperandList = (outs RC:$rd); 341 dag InOperandList = (ins RC:$rt, uimm16:$rs_sa); 342 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 343 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))]; 344 InstrItinClass Itinerary = itin; 345 list<Register> Defs = [DSPCtrl]; 346} 347 348class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 349 InstrItinClass itin> { 350 dag OutOperandList = (outs CPURegs:$rd); 351 dag InOperandList = (ins CPURegs:$base, CPURegs:$index); 352 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})"); 353 list<dag> Pattern = [(set CPURegs:$rd, 354 (OpNode CPURegs:$base, CPURegs:$index))]; 355 InstrItinClass Itinerary = itin; 356 list<Register> Defs = [DSPCtrl]; 357 bit mayLoad = 1; 358} 359 360class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 361 InstrItinClass itin, RegisterClass RCD, 362 RegisterClass RCS = RCD, RegisterClass RCT = RCD> { 363 dag OutOperandList = (outs RCD:$rd); 364 dag InOperandList = (ins RCS:$rs, RCT:$rt); 365 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 366 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 367 InstrItinClass Itinerary = itin; 368 list<Register> Defs = [DSPCtrl]; 369} 370 371class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 372 SDPatternOperator ImmOp, InstrItinClass itin> { 373 dag OutOperandList = (outs CPURegs:$rt); 374 dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src); 375 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 376 list<dag> Pattern = [(set CPURegs:$rt, 377 (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))]; 378 InstrItinClass Itinerary = itin; 379 list<Register> Defs = [DSPCtrl]; 380 string Constraints = "$src = $rt"; 381} 382 383class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 384 InstrItinClass itin> { 385 dag OutOperandList = (outs CPURegs:$rt); 386 dag InOperandList = (ins ACRegs:$ac, CPURegs:$shift_rs); 387 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 388 InstrItinClass Itinerary = itin; 389 list<Register> Defs = [DSPCtrl]; 390} 391 392class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 393 InstrItinClass itin> { 394 dag OutOperandList = (outs CPURegs:$rt); 395 dag InOperandList = (ins ACRegs:$ac, uimm16:$shift_rs); 396 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 397 InstrItinClass Itinerary = itin; 398 list<Register> Defs = [DSPCtrl]; 399} 400 401class SHILO_R1_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 402 Instruction realinst> : 403 PseudoDSP<(outs), (ins simm16:$shift), [(OpNode immSExt6:$shift)]>, 404 PseudoInstExpansion<(realinst AC0, simm16:$shift)> { 405 list<Register> Defs = [DSPCtrl, AC0]; 406 list<Register> Uses = [AC0]; 407 InstrItinClass Itinerary = itin; 408} 409 410class SHILO_R1_DESC_BASE<string instr_asm> { 411 dag OutOperandList = (outs ACRegs:$ac); 412 dag InOperandList = (ins simm16:$shift); 413 string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); 414} 415 416class SHILO_R2_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 417 Instruction realinst> : 418 PseudoDSP<(outs), (ins CPURegs:$rs), [(OpNode CPURegs:$rs)]>, 419 PseudoInstExpansion<(realinst AC0, CPURegs:$rs)> { 420 list<Register> Defs = [DSPCtrl, AC0]; 421 list<Register> Uses = [AC0]; 422 InstrItinClass Itinerary = itin; 423} 424 425class SHILO_R2_DESC_BASE<string instr_asm> { 426 dag OutOperandList = (outs ACRegs:$ac); 427 dag InOperandList = (ins CPURegs:$rs); 428 string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); 429} 430 431class MTHLIP_DESC_BASE<string instr_asm> { 432 dag OutOperandList = (outs ACRegs:$ac); 433 dag InOperandList = (ins CPURegs:$rs); 434 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 435} 436 437class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 438 InstrItinClass itin> { 439 dag OutOperandList = (outs CPURegs:$rd); 440 dag InOperandList = (ins uimm16:$mask); 441 string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); 442 list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))]; 443 InstrItinClass Itinerary = itin; 444 list<Register> Uses = [DSPCtrl]; 445} 446 447class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 448 InstrItinClass itin> { 449 dag OutOperandList = (outs); 450 dag InOperandList = (ins CPURegs:$rs, uimm16:$mask); 451 string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); 452 list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)]; 453 InstrItinClass Itinerary = itin; 454 list<Register> Defs = [DSPCtrl]; 455} 456 457class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 458 Instruction realinst> : 459 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), 460 [(OpNode CPURegs:$rs, CPURegs:$rt)]>, 461 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> { 462 list<Register> Defs = [DSPCtrl, AC0]; 463 list<Register> Uses = [AC0]; 464 InstrItinClass Itinerary = itin; 465} 466 467class DPA_W_PH_DESC_BASE<string instr_asm> { 468 dag OutOperandList = (outs ACRegs:$ac); 469 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 470 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 471} 472 473class MULT_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, 474 Instruction realinst> : 475 PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), 476 [(OpNode CPURegs:$rs, CPURegs:$rt)]>, 477 PseudoInstExpansion<(realinst AC0, CPURegs:$rs, CPURegs:$rt)> { 478 list<Register> Defs = [DSPCtrl, AC0]; 479 InstrItinClass Itinerary = itin; 480} 481 482class MULT_DESC_BASE<string instr_asm> { 483 dag OutOperandList = (outs ACRegs:$ac); 484 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 485 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 486} 487 488class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : 489 MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> { 490 list<Register> Uses = [DSPCtrl]; 491 bit usesCustomInserter = 1; 492} 493 494class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { 495 dag OutOperandList = (outs); 496 dag InOperandList = (ins brtarget:$offset); 497 string AsmString = !strconcat(instr_asm, "\t$offset"); 498 InstrItinClass Itinerary = itin; 499 list<Register> Uses = [DSPCtrl]; 500 bit isBranch = 1; 501 bit isTerminator = 1; 502 bit hasDelaySlot = 1; 503} 504 505class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 506 InstrItinClass itin> { 507 dag OutOperandList = (outs CPURegs:$rt); 508 dag InOperandList = (ins CPURegs:$src, CPURegs:$rs); 509 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 510 list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))]; 511 InstrItinClass Itinerary = itin; 512 list<Register> Uses = [DSPCtrl]; 513 string Constraints = "$src = $rt"; 514} 515 516//===----------------------------------------------------------------------===// 517// MIPS DSP Rev 1 518//===----------------------------------------------------------------------===// 519 520// Addition/subtraction 521class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", int_mips_addu_qb, NoItinerary, 522 DSPRegs, DSPRegs>, IsCommutable; 523 524class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, 525 NoItinerary, DSPRegs, DSPRegs>, 526 IsCommutable; 527 528class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", int_mips_subu_qb, NoItinerary, 529 DSPRegs, DSPRegs>; 530 531class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, 532 NoItinerary, DSPRegs, DSPRegs>; 533 534class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", int_mips_addq_ph, NoItinerary, 535 DSPRegs, DSPRegs>, IsCommutable; 536 537class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, 538 NoItinerary, DSPRegs, DSPRegs>, 539 IsCommutable; 540 541class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", int_mips_subq_ph, NoItinerary, 542 DSPRegs, DSPRegs>; 543 544class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, 545 NoItinerary, DSPRegs, DSPRegs>; 546 547class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, 548 NoItinerary, CPURegs, CPURegs>, 549 IsCommutable; 550 551class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, 552 NoItinerary, CPURegs, CPURegs>; 553 554class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary, 555 CPURegs, CPURegs>, IsCommutable; 556 557class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary, 558 CPURegs, CPURegs>, 559 IsCommutable, UseDSPCtrl; 560 561class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, 562 CPURegs, CPURegs>, ClearDefs; 563 564class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, 565 NoItinerary, CPURegs, DSPRegs>, 566 ClearDefs; 567 568// Absolute value 569class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph, 570 NoItinerary, DSPRegs>; 571 572class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w, 573 NoItinerary, CPURegs>; 574 575// Precision reduce/expand 576class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", 577 int_mips_precrq_qb_ph, 578 NoItinerary, DSPRegs, DSPRegs>, 579 ClearDefs; 580 581class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", 582 int_mips_precrq_ph_w, 583 NoItinerary, DSPRegs, CPURegs>, 584 ClearDefs; 585 586class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", 587 int_mips_precrq_rs_ph_w, 588 NoItinerary, DSPRegs, 589 CPURegs>; 590 591class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", 592 int_mips_precrqu_s_qb_ph, 593 NoItinerary, DSPRegs, 594 DSPRegs>; 595 596class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl", 597 int_mips_preceq_w_phl, 598 NoItinerary, CPURegs, DSPRegs>, 599 ClearDefs; 600 601class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr", 602 int_mips_preceq_w_phr, 603 NoItinerary, CPURegs, DSPRegs>, 604 ClearDefs; 605 606class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl", 607 int_mips_precequ_ph_qbl, 608 NoItinerary, DSPRegs>, 609 ClearDefs; 610 611class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr", 612 int_mips_precequ_ph_qbr, 613 NoItinerary, DSPRegs>, 614 ClearDefs; 615 616class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla", 617 int_mips_precequ_ph_qbla, 618 NoItinerary, DSPRegs>, 619 ClearDefs; 620 621class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra", 622 int_mips_precequ_ph_qbra, 623 NoItinerary, DSPRegs>, 624 ClearDefs; 625 626class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl", 627 int_mips_preceu_ph_qbl, 628 NoItinerary, DSPRegs>, 629 ClearDefs; 630 631class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr", 632 int_mips_preceu_ph_qbr, 633 NoItinerary, DSPRegs>, 634 ClearDefs; 635 636class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla", 637 int_mips_preceu_ph_qbla, 638 NoItinerary, DSPRegs>, 639 ClearDefs; 640 641class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra", 642 int_mips_preceu_ph_qbra, 643 NoItinerary, DSPRegs>, 644 ClearDefs; 645 646// Shift 647class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3, 648 NoItinerary, DSPRegs>; 649 650class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb, 651 NoItinerary, DSPRegs>; 652 653class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3, 654 NoItinerary, DSPRegs>, ClearDefs; 655 656class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb, 657 NoItinerary, DSPRegs>, ClearDefs; 658 659class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4, 660 NoItinerary, DSPRegs>; 661 662class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph, 663 NoItinerary, DSPRegs>; 664 665class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph, 666 immZExt4, NoItinerary, DSPRegs>; 667 668class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph, 669 NoItinerary, DSPRegs>; 670 671class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4, 672 NoItinerary, DSPRegs>, ClearDefs; 673 674class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph, 675 NoItinerary, DSPRegs>, ClearDefs; 676 677class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph, 678 immZExt4, NoItinerary, DSPRegs>, 679 ClearDefs; 680 681class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph, 682 NoItinerary, DSPRegs>, ClearDefs; 683 684class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w, 685 immZExt5, NoItinerary, CPURegs>; 686 687class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w, 688 NoItinerary, CPURegs>; 689 690class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w, 691 immZExt5, NoItinerary, CPURegs>, 692 ClearDefs; 693 694class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w, 695 NoItinerary, CPURegs>; 696 697// Multiplication 698class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", 699 int_mips_muleu_s_ph_qbl, 700 NoItinerary, DSPRegs, DSPRegs>; 701 702class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", 703 int_mips_muleu_s_ph_qbr, 704 NoItinerary, DSPRegs, DSPRegs>; 705 706class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", 707 int_mips_muleq_s_w_phl, 708 NoItinerary, CPURegs, DSPRegs>, 709 IsCommutable; 710 711class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", 712 int_mips_muleq_s_w_phr, 713 NoItinerary, CPURegs, DSPRegs>, 714 IsCommutable; 715 716class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, 717 NoItinerary, DSPRegs, DSPRegs>, 718 IsCommutable; 719 720class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph">; 721 722class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl">; 723 724class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr">; 725 726class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl">; 727 728class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr">; 729 730// Dot product with accumulate/subtract 731class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl">; 732 733class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr">; 734 735class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl">; 736 737class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr">; 738 739class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph">; 740 741class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph">; 742 743class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w">; 744 745class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w">; 746 747class MULT_DSP_DESC : MULT_DESC_BASE<"mult">; 748 749class MULTU_DSP_DESC : MULT_DESC_BASE<"multu">; 750 751class MADD_DSP_DESC : MULT_DESC_BASE<"madd">; 752 753class MADDU_DSP_DESC : MULT_DESC_BASE<"maddu">; 754 755class MSUB_DSP_DESC : MULT_DESC_BASE<"msub">; 756 757class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">; 758 759// Comparison 760class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", 761 int_mips_cmpu_eq_qb, NoItinerary, 762 DSPRegs>, IsCommutable; 763 764class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", 765 int_mips_cmpu_lt_qb, NoItinerary, 766 DSPRegs>, IsCommutable; 767 768class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", 769 int_mips_cmpu_le_qb, NoItinerary, 770 DSPRegs>, IsCommutable; 771 772class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", 773 int_mips_cmpgu_eq_qb, 774 NoItinerary, CPURegs, DSPRegs>, 775 IsCommutable; 776 777class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", 778 int_mips_cmpgu_lt_qb, 779 NoItinerary, CPURegs, DSPRegs>, 780 IsCommutable; 781 782class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", 783 int_mips_cmpgu_le_qb, 784 NoItinerary, CPURegs, DSPRegs>, 785 IsCommutable; 786 787class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, 788 NoItinerary, DSPRegs>, 789 IsCommutable; 790 791class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, 792 NoItinerary, DSPRegs>, 793 IsCommutable; 794 795class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, 796 NoItinerary, DSPRegs>, 797 IsCommutable; 798 799// Misc 800class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev, 801 NoItinerary, CPURegs>, ClearDefs; 802 803class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, 804 NoItinerary, DSPRegs, DSPRegs>, 805 ClearDefs; 806 807class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, 808 NoItinerary, DSPRegs>, ClearDefs; 809 810class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, 811 NoItinerary, DSPRegs>, ClearDefs; 812 813class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 814 NoItinerary, DSPRegs, CPURegs>, 815 ClearDefs; 816 817class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 818 NoItinerary, DSPRegs, CPURegs>, 819 ClearDefs; 820 821class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, 822 NoItinerary, DSPRegs, DSPRegs>, 823 ClearDefs, UseDSPCtrl; 824 825class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, 826 NoItinerary, DSPRegs, DSPRegs>, 827 ClearDefs, UseDSPCtrl; 828 829class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs; 830 831class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs; 832 833class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs; 834 835class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; 836 837// Extr 838class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>; 839 840class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>; 841 842class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>; 843 844class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, 845 NoItinerary>; 846 847class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>; 848 849class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, 850 NoItinerary>; 851 852class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, 853 NoItinerary>; 854 855class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, 856 NoItinerary>; 857 858class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, 859 NoItinerary>; 860 861class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, 862 NoItinerary>; 863 864class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, 865 NoItinerary>; 866 867class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, 868 NoItinerary>; 869 870class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo">; 871 872class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">; 873 874class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">; 875 876class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; 877 878class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>; 879 880class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>; 881 882//===----------------------------------------------------------------------===// 883// MIPS DSP Rev 2 884// Addition/subtraction 885class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, 886 DSPRegs, DSPRegs>, IsCommutable; 887 888class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, 889 NoItinerary, DSPRegs, DSPRegs>, 890 IsCommutable; 891 892class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, 893 DSPRegs, DSPRegs>; 894 895class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, 896 NoItinerary, DSPRegs, DSPRegs>; 897 898class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb, 899 NoItinerary, DSPRegs>, 900 ClearDefs, IsCommutable; 901 902class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb, 903 NoItinerary, DSPRegs>, 904 ClearDefs, IsCommutable; 905 906class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb, 907 NoItinerary, DSPRegs>, ClearDefs; 908 909class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb, 910 NoItinerary, DSPRegs>, ClearDefs; 911 912class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph, 913 NoItinerary, DSPRegs>, 914 ClearDefs, IsCommutable; 915 916class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph, 917 NoItinerary, DSPRegs>, 918 ClearDefs, IsCommutable; 919 920class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph, 921 NoItinerary, DSPRegs>, ClearDefs; 922 923class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph, 924 NoItinerary, DSPRegs>, ClearDefs; 925 926class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w, 927 NoItinerary, CPURegs>, 928 ClearDefs, IsCommutable; 929 930class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w, 931 NoItinerary, CPURegs>, 932 ClearDefs, IsCommutable; 933 934class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w, 935 NoItinerary, CPURegs>, ClearDefs; 936 937class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w, 938 NoItinerary, CPURegs>, ClearDefs; 939 940// Comparison 941class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", 942 int_mips_cmpgdu_eq_qb, 943 NoItinerary, CPURegs, DSPRegs>, 944 IsCommutable; 945 946class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", 947 int_mips_cmpgdu_lt_qb, 948 NoItinerary, CPURegs, DSPRegs>, 949 IsCommutable; 950 951class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", 952 int_mips_cmpgdu_le_qb, 953 NoItinerary, CPURegs, DSPRegs>, 954 IsCommutable; 955 956// Absolute 957class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, 958 NoItinerary, DSPRegs>; 959 960// Multiplication 961class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", int_mips_mul_ph, NoItinerary, 962 DSPRegs>, IsCommutable; 963 964class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, 965 NoItinerary, DSPRegs>, IsCommutable; 966 967class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w, 968 NoItinerary, CPURegs>, IsCommutable; 969 970class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w, 971 NoItinerary, CPURegs>, IsCommutable; 972 973class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, 974 NoItinerary, DSPRegs, DSPRegs>, 975 IsCommutable; 976 977// Dot product with accumulate/subtract 978class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph">; 979 980class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph">; 981 982class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph">; 983 984class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph">; 985 986class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph">; 987 988class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph">; 989 990class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph">; 991 992class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph">; 993 994class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">; 995 996// Precision reduce/expand 997class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", 998 int_mips_precr_qb_ph, 999 NoItinerary, DSPRegs, DSPRegs>; 1000 1001class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", 1002 int_mips_precr_sra_ph_w, 1003 NoItinerary, DSPRegs, 1004 CPURegs>, ClearDefs; 1005 1006class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", 1007 int_mips_precr_sra_r_ph_w, 1008 NoItinerary, DSPRegs, 1009 CPURegs>, ClearDefs; 1010 1011// Shift 1012class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3, 1013 NoItinerary, DSPRegs>, ClearDefs; 1014 1015class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb, 1016 NoItinerary, DSPRegs>, ClearDefs; 1017 1018class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb, 1019 immZExt3, NoItinerary, DSPRegs>, 1020 ClearDefs; 1021 1022class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb, 1023 NoItinerary, DSPRegs>, ClearDefs; 1024 1025class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4, 1026 NoItinerary, DSPRegs>, ClearDefs; 1027 1028class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, 1029 NoItinerary, DSPRegs>, ClearDefs; 1030 1031// Misc 1032class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5, 1033 NoItinerary>, ClearDefs; 1034 1035class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2, 1036 NoItinerary>, ClearDefs; 1037 1038class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5, 1039 NoItinerary>, ClearDefs; 1040 1041// Pseudos. 1042def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>; 1043 1044// Instruction defs. 1045// MIPS DSP Rev 1 1046def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC; 1047def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC; 1048def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; 1049def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; 1050def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC; 1051def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; 1052def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; 1053def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; 1054def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC; 1055def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; 1056def ADDSC : ADDSC_ENC, ADDSC_DESC; 1057def ADDWC : ADDWC_ENC, ADDWC_DESC; 1058def MODSUB : MODSUB_ENC, MODSUB_DESC; 1059def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; 1060def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; 1061def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC; 1062def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; 1063def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; 1064def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; 1065def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; 1066def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; 1067def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; 1068def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; 1069def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; 1070def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; 1071def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; 1072def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; 1073def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; 1074def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; 1075def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; 1076def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC; 1077def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC; 1078def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC; 1079def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC; 1080def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC; 1081def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC; 1082def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC; 1083def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; 1084def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC; 1085def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC; 1086def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC; 1087def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC; 1088def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC; 1089def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC; 1090def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC; 1091def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC; 1092def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; 1093def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; 1094def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; 1095def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; 1096def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; 1097def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; 1098def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; 1099def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; 1100def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; 1101def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; 1102def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; 1103def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; 1104def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; 1105def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; 1106def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; 1107def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; 1108def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; 1109def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; 1110def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC; 1111def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC; 1112def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC; 1113def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC; 1114def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC; 1115def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC; 1116def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; 1117def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; 1118def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; 1119def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; 1120def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; 1121def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; 1122def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; 1123def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; 1124def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; 1125def BITREV : BITREV_ENC, BITREV_DESC; 1126def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; 1127def REPL_QB : REPL_QB_ENC, REPL_QB_DESC; 1128def REPL_PH : REPL_PH_ENC, REPL_PH_DESC; 1129def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC; 1130def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC; 1131def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; 1132def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; 1133def LWX : LWX_ENC, LWX_DESC; 1134def LHX : LHX_ENC, LHX_DESC; 1135def LBUX : LBUX_ENC, LBUX_DESC; 1136def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; 1137def INSV : INSV_ENC, INSV_DESC; 1138def EXTP : EXTP_ENC, EXTP_DESC; 1139def EXTPV : EXTPV_ENC, EXTPV_DESC; 1140def EXTPDP : EXTPDP_ENC, EXTPDP_DESC; 1141def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC; 1142def EXTR_W : EXTR_W_ENC, EXTR_W_DESC; 1143def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC; 1144def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC; 1145def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC; 1146def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC; 1147def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; 1148def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC; 1149def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; 1150def SHILO : SHILO_ENC, SHILO_DESC; 1151def SHILOV : SHILOV_ENC, SHILOV_DESC; 1152def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; 1153def RDDSP : RDDSP_ENC, RDDSP_DESC; 1154def WRDSP : WRDSP_ENC, WRDSP_DESC; 1155 1156// MIPS DSP Rev 2 1157let Predicates = [HasDSPR2] in { 1158 1159def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC; 1160def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC; 1161def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; 1162def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; 1163def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; 1164def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; 1165def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; 1166def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; 1167def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC; 1168def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; 1169def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC; 1170def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; 1171def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC; 1172def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; 1173def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC; 1174def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; 1175def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC; 1176def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC; 1177def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; 1178def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; 1179def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; 1180def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; 1181def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; 1182def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; 1183def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; 1184def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC; 1185def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; 1186def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; 1187def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; 1188def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC; 1189def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; 1190def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; 1191def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; 1192def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; 1193def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; 1194def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; 1195def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; 1196def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC; 1197def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC; 1198def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC; 1199def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; 1200def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC; 1201def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC; 1202def APPEND : APPEND_ENC, APPEND_DESC; 1203def BALIGN : BALIGN_ENC, BALIGN_DESC; 1204def PREPEND : PREPEND_ENC, PREPEND_DESC; 1205 1206} 1207 1208// Pseudos. 1209def MULSAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSAQ_S_W_PH, NoItinerary, 1210 MULSAQ_S_W_PH>; 1211def MAQ_S_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHL, NoItinerary, 1212 MAQ_S_W_PHL>; 1213def MAQ_S_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_S_W_PHR, NoItinerary, 1214 MAQ_S_W_PHR>; 1215def MAQ_SA_W_PHL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHL, NoItinerary, 1216 MAQ_SA_W_PHL>; 1217def MAQ_SA_W_PHR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMAQ_SA_W_PHR, NoItinerary, 1218 MAQ_SA_W_PHR>; 1219def DPAU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBL, NoItinerary, 1220 DPAU_H_QBL>; 1221def DPAU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAU_H_QBR, NoItinerary, 1222 DPAU_H_QBR>; 1223def DPSU_H_QBL_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBL, NoItinerary, 1224 DPSU_H_QBL>; 1225def DPSU_H_QBR_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSU_H_QBR, NoItinerary, 1226 DPSU_H_QBR>; 1227def DPAQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_S_W_PH, NoItinerary, 1228 DPAQ_S_W_PH>; 1229def DPSQ_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_S_W_PH, NoItinerary, 1230 DPSQ_S_W_PH>; 1231def DPAQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQ_SA_L_W, NoItinerary, 1232 DPAQ_SA_L_W>; 1233def DPSQ_SA_L_W_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQ_SA_L_W, NoItinerary, 1234 DPSQ_SA_L_W>; 1235 1236def MULT_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULT, NoItinerary, MULT_DSP>, 1237 IsCommutable; 1238def MULTU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMULTU, NoItinerary, MULTU_DSP>, 1239 IsCommutable; 1240def MADD_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADD_DSP, NoItinerary, MADD_DSP>, 1241 IsCommutable, UseAC; 1242def MADDU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMADDU_DSP, NoItinerary, MADDU_DSP>, 1243 IsCommutable, UseAC; 1244def MSUB_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUB_DSP, NoItinerary, MSUB_DSP>, 1245 UseAC; 1246def MSUBU_DSP_PSEUDO : MULT_PSEUDO_BASE<MipsMSUBU_DSP, NoItinerary, MSUBU_DSP>, 1247 UseAC; 1248 1249def SHILO_PSEUDO : SHILO_R1_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILO>; 1250def SHILOV_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsSHILO, NoItinerary, SHILOV>; 1251def MTHLIP_PSEUDO : SHILO_R2_PSEUDO_BASE<MipsMTHLIP, NoItinerary, MTHLIP>; 1252 1253let Predicates = [HasDSPR2] in { 1254 1255def DPA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPA_W_PH, NoItinerary, DPA_W_PH>; 1256def DPS_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPS_W_PH, NoItinerary, DPS_W_PH>; 1257def DPAQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_S_W_PH, NoItinerary, 1258 DPAQX_S_W_PH>; 1259def DPAQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAQX_SA_W_PH, NoItinerary, 1260 DPAQX_SA_W_PH>; 1261def DPAX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPAX_W_PH, NoItinerary, 1262 DPAX_W_PH>; 1263def DPSX_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSX_W_PH, NoItinerary, 1264 DPSX_W_PH>; 1265def DPSQX_S_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_S_W_PH, NoItinerary, 1266 DPSQX_S_W_PH>; 1267def DPSQX_SA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsDPSQX_SA_W_PH, NoItinerary, 1268 DPSQX_SA_W_PH>; 1269def MULSA_W_PH_PSEUDO : DPA_W_PH_PSEUDO_BASE<MipsMULSA_W_PH, NoItinerary, 1270 MULSA_W_PH>; 1271 1272} 1273 1274// Patterns. 1275class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : 1276 Pat<pattern, result>, Requires<[pred]>; 1277 1278class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 1279 RegisterClass SrcRC> : 1280 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), 1281 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; 1282 1283def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>; 1284def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>; 1285def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>; 1286def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>; 1287 1288def : DSPPat<(v2i16 (load addr:$a)), 1289 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1290def : DSPPat<(v4i8 (load addr:$a)), 1291 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1292def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a), 1293 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 1294def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a), 1295 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 1296 1297// Extr patterns. 1298class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : 1299 DSPPat<(i32 (OpNode CPURegs:$rs)), (Instr AC0, CPURegs:$rs)>; 1300 1301class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : 1302 DSPPat<(i32 (OpNode immZExt5:$shift)), (Instr AC0, immZExt5:$shift)>; 1303 1304def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; 1305def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; 1306def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; 1307def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; 1308def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; 1309def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; 1310def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; 1311def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; 1312def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; 1313def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; 1314def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; 1315def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; 1316