MipsDSPInstrInfo.td revision 3d60241c3e86973be281660bc5971c3a46cfdc47
1//===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips DSP ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14// ImmLeaf 15def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>; 16def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>; 17def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>; 18def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>; 19def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>; 20def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>; 21 22// Mips-specific dsp nodes 23def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 24 SDTCisVT<2, untyped>]>; 25def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 26 SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>; 27def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 28 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 29 30class MipsDSPBase<string Opc, SDTypeProfile Prof> : 31 SDNode<!strconcat("MipsISD::", Opc), Prof>; 32 33class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> : 34 SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>; 35 36def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>; 37def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>; 38def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>; 39def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>; 40def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>; 41def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>; 42 43def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>; 44def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>; 45 46def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>; 47def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>; 48def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>; 49def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>; 50def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>; 51 52def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>; 53def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>; 54def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>; 55def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>; 56def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>; 57def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>; 58def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>; 59def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>; 60 61def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>; 62def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>; 63def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>; 64def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>; 65def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>; 66def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>; 67def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>; 68def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>; 69def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>; 70 71def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>; 72def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; 73def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>; 74def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>; 75def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>; 76def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>; 77 78// Flags. 79class UseAC { 80 list<Register> Uses = [AC0]; 81} 82 83class UseDSPCtrl { 84 list<Register> Uses = [DSPCtrl]; 85} 86 87class ClearDefs { 88 list<Register> Defs = []; 89} 90 91// Instruction encoding. 92class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>; 93class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>; 94class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>; 95class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>; 96class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>; 97class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>; 98class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>; 99class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>; 100class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>; 101class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>; 102class ADDSC_ENC : ADDU_QB_FMT<0b10000>; 103class ADDWC_ENC : ADDU_QB_FMT<0b10001>; 104class MODSUB_ENC : ADDU_QB_FMT<0b10010>; 105class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>; 106class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>; 107class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>; 108class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>; 109class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>; 110class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>; 111class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>; 112class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>; 113class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>; 114class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>; 115class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>; 116class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>; 117class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>; 118class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>; 119class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>; 120class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>; 121class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>; 122class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>; 123class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>; 124class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>; 125class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>; 126class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>; 127class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>; 128class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>; 129class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>; 130class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>; 131class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>; 132class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>; 133class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>; 134class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>; 135class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>; 136class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>; 137class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>; 138class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>; 139class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>; 140class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>; 141class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>; 142class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>; 143class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>; 144class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>; 145class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>; 146class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>; 147class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>; 148class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>; 149class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>; 150class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>; 151class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>; 152class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>; 153class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>; 154class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>; 155class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>; 156class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>; 157class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>; 158class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>; 159class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>; 160class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>; 161class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>; 162class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>; 163class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>; 164class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>; 165class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>; 166class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>; 167class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>; 168class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>; 169class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>; 170class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>; 171class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>; 172class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>; 173class REPL_QB_ENC : REPL_FMT<0b00010>; 174class REPL_PH_ENC : REPL_FMT<0b01010>; 175class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>; 176class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>; 177class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>; 178class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>; 179class LWX_ENC : LX_FMT<0b00000>; 180class LHX_ENC : LX_FMT<0b00100>; 181class LBUX_ENC : LX_FMT<0b00110>; 182class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>; 183class INSV_ENC : INSV_FMT<0b001100>; 184 185class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>; 186class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>; 187class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>; 188class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>; 189class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>; 190class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>; 191class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>; 192class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>; 193class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>; 194class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>; 195class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>; 196class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>; 197class SHILO_ENC : SHILO_R1_FMT<0b11010>; 198class SHILOV_ENC : SHILO_R2_FMT<0b11011>; 199class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; 200 201class RDDSP_ENC : RDDSP_FMT<0b10010>; 202class WRDSP_ENC : WRDSP_FMT<0b10011>; 203class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; 204class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; 205class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; 206class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>; 207class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>; 208class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>; 209class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>; 210class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>; 211class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>; 212class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>; 213class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>; 214class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>; 215class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>; 216class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>; 217class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>; 218class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>; 219class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>; 220class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>; 221class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>; 222class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>; 223class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>; 224class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>; 225class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>; 226class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>; 227class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>; 228class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>; 229class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>; 230class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>; 231class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>; 232class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>; 233class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>; 234class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>; 235class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>; 236class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>; 237class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>; 238class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>; 239class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>; 240class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>; 241class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>; 242class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>; 243class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>; 244class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>; 245class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>; 246class APPEND_ENC : APPEND_FMT<0b00000>; 247class BALIGN_ENC : APPEND_FMT<0b10000>; 248class PREPEND_ENC : APPEND_FMT<0b00001>; 249 250// Instruction desc. 251class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 252 InstrItinClass itin, RegisterClass RCD, 253 RegisterClass RCS, RegisterClass RCT = RCS> { 254 dag OutOperandList = (outs RCD:$rd); 255 dag InOperandList = (ins RCS:$rs, RCT:$rt); 256 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 257 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 258 InstrItinClass Itinerary = itin; 259 list<Register> Defs = [DSPCtrl]; 260} 261 262class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 263 InstrItinClass itin, RegisterClass RCD, 264 RegisterClass RCS = RCD> { 265 dag OutOperandList = (outs RCD:$rd); 266 dag InOperandList = (ins RCS:$rs); 267 string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); 268 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))]; 269 InstrItinClass Itinerary = itin; 270 list<Register> Defs = [DSPCtrl]; 271} 272 273class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 274 InstrItinClass itin, RegisterClass RCS, 275 RegisterClass RCT = RCS> { 276 dag OutOperandList = (outs); 277 dag InOperandList = (ins RCS:$rs, RCT:$rt); 278 string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); 279 list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)]; 280 InstrItinClass Itinerary = itin; 281 list<Register> Defs = [DSPCtrl]; 282} 283 284class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 285 InstrItinClass itin, RegisterClass RCD, 286 RegisterClass RCS, RegisterClass RCT = RCS> { 287 dag OutOperandList = (outs RCD:$rd); 288 dag InOperandList = (ins RCS:$rs, RCT:$rt); 289 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 290 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 291 InstrItinClass Itinerary = itin; 292 list<Register> Defs = [DSPCtrl]; 293} 294 295class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 296 InstrItinClass itin, RegisterClass RCT, 297 RegisterClass RCS = RCT> { 298 dag OutOperandList = (outs RCT:$rt); 299 dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src); 300 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 301 list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))]; 302 InstrItinClass Itinerary = itin; 303 list<Register> Defs = [DSPCtrl]; 304 string Constraints = "$src = $rt"; 305} 306 307class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 308 InstrItinClass itin, RegisterClass RCD, 309 RegisterClass RCT = RCD> { 310 dag OutOperandList = (outs RCD:$rd); 311 dag InOperandList = (ins RCT:$rt); 312 string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); 313 list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))]; 314 InstrItinClass Itinerary = itin; 315 list<Register> Defs = [DSPCtrl]; 316} 317 318class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 319 ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> { 320 dag OutOperandList = (outs RC:$rd); 321 dag InOperandList = (ins uimm16:$imm); 322 string AsmString = !strconcat(instr_asm, "\t$rd, $imm"); 323 list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))]; 324 InstrItinClass Itinerary = itin; 325 list<Register> Defs = [DSPCtrl]; 326} 327 328class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 329 InstrItinClass itin, RegisterClass RC> { 330 dag OutOperandList = (outs RC:$rd); 331 dag InOperandList = (ins RC:$rt, CPURegs:$rs_sa); 332 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 333 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))]; 334 InstrItinClass Itinerary = itin; 335 list<Register> Defs = [DSPCtrl]; 336} 337 338class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 339 SDPatternOperator ImmPat, InstrItinClass itin, 340 RegisterClass RC> { 341 dag OutOperandList = (outs RC:$rd); 342 dag InOperandList = (ins RC:$rt, uimm16:$rs_sa); 343 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa"); 344 list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))]; 345 InstrItinClass Itinerary = itin; 346 list<Register> Defs = [DSPCtrl]; 347} 348 349class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 350 InstrItinClass itin> { 351 dag OutOperandList = (outs CPURegs:$rd); 352 dag InOperandList = (ins CPURegs:$base, CPURegs:$index); 353 string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})"); 354 list<dag> Pattern = [(set CPURegs:$rd, 355 (OpNode CPURegs:$base, CPURegs:$index))]; 356 InstrItinClass Itinerary = itin; 357 list<Register> Defs = [DSPCtrl]; 358 bit mayLoad = 1; 359} 360 361class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 362 InstrItinClass itin, RegisterClass RCD, 363 RegisterClass RCS = RCD, RegisterClass RCT = RCD> { 364 dag OutOperandList = (outs RCD:$rd); 365 dag InOperandList = (ins RCS:$rs, RCT:$rt); 366 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); 367 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))]; 368 InstrItinClass Itinerary = itin; 369 list<Register> Defs = [DSPCtrl]; 370} 371 372class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 373 SDPatternOperator ImmOp, InstrItinClass itin> { 374 dag OutOperandList = (outs CPURegs:$rt); 375 dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src); 376 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 377 list<dag> Pattern = [(set CPURegs:$rt, 378 (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))]; 379 InstrItinClass Itinerary = itin; 380 list<Register> Defs = [DSPCtrl]; 381 string Constraints = "$src = $rt"; 382} 383 384class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 385 InstrItinClass itin> { 386 dag OutOperandList = (outs CPURegs:$rt); 387 dag InOperandList = (ins ACRegsDSP:$ac, CPURegs:$shift_rs); 388 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 389 InstrItinClass Itinerary = itin; 390 list<Register> Defs = [DSPCtrl]; 391} 392 393class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 394 InstrItinClass itin> { 395 dag OutOperandList = (outs CPURegs:$rt); 396 dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs); 397 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs"); 398 InstrItinClass Itinerary = itin; 399 list<Register> Defs = [DSPCtrl]; 400} 401 402class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 403 dag OutOperandList = (outs ACRegsDSP:$ac); 404 dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin); 405 string AsmString = !strconcat(instr_asm, "\t$ac, $shift"); 406 list<dag> Pattern = [(set ACRegsDSP:$ac, 407 (OpNode immSExt6:$shift, ACRegsDSP:$acin))]; 408 list<Register> Defs = [DSPCtrl]; 409 string Constraints = "$acin = $ac"; 410} 411 412class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 413 dag OutOperandList = (outs ACRegsDSP:$ac); 414 dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin); 415 string AsmString = !strconcat(instr_asm, "\t$ac, $rs"); 416 list<dag> Pattern = [(set ACRegsDSP:$ac, 417 (OpNode CPURegs:$rs, ACRegsDSP:$acin))]; 418 list<Register> Defs = [DSPCtrl]; 419 string Constraints = "$acin = $ac"; 420} 421 422class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 423 dag OutOperandList = (outs ACRegsDSP:$ac); 424 dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin); 425 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 426 list<dag> Pattern = [(set ACRegsDSP:$ac, 427 (OpNode CPURegs:$rs, ACRegsDSP:$acin))]; 428 list<Register> Uses = [DSPCtrl]; 429 string Constraints = "$acin = $ac"; 430} 431 432class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 433 InstrItinClass itin> { 434 dag OutOperandList = (outs CPURegs:$rd); 435 dag InOperandList = (ins uimm16:$mask); 436 string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); 437 list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))]; 438 InstrItinClass Itinerary = itin; 439 list<Register> Uses = [DSPCtrl]; 440} 441 442class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 443 InstrItinClass itin> { 444 dag OutOperandList = (outs); 445 dag InOperandList = (ins CPURegs:$rs, uimm16:$mask); 446 string AsmString = !strconcat(instr_asm, "\t$rs, $mask"); 447 list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)]; 448 InstrItinClass Itinerary = itin; 449 list<Register> Defs = [DSPCtrl]; 450} 451 452class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> { 453 dag OutOperandList = (outs ACRegsDSP:$ac); 454 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin); 455 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 456 list<dag> Pattern = [(set ACRegsDSP:$ac, 457 (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))]; 458 list<Register> Defs = [DSPCtrl]; 459 string Constraints = "$acin = $ac"; 460} 461 462class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 463 InstrItinClass itin> { 464 dag OutOperandList = (outs ACRegsDSP:$ac); 465 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt); 466 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 467 list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode CPURegs:$rs, CPURegs:$rt))]; 468 InstrItinClass Itinerary = itin; 469 int AddedComplexity = 20; 470 bit isCommutable = 1; 471} 472 473class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 474 InstrItinClass itin> { 475 dag OutOperandList = (outs ACRegsDSP:$ac); 476 dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin); 477 string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); 478 list<dag> Pattern = [(set ACRegsDSP:$ac, 479 (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))]; 480 InstrItinClass Itinerary = itin; 481 int AddedComplexity = 20; 482 string Constraints = "$acin = $ac"; 483} 484 485class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> : 486 MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> { 487 list<Register> Uses = [DSPCtrl]; 488 bit usesCustomInserter = 1; 489} 490 491class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> { 492 dag OutOperandList = (outs); 493 dag InOperandList = (ins brtarget:$offset); 494 string AsmString = !strconcat(instr_asm, "\t$offset"); 495 InstrItinClass Itinerary = itin; 496 list<Register> Uses = [DSPCtrl]; 497 bit isBranch = 1; 498 bit isTerminator = 1; 499 bit hasDelaySlot = 1; 500} 501 502class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 503 InstrItinClass itin> { 504 dag OutOperandList = (outs CPURegs:$rt); 505 dag InOperandList = (ins CPURegs:$src, CPURegs:$rs); 506 string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); 507 list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))]; 508 InstrItinClass Itinerary = itin; 509 list<Register> Uses = [DSPCtrl]; 510 string Constraints = "$src = $rt"; 511} 512 513//===----------------------------------------------------------------------===// 514// MIPS DSP Rev 1 515//===----------------------------------------------------------------------===// 516 517// Addition/subtraction 518class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary, 519 DSPRegs, DSPRegs>, IsCommutable; 520 521class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb, 522 NoItinerary, DSPRegs, DSPRegs>, 523 IsCommutable; 524 525class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary, 526 DSPRegs, DSPRegs>; 527 528class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb, 529 NoItinerary, DSPRegs, DSPRegs>; 530 531class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary, 532 DSPRegs, DSPRegs>, IsCommutable; 533 534class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph, 535 NoItinerary, DSPRegs, DSPRegs>, 536 IsCommutable; 537 538class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary, 539 DSPRegs, DSPRegs>; 540 541class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph, 542 NoItinerary, DSPRegs, DSPRegs>; 543 544class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w, 545 NoItinerary, CPURegs, CPURegs>, 546 IsCommutable; 547 548class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w, 549 NoItinerary, CPURegs, CPURegs>; 550 551class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary, 552 CPURegs, CPURegs>, IsCommutable; 553 554class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary, 555 CPURegs, CPURegs>, 556 IsCommutable, UseDSPCtrl; 557 558class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary, 559 CPURegs, CPURegs>, ClearDefs; 560 561class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb, 562 NoItinerary, CPURegs, DSPRegs>, 563 ClearDefs; 564 565// Absolute value 566class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph, 567 NoItinerary, DSPRegs>; 568 569class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w, 570 NoItinerary, CPURegs>; 571 572// Precision reduce/expand 573class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph", 574 int_mips_precrq_qb_ph, 575 NoItinerary, DSPRegs, DSPRegs>, 576 ClearDefs; 577 578class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w", 579 int_mips_precrq_ph_w, 580 NoItinerary, DSPRegs, CPURegs>, 581 ClearDefs; 582 583class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w", 584 int_mips_precrq_rs_ph_w, 585 NoItinerary, DSPRegs, 586 CPURegs>; 587 588class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph", 589 int_mips_precrqu_s_qb_ph, 590 NoItinerary, DSPRegs, 591 DSPRegs>; 592 593class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl", 594 int_mips_preceq_w_phl, 595 NoItinerary, CPURegs, DSPRegs>, 596 ClearDefs; 597 598class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr", 599 int_mips_preceq_w_phr, 600 NoItinerary, CPURegs, DSPRegs>, 601 ClearDefs; 602 603class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl", 604 int_mips_precequ_ph_qbl, 605 NoItinerary, DSPRegs>, 606 ClearDefs; 607 608class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr", 609 int_mips_precequ_ph_qbr, 610 NoItinerary, DSPRegs>, 611 ClearDefs; 612 613class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla", 614 int_mips_precequ_ph_qbla, 615 NoItinerary, DSPRegs>, 616 ClearDefs; 617 618class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra", 619 int_mips_precequ_ph_qbra, 620 NoItinerary, DSPRegs>, 621 ClearDefs; 622 623class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl", 624 int_mips_preceu_ph_qbl, 625 NoItinerary, DSPRegs>, 626 ClearDefs; 627 628class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr", 629 int_mips_preceu_ph_qbr, 630 NoItinerary, DSPRegs>, 631 ClearDefs; 632 633class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla", 634 int_mips_preceu_ph_qbla, 635 NoItinerary, DSPRegs>, 636 ClearDefs; 637 638class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra", 639 int_mips_preceu_ph_qbra, 640 NoItinerary, DSPRegs>, 641 ClearDefs; 642 643// Shift 644class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3, 645 NoItinerary, DSPRegs>; 646 647class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb, 648 NoItinerary, DSPRegs>; 649 650class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3, 651 NoItinerary, DSPRegs>, ClearDefs; 652 653class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb, 654 NoItinerary, DSPRegs>, ClearDefs; 655 656class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4, 657 NoItinerary, DSPRegs>; 658 659class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph, 660 NoItinerary, DSPRegs>; 661 662class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph, 663 immZExt4, NoItinerary, DSPRegs>; 664 665class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph, 666 NoItinerary, DSPRegs>; 667 668class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4, 669 NoItinerary, DSPRegs>, ClearDefs; 670 671class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph, 672 NoItinerary, DSPRegs>, ClearDefs; 673 674class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph, 675 immZExt4, NoItinerary, DSPRegs>, 676 ClearDefs; 677 678class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph, 679 NoItinerary, DSPRegs>, ClearDefs; 680 681class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w, 682 immZExt5, NoItinerary, CPURegs>; 683 684class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w, 685 NoItinerary, CPURegs>; 686 687class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w, 688 immZExt5, NoItinerary, CPURegs>, 689 ClearDefs; 690 691class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w, 692 NoItinerary, CPURegs>; 693 694// Multiplication 695class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl", 696 int_mips_muleu_s_ph_qbl, 697 NoItinerary, DSPRegs, DSPRegs>; 698 699class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr", 700 int_mips_muleu_s_ph_qbr, 701 NoItinerary, DSPRegs, DSPRegs>; 702 703class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl", 704 int_mips_muleq_s_w_phl, 705 NoItinerary, CPURegs, DSPRegs>, 706 IsCommutable; 707 708class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr", 709 int_mips_muleq_s_w_phr, 710 NoItinerary, CPURegs, DSPRegs>, 711 IsCommutable; 712 713class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph, 714 NoItinerary, DSPRegs, DSPRegs>, 715 IsCommutable; 716 717class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph", 718 MipsMULSAQ_S_W_PH>; 719 720class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>; 721 722class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>; 723 724class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>; 725 726class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>; 727 728// Dot product with accumulate/subtract 729class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>; 730 731class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>; 732 733class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>; 734 735class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>; 736 737class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>; 738 739class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>; 740 741class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>; 742 743class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>; 744 745class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>; 746class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>; 747class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>; 748class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>; 749class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>; 750class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>; 751 752// Comparison 753class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb", 754 int_mips_cmpu_eq_qb, NoItinerary, 755 DSPRegs>, IsCommutable; 756 757class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb", 758 int_mips_cmpu_lt_qb, NoItinerary, 759 DSPRegs>, IsCommutable; 760 761class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb", 762 int_mips_cmpu_le_qb, NoItinerary, 763 DSPRegs>, IsCommutable; 764 765class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb", 766 int_mips_cmpgu_eq_qb, 767 NoItinerary, CPURegs, DSPRegs>, 768 IsCommutable; 769 770class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb", 771 int_mips_cmpgu_lt_qb, 772 NoItinerary, CPURegs, DSPRegs>, 773 IsCommutable; 774 775class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb", 776 int_mips_cmpgu_le_qb, 777 NoItinerary, CPURegs, DSPRegs>, 778 IsCommutable; 779 780class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph, 781 NoItinerary, DSPRegs>, 782 IsCommutable; 783 784class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph, 785 NoItinerary, DSPRegs>, 786 IsCommutable; 787 788class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph, 789 NoItinerary, DSPRegs>, 790 IsCommutable; 791 792// Misc 793class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev, 794 NoItinerary, CPURegs>, ClearDefs; 795 796class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph, 797 NoItinerary, DSPRegs, DSPRegs>, 798 ClearDefs; 799 800class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8, 801 NoItinerary, DSPRegs>, ClearDefs; 802 803class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10, 804 NoItinerary, DSPRegs>, ClearDefs; 805 806class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 807 NoItinerary, DSPRegs, CPURegs>, 808 ClearDefs; 809 810class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 811 NoItinerary, DSPRegs, CPURegs>, 812 ClearDefs; 813 814class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb, 815 NoItinerary, DSPRegs, DSPRegs>, 816 ClearDefs, UseDSPCtrl; 817 818class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph, 819 NoItinerary, DSPRegs, DSPRegs>, 820 ClearDefs, UseDSPCtrl; 821 822class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs; 823 824class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs; 825 826class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs; 827 828class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; 829 830// Extr 831class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>; 832 833class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>; 834 835class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>; 836 837class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP, 838 NoItinerary>; 839 840class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>; 841 842class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W, 843 NoItinerary>; 844 845class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W, 846 NoItinerary>; 847 848class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, 849 NoItinerary>; 850 851class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, 852 NoItinerary>; 853 854class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, 855 NoItinerary>; 856 857class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H, 858 NoItinerary>; 859 860class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, 861 NoItinerary>; 862 863class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>; 864 865class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>; 866 867class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>; 868 869class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; 870 871class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>; 872 873class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>; 874 875//===----------------------------------------------------------------------===// 876// MIPS DSP Rev 2 877// Addition/subtraction 878class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary, 879 DSPRegs, DSPRegs>, IsCommutable; 880 881class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph, 882 NoItinerary, DSPRegs, DSPRegs>, 883 IsCommutable; 884 885class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary, 886 DSPRegs, DSPRegs>; 887 888class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph, 889 NoItinerary, DSPRegs, DSPRegs>; 890 891class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb, 892 NoItinerary, DSPRegs>, 893 ClearDefs, IsCommutable; 894 895class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb, 896 NoItinerary, DSPRegs>, 897 ClearDefs, IsCommutable; 898 899class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb, 900 NoItinerary, DSPRegs>, ClearDefs; 901 902class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb, 903 NoItinerary, DSPRegs>, ClearDefs; 904 905class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph, 906 NoItinerary, DSPRegs>, 907 ClearDefs, IsCommutable; 908 909class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph, 910 NoItinerary, DSPRegs>, 911 ClearDefs, IsCommutable; 912 913class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph, 914 NoItinerary, DSPRegs>, ClearDefs; 915 916class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph, 917 NoItinerary, DSPRegs>, ClearDefs; 918 919class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w, 920 NoItinerary, CPURegs>, 921 ClearDefs, IsCommutable; 922 923class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w, 924 NoItinerary, CPURegs>, 925 ClearDefs, IsCommutable; 926 927class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w, 928 NoItinerary, CPURegs>, ClearDefs; 929 930class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w, 931 NoItinerary, CPURegs>, ClearDefs; 932 933// Comparison 934class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb", 935 int_mips_cmpgdu_eq_qb, 936 NoItinerary, CPURegs, DSPRegs>, 937 IsCommutable; 938 939class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb", 940 int_mips_cmpgdu_lt_qb, 941 NoItinerary, CPURegs, DSPRegs>, 942 IsCommutable; 943 944class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb", 945 int_mips_cmpgdu_le_qb, 946 NoItinerary, CPURegs, DSPRegs>, 947 IsCommutable; 948 949// Absolute 950class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb, 951 NoItinerary, DSPRegs>; 952 953// Multiplication 954class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary, 955 DSPRegs>, IsCommutable; 956 957class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph, 958 NoItinerary, DSPRegs>, IsCommutable; 959 960class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w, 961 NoItinerary, CPURegs>, IsCommutable; 962 963class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w, 964 NoItinerary, CPURegs>, IsCommutable; 965 966class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph, 967 NoItinerary, DSPRegs, DSPRegs>, 968 IsCommutable; 969 970// Dot product with accumulate/subtract 971class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>; 972 973class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>; 974 975class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>; 976 977class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph", 978 MipsDPAQX_SA_W_PH>; 979 980class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>; 981 982class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>; 983 984class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>; 985 986class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph", 987 MipsDPSQX_SA_W_PH>; 988 989class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>; 990 991// Precision reduce/expand 992class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph", 993 int_mips_precr_qb_ph, 994 NoItinerary, DSPRegs, DSPRegs>; 995 996class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w", 997 int_mips_precr_sra_ph_w, 998 NoItinerary, DSPRegs, 999 CPURegs>, ClearDefs; 1000 1001class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w", 1002 int_mips_precr_sra_r_ph_w, 1003 NoItinerary, DSPRegs, 1004 CPURegs>, ClearDefs; 1005 1006// Shift 1007class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3, 1008 NoItinerary, DSPRegs>, ClearDefs; 1009 1010class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb, 1011 NoItinerary, DSPRegs>, ClearDefs; 1012 1013class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb, 1014 immZExt3, NoItinerary, DSPRegs>, 1015 ClearDefs; 1016 1017class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb, 1018 NoItinerary, DSPRegs>, ClearDefs; 1019 1020class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4, 1021 NoItinerary, DSPRegs>, ClearDefs; 1022 1023class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph, 1024 NoItinerary, DSPRegs>, ClearDefs; 1025 1026// Misc 1027class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5, 1028 NoItinerary>, ClearDefs; 1029 1030class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2, 1031 NoItinerary>, ClearDefs; 1032 1033class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5, 1034 NoItinerary>, ClearDefs; 1035 1036// Pseudos. 1037def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>; 1038 1039// Instruction defs. 1040// MIPS DSP Rev 1 1041def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC; 1042def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC; 1043def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC; 1044def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC; 1045def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC; 1046def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC; 1047def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC; 1048def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC; 1049def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC; 1050def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC; 1051def ADDSC : ADDSC_ENC, ADDSC_DESC; 1052def ADDWC : ADDWC_ENC, ADDWC_DESC; 1053def MODSUB : MODSUB_ENC, MODSUB_DESC; 1054def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; 1055def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; 1056def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC; 1057def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; 1058def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; 1059def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; 1060def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; 1061def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; 1062def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; 1063def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; 1064def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; 1065def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; 1066def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; 1067def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; 1068def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; 1069def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; 1070def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; 1071def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC; 1072def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC; 1073def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC; 1074def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC; 1075def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC; 1076def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC; 1077def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC; 1078def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; 1079def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC; 1080def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC; 1081def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC; 1082def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC; 1083def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC; 1084def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC; 1085def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC; 1086def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC; 1087def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC; 1088def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC; 1089def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC; 1090def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC; 1091def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC; 1092def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC; 1093def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC; 1094def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC; 1095def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC; 1096def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC; 1097def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC; 1098def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC; 1099def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC; 1100def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC; 1101def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC; 1102def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC; 1103def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC; 1104def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC; 1105def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC; 1106def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC; 1107def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC; 1108def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC; 1109def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC; 1110def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC; 1111def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; 1112def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; 1113def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; 1114def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; 1115def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; 1116def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; 1117def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; 1118def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; 1119def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; 1120def BITREV : BITREV_ENC, BITREV_DESC; 1121def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC; 1122def REPL_QB : REPL_QB_ENC, REPL_QB_DESC; 1123def REPL_PH : REPL_PH_ENC, REPL_PH_DESC; 1124def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC; 1125def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC; 1126def PICK_QB : PICK_QB_ENC, PICK_QB_DESC; 1127def PICK_PH : PICK_PH_ENC, PICK_PH_DESC; 1128def LWX : LWX_ENC, LWX_DESC; 1129def LHX : LHX_ENC, LHX_DESC; 1130def LBUX : LBUX_ENC, LBUX_DESC; 1131def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; 1132def INSV : INSV_ENC, INSV_DESC; 1133def EXTP : EXTP_ENC, EXTP_DESC; 1134def EXTPV : EXTPV_ENC, EXTPV_DESC; 1135def EXTPDP : EXTPDP_ENC, EXTPDP_DESC; 1136def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC; 1137def EXTR_W : EXTR_W_ENC, EXTR_W_DESC; 1138def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC; 1139def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC; 1140def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC; 1141def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC; 1142def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC; 1143def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC; 1144def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; 1145def SHILO : SHILO_ENC, SHILO_DESC; 1146def SHILOV : SHILOV_ENC, SHILOV_DESC; 1147def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; 1148def RDDSP : RDDSP_ENC, RDDSP_DESC; 1149def WRDSP : WRDSP_ENC, WRDSP_DESC; 1150 1151// MIPS DSP Rev 2 1152let Predicates = [HasDSPR2] in { 1153 1154def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC; 1155def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC; 1156def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC; 1157def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC; 1158def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC; 1159def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC; 1160def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC; 1161def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC; 1162def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC; 1163def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC; 1164def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC; 1165def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC; 1166def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC; 1167def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC; 1168def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC; 1169def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC; 1170def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC; 1171def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC; 1172def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC; 1173def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC; 1174def MUL_PH : MUL_PH_ENC, MUL_PH_DESC; 1175def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC; 1176def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC; 1177def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC; 1178def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC; 1179def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC; 1180def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC; 1181def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC; 1182def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC; 1183def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC; 1184def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC; 1185def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC; 1186def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC; 1187def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC; 1188def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC; 1189def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC; 1190def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC; 1191def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC; 1192def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC; 1193def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC; 1194def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC; 1195def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC; 1196def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC; 1197def APPEND : APPEND_ENC, APPEND_DESC; 1198def BALIGN : BALIGN_ENC, BALIGN_DESC; 1199def PREPEND : PREPEND_ENC, PREPEND_DESC; 1200 1201} 1202 1203// Pseudos. 1204/// Pseudo instructions for loading, storing and copying accumulator registers. 1205let isPseudo = 1 in { 1206 defm LOAD_AC_DSP : LoadM<"load_ac_dsp", ACRegsDSP>; 1207 defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>; 1208} 1209 1210def COPY_AC_DSP : PseudoSE<(outs ACRegsDSP:$dst), (ins ACRegsDSP:$src), []>; 1211 1212// Patterns. 1213class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> : 1214 Pat<pattern, result>, Requires<[pred]>; 1215 1216class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC, 1217 RegisterClass SrcRC> : 1218 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))), 1219 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>; 1220 1221def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>; 1222def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>; 1223def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>; 1224def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>; 1225 1226def : DSPPat<(v2i16 (load addr:$a)), 1227 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1228def : DSPPat<(v4i8 (load addr:$a)), 1229 (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>; 1230def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a), 1231 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 1232def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a), 1233 (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>; 1234 1235// Binary operations. 1236class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, 1237 Predicate Pred = HasDSP> : 1238 DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>; 1239 1240def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>; 1241def : DSPBinPat<ADDQ_PH, v2i16, add>; 1242def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>; 1243def : DSPBinPat<SUBQ_PH, v2i16, sub>; 1244def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>; 1245def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>; 1246def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>; 1247def : DSPBinPat<ADDU_QB, v4i8, add>; 1248def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>; 1249def : DSPBinPat<SUBU_QB, v4i8, sub>; 1250def : DSPBinPat<ADDSC, i32, int_mips_addsc>; 1251def : DSPBinPat<ADDSC, i32, addc>; 1252def : DSPBinPat<ADDWC, i32, int_mips_addwc>; 1253def : DSPBinPat<ADDWC, i32, adde>; 1254 1255// Extr patterns. 1256class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> : 1257 DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)), 1258 (Instr ACRegsDSP:$ac, CPURegs:$rs)>; 1259 1260class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> : 1261 DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)), 1262 (Instr ACRegsDSP:$ac, immZExt5:$shift)>; 1263 1264def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>; 1265def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>; 1266def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>; 1267def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>; 1268def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>; 1269def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>; 1270def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>; 1271def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>; 1272def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>; 1273def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>; 1274def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>; 1275def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>; 1276 1277// mflo/hi patterns. 1278let AddedComplexity = 20 in 1279def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)), 1280 (EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>; 1281 1282// Indexed load patterns. 1283class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> : 1284 DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))), 1285 (Instr i32:$base, i32:$index)>; 1286 1287let AddedComplexity = 20 in { 1288 def : IndexedLoadPat<zextloadi8, LBUX>; 1289 def : IndexedLoadPat<sextloadi16, LHX>; 1290 def : IndexedLoadPat<load, LWX>; 1291} 1292